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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s3; RUN: llc -mtriple=amdgcn -mcpu=tonga -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s4; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -mattr=-flat-for-global < %s | FileCheck -enable-var-scope -check-prefixes=GCN,GFX9 %s5 6declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone7declare i32 @llvm.amdgcn.workitem.id.y() nounwind readnone8 9define amdgpu_kernel void @test_umul24_i32(ptr addrspace(1) %out, i32 %a, i32 %b) {10; SI-LABEL: test_umul24_i32:11; SI: ; %bb.0: ; %entry12; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x913; SI-NEXT: s_waitcnt lgkmcnt(0)14; SI-NEXT: s_mov_b64 s[4:5], s[2:3]15; SI-NEXT: s_mov_b32 s3, 0xf00016; SI-NEXT: s_and_b32 s2, s4, 0xffffff17; SI-NEXT: s_and_b32 s4, s5, 0xffffff18; SI-NEXT: s_mul_i32 s4, s2, s419; SI-NEXT: s_mov_b32 s2, -120; SI-NEXT: v_mov_b32_e32 v0, s421; SI-NEXT: buffer_store_dword v0, off, s[0:3], 022; SI-NEXT: s_endpgm23;24; VI-LABEL: test_umul24_i32:25; VI: ; %bb.0: ; %entry26; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2427; VI-NEXT: s_waitcnt lgkmcnt(0)28; VI-NEXT: s_mov_b64 s[4:5], s[2:3]29; VI-NEXT: s_and_b32 s4, s4, 0xffffff30; VI-NEXT: s_and_b32 s5, s5, 0xffffff31; VI-NEXT: s_mul_i32 s4, s4, s532; VI-NEXT: s_mov_b32 s3, 0xf00033; VI-NEXT: s_mov_b32 s2, -134; VI-NEXT: v_mov_b32_e32 v0, s435; VI-NEXT: buffer_store_dword v0, off, s[0:3], 036; VI-NEXT: s_endpgm37;38; GFX9-LABEL: test_umul24_i32:39; GFX9: ; %bb.0: ; %entry40; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2441; GFX9-NEXT: s_waitcnt lgkmcnt(0)42; GFX9-NEXT: s_mov_b64 s[4:5], s[2:3]43; GFX9-NEXT: s_and_b32 s4, s4, 0xffffff44; GFX9-NEXT: s_and_b32 s5, s5, 0xffffff45; GFX9-NEXT: s_mul_i32 s4, s4, s546; GFX9-NEXT: s_mov_b32 s3, 0xf00047; GFX9-NEXT: s_mov_b32 s2, -148; GFX9-NEXT: v_mov_b32_e32 v0, s449; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 050; GFX9-NEXT: s_endpgm51entry:52 %0 = shl i32 %a, 853 %a_24 = lshr i32 %0, 854 %1 = shl i32 %b, 855 %b_24 = lshr i32 %1, 856 %2 = mul i32 %a_24, %b_2457 store i32 %2, ptr addrspace(1) %out58 ret void59}60 61define amdgpu_kernel void @test_umul24_i16_sext(ptr addrspace(1) %out, i16 %a, i16 %b) {62; SI-LABEL: test_umul24_i16_sext:63; SI: ; %bb.0: ; %entry64; SI-NEXT: s_load_dword s2, s[4:5], 0xb65; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x966; SI-NEXT: s_mov_b32 s3, 0xf00067; SI-NEXT: s_waitcnt lgkmcnt(0)68; SI-NEXT: s_lshr_b32 s4, s2, 1669; SI-NEXT: s_mul_i32 s2, s2, s470; SI-NEXT: s_sext_i32_i16 s4, s271; SI-NEXT: s_mov_b32 s2, -172; SI-NEXT: v_mov_b32_e32 v0, s473; SI-NEXT: buffer_store_dword v0, off, s[0:3], 074; SI-NEXT: s_endpgm75;76; VI-LABEL: test_umul24_i16_sext:77; VI: ; %bb.0: ; %entry78; VI-NEXT: s_load_dword s6, s[4:5], 0x2c79; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2480; VI-NEXT: s_mov_b32 s3, 0xf00081; VI-NEXT: s_mov_b32 s2, -182; VI-NEXT: s_waitcnt lgkmcnt(0)83; VI-NEXT: s_lshr_b32 s4, s6, 1684; VI-NEXT: s_mul_i32 s6, s6, s485; VI-NEXT: s_sext_i32_i16 s4, s686; VI-NEXT: v_mov_b32_e32 v0, s487; VI-NEXT: buffer_store_dword v0, off, s[0:3], 088; VI-NEXT: s_endpgm89;90; GFX9-LABEL: test_umul24_i16_sext:91; GFX9: ; %bb.0: ; %entry92; GFX9-NEXT: s_load_dword s6, s[4:5], 0x2c93; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2494; GFX9-NEXT: s_mov_b32 s3, 0xf00095; GFX9-NEXT: s_mov_b32 s2, -196; GFX9-NEXT: s_waitcnt lgkmcnt(0)97; GFX9-NEXT: s_lshr_b32 s4, s6, 1698; GFX9-NEXT: s_mul_i32 s6, s6, s499; GFX9-NEXT: s_sext_i32_i16 s4, s6100; GFX9-NEXT: v_mov_b32_e32 v0, s4101; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0102; GFX9-NEXT: s_endpgm103entry:104 %mul = mul i16 %a, %b105 %ext = sext i16 %mul to i32106 store i32 %ext, ptr addrspace(1) %out107 ret void108}109 110define amdgpu_kernel void @test_umul24_i16_vgpr_sext(ptr addrspace(1) %out, ptr addrspace(1) %in) {111; SI-LABEL: test_umul24_i16_vgpr_sext:112; SI: ; %bb.0:113; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9114; SI-NEXT: s_mov_b32 s7, 0xf000115; SI-NEXT: s_mov_b32 s10, 0116; SI-NEXT: v_lshlrev_b32_e32 v2, 1, v0117; SI-NEXT: v_mov_b32_e32 v3, 0118; SI-NEXT: v_lshlrev_b32_e32 v0, 1, v1119; SI-NEXT: s_mov_b32 s11, s7120; SI-NEXT: v_mov_b32_e32 v1, v3121; SI-NEXT: s_waitcnt lgkmcnt(0)122; SI-NEXT: s_mov_b64 s[8:9], s[2:3]123; SI-NEXT: buffer_load_ushort v2, v[2:3], s[8:11], 0 addr64124; SI-NEXT: buffer_load_ushort v0, v[0:1], s[8:11], 0 addr64125; SI-NEXT: s_mov_b32 s6, -1126; SI-NEXT: s_mov_b32 s4, s0127; SI-NEXT: s_mov_b32 s5, s1128; SI-NEXT: s_waitcnt vmcnt(0)129; SI-NEXT: v_mul_u32_u24_e32 v0, v2, v0130; SI-NEXT: v_bfe_i32 v0, v0, 0, 16131; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0132; SI-NEXT: s_endpgm133;134; VI-LABEL: test_umul24_i16_vgpr_sext:135; VI: ; %bb.0:136; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24137; VI-NEXT: v_lshlrev_b32_e32 v0, 1, v0138; VI-NEXT: s_waitcnt lgkmcnt(0)139; VI-NEXT: v_mov_b32_e32 v3, s3140; VI-NEXT: v_add_u32_e32 v2, vcc, s2, v0141; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc142; VI-NEXT: v_lshlrev_b32_e32 v0, 1, v1143; VI-NEXT: v_mov_b32_e32 v1, s3144; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0145; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc146; VI-NEXT: flat_load_ushort v2, v[2:3]147; VI-NEXT: flat_load_ushort v0, v[0:1]148; VI-NEXT: s_mov_b32 s3, 0xf000149; VI-NEXT: s_mov_b32 s2, -1150; VI-NEXT: s_waitcnt vmcnt(0)151; VI-NEXT: v_mul_lo_u16_e32 v0, v2, v0152; VI-NEXT: v_bfe_i32 v0, v0, 0, 16153; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0154; VI-NEXT: s_endpgm155;156; GFX9-LABEL: test_umul24_i16_vgpr_sext:157; GFX9: ; %bb.0:158; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24159; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v0160; GFX9-NEXT: v_lshlrev_b32_e32 v1, 1, v1161; GFX9-NEXT: s_waitcnt lgkmcnt(0)162; GFX9-NEXT: global_load_ushort v2, v0, s[2:3]163; GFX9-NEXT: global_load_ushort v3, v1, s[2:3]164; GFX9-NEXT: s_mov_b32 s3, 0xf000165; GFX9-NEXT: s_mov_b32 s2, -1166; GFX9-NEXT: s_waitcnt vmcnt(0)167; GFX9-NEXT: v_mul_lo_u16_e32 v0, v2, v3168; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 16169; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0170; GFX9-NEXT: s_endpgm171 %tid.x = call i32 @llvm.amdgcn.workitem.id.x()172 %tid.y = call i32 @llvm.amdgcn.workitem.id.y()173 %ptr_a = getelementptr i16, ptr addrspace(1) %in, i32 %tid.x174 %ptr_b = getelementptr i16, ptr addrspace(1) %in, i32 %tid.y175 %a = load i16, ptr addrspace(1) %ptr_a176 %b = load i16, ptr addrspace(1) %ptr_b177 %mul = mul i16 %a, %b178 %val = sext i16 %mul to i32179 store i32 %val, ptr addrspace(1) %out180 ret void181}182 183define amdgpu_kernel void @test_umul24_i16(ptr addrspace(1) %out, i16 %a, i16 %b) {184; SI-LABEL: test_umul24_i16:185; SI: ; %bb.0: ; %entry186; SI-NEXT: s_load_dword s2, s[4:5], 0xb187; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9188; SI-NEXT: s_mov_b32 s3, 0xf000189; SI-NEXT: s_waitcnt lgkmcnt(0)190; SI-NEXT: s_lshr_b32 s4, s2, 16191; SI-NEXT: s_mul_i32 s2, s2, s4192; SI-NEXT: s_and_b32 s4, s2, 0xffff193; SI-NEXT: s_mov_b32 s2, -1194; SI-NEXT: v_mov_b32_e32 v0, s4195; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0196; SI-NEXT: s_endpgm197;198; VI-LABEL: test_umul24_i16:199; VI: ; %bb.0: ; %entry200; VI-NEXT: s_load_dword s6, s[4:5], 0x2c201; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24202; VI-NEXT: s_mov_b32 s3, 0xf000203; VI-NEXT: s_mov_b32 s2, -1204; VI-NEXT: s_waitcnt lgkmcnt(0)205; VI-NEXT: s_lshr_b32 s4, s6, 16206; VI-NEXT: s_mul_i32 s6, s6, s4207; VI-NEXT: s_and_b32 s4, s6, 0xffff208; VI-NEXT: v_mov_b32_e32 v0, s4209; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0210; VI-NEXT: s_endpgm211;212; GFX9-LABEL: test_umul24_i16:213; GFX9: ; %bb.0: ; %entry214; GFX9-NEXT: s_load_dword s6, s[4:5], 0x2c215; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24216; GFX9-NEXT: s_mov_b32 s3, 0xf000217; GFX9-NEXT: s_mov_b32 s2, -1218; GFX9-NEXT: s_waitcnt lgkmcnt(0)219; GFX9-NEXT: s_lshr_b32 s4, s6, 16220; GFX9-NEXT: s_mul_i32 s6, s6, s4221; GFX9-NEXT: s_and_b32 s4, s6, 0xffff222; GFX9-NEXT: v_mov_b32_e32 v0, s4223; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0224; GFX9-NEXT: s_endpgm225entry:226 %mul = mul i16 %a, %b227 %ext = zext i16 %mul to i32228 store i32 %ext, ptr addrspace(1) %out229 ret void230}231 232define amdgpu_kernel void @test_umul24_i16_vgpr(ptr addrspace(1) %out, ptr addrspace(1) %in) {233; SI-LABEL: test_umul24_i16_vgpr:234; SI: ; %bb.0:235; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9236; SI-NEXT: s_mov_b32 s7, 0xf000237; SI-NEXT: s_mov_b32 s10, 0238; SI-NEXT: v_lshlrev_b32_e32 v2, 1, v0239; SI-NEXT: v_mov_b32_e32 v3, 0240; SI-NEXT: v_lshlrev_b32_e32 v0, 1, v1241; SI-NEXT: s_mov_b32 s11, s7242; SI-NEXT: v_mov_b32_e32 v1, v3243; SI-NEXT: s_waitcnt lgkmcnt(0)244; SI-NEXT: s_mov_b64 s[8:9], s[2:3]245; SI-NEXT: buffer_load_ushort v2, v[2:3], s[8:11], 0 addr64246; SI-NEXT: buffer_load_ushort v0, v[0:1], s[8:11], 0 addr64247; SI-NEXT: s_mov_b32 s6, -1248; SI-NEXT: s_mov_b32 s4, s0249; SI-NEXT: s_mov_b32 s5, s1250; SI-NEXT: s_waitcnt vmcnt(0)251; SI-NEXT: v_mul_u32_u24_e32 v0, v2, v0252; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0253; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0254; SI-NEXT: s_endpgm255;256; VI-LABEL: test_umul24_i16_vgpr:257; VI: ; %bb.0:258; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24259; VI-NEXT: v_lshlrev_b32_e32 v0, 1, v0260; VI-NEXT: s_waitcnt lgkmcnt(0)261; VI-NEXT: v_mov_b32_e32 v3, s3262; VI-NEXT: v_add_u32_e32 v2, vcc, s2, v0263; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc264; VI-NEXT: v_lshlrev_b32_e32 v0, 1, v1265; VI-NEXT: v_mov_b32_e32 v1, s3266; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0267; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc268; VI-NEXT: flat_load_ushort v2, v[2:3]269; VI-NEXT: flat_load_ushort v0, v[0:1]270; VI-NEXT: s_mov_b32 s3, 0xf000271; VI-NEXT: s_mov_b32 s2, -1272; VI-NEXT: s_waitcnt vmcnt(0)273; VI-NEXT: v_mul_lo_u16_e32 v0, v2, v0274; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0275; VI-NEXT: s_endpgm276;277; GFX9-LABEL: test_umul24_i16_vgpr:278; GFX9: ; %bb.0:279; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24280; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v0281; GFX9-NEXT: v_lshlrev_b32_e32 v1, 1, v1282; GFX9-NEXT: s_waitcnt lgkmcnt(0)283; GFX9-NEXT: global_load_ushort v2, v0, s[2:3]284; GFX9-NEXT: global_load_ushort v3, v1, s[2:3]285; GFX9-NEXT: s_mov_b32 s3, 0xf000286; GFX9-NEXT: s_mov_b32 s2, -1287; GFX9-NEXT: s_waitcnt vmcnt(0)288; GFX9-NEXT: v_mul_lo_u16_e32 v0, v2, v3289; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0290; GFX9-NEXT: s_endpgm291 %tid.x = call i32 @llvm.amdgcn.workitem.id.x()292 %tid.y = call i32 @llvm.amdgcn.workitem.id.y()293 %ptr_a = getelementptr i16, ptr addrspace(1) %in, i32 %tid.x294 %ptr_b = getelementptr i16, ptr addrspace(1) %in, i32 %tid.y295 %a = load i16, ptr addrspace(1) %ptr_a296 %b = load i16, ptr addrspace(1) %ptr_b297 %mul = mul i16 %a, %b298 %val = zext i16 %mul to i32299 store i32 %val, ptr addrspace(1) %out300 ret void301}302 303define amdgpu_kernel void @test_umul24_i8_vgpr(ptr addrspace(1) %out, ptr addrspace(1) %a, ptr addrspace(1) %b) {304; SI-LABEL: test_umul24_i8_vgpr:305; SI: ; %bb.0: ; %entry306; SI-NEXT: v_mov_b32_e32 v3, v0307; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9308; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd309; SI-NEXT: s_mov_b32 s11, 0xf000310; SI-NEXT: v_mov_b32_e32 v4, 0311; SI-NEXT: s_mov_b32 s14, 0312; SI-NEXT: s_mov_b32 s15, s11313; SI-NEXT: v_mov_b32_e32 v2, v4314; SI-NEXT: s_mov_b64 s[6:7], s[14:15]315; SI-NEXT: s_waitcnt lgkmcnt(0)316; SI-NEXT: s_mov_b64 s[12:13], s[2:3]317; SI-NEXT: buffer_load_ubyte v0, v[3:4], s[12:15], 0 addr64318; SI-NEXT: buffer_load_ubyte v1, v[1:2], s[4:7], 0 addr64319; SI-NEXT: s_mov_b32 s10, -1320; SI-NEXT: s_mov_b32 s8, s0321; SI-NEXT: s_mov_b32 s9, s1322; SI-NEXT: s_waitcnt vmcnt(0)323; SI-NEXT: v_mul_u32_u24_e32 v0, v0, v1324; SI-NEXT: v_bfe_i32 v0, v0, 0, 8325; SI-NEXT: buffer_store_dword v0, off, s[8:11], 0326; SI-NEXT: s_endpgm327;328; VI-LABEL: test_umul24_i8_vgpr:329; VI: ; %bb.0: ; %entry330; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24331; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34332; VI-NEXT: s_waitcnt lgkmcnt(0)333; VI-NEXT: v_mov_b32_e32 v3, s3334; VI-NEXT: v_add_u32_e32 v2, vcc, s2, v0335; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc336; VI-NEXT: v_mov_b32_e32 v4, s5337; VI-NEXT: v_add_u32_e32 v0, vcc, s4, v1338; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v4, vcc339; VI-NEXT: flat_load_ubyte v2, v[2:3]340; VI-NEXT: flat_load_ubyte v0, v[0:1]341; VI-NEXT: s_mov_b32 s3, 0xf000342; VI-NEXT: s_mov_b32 s2, -1343; VI-NEXT: s_waitcnt vmcnt(0)344; VI-NEXT: v_mul_lo_u16_e32 v0, v2, v0345; VI-NEXT: v_bfe_i32 v0, v0, 0, 8346; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0347; VI-NEXT: s_endpgm348;349; GFX9-LABEL: test_umul24_i8_vgpr:350; GFX9: ; %bb.0: ; %entry351; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24352; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34353; GFX9-NEXT: s_waitcnt lgkmcnt(0)354; GFX9-NEXT: global_load_ubyte v2, v0, s[2:3]355; GFX9-NEXT: global_load_ubyte v3, v1, s[6:7]356; GFX9-NEXT: s_mov_b32 s3, 0xf000357; GFX9-NEXT: s_mov_b32 s2, -1358; GFX9-NEXT: s_waitcnt vmcnt(0)359; GFX9-NEXT: v_mul_lo_u16_e32 v0, v2, v3360; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 8361; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0362; GFX9-NEXT: s_endpgm363entry:364 %tid.x = call i32 @llvm.amdgcn.workitem.id.x()365 %tid.y = call i32 @llvm.amdgcn.workitem.id.y()366 %a.ptr = getelementptr i8, ptr addrspace(1) %a, i32 %tid.x367 %b.ptr = getelementptr i8, ptr addrspace(1) %b, i32 %tid.y368 %a.l = load i8, ptr addrspace(1) %a.ptr369 %b.l = load i8, ptr addrspace(1) %b.ptr370 %mul = mul i8 %a.l, %b.l371 %ext = sext i8 %mul to i32372 store i32 %ext, ptr addrspace(1) %out373 ret void374}375 376define amdgpu_kernel void @test_umulhi24_i32_i64(ptr addrspace(1) %out, i32 %a, i32 %b) {377; SI-LABEL: test_umulhi24_i32_i64:378; SI: ; %bb.0: ; %entry379; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9380; SI-NEXT: s_mov_b32 s7, 0xf000381; SI-NEXT: s_mov_b32 s6, -1382; SI-NEXT: s_waitcnt lgkmcnt(0)383; SI-NEXT: s_mov_b32 s4, s0384; SI-NEXT: s_mov_b32 s5, s1385; SI-NEXT: v_mov_b32_e32 v0, s3386; SI-NEXT: v_mul_hi_u32_u24_e32 v0, s2, v0387; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0388; SI-NEXT: s_endpgm389;390; VI-LABEL: test_umulhi24_i32_i64:391; VI: ; %bb.0: ; %entry392; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24393; VI-NEXT: s_mov_b32 s7, 0xf000394; VI-NEXT: s_mov_b32 s6, -1395; VI-NEXT: s_waitcnt lgkmcnt(0)396; VI-NEXT: v_mov_b32_e32 v0, s3397; VI-NEXT: s_mov_b32 s4, s0398; VI-NEXT: s_mov_b32 s5, s1399; VI-NEXT: v_mul_hi_u32_u24_e32 v0, s2, v0400; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0401; VI-NEXT: s_endpgm402;403; GFX9-LABEL: test_umulhi24_i32_i64:404; GFX9: ; %bb.0: ; %entry405; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24406; GFX9-NEXT: s_waitcnt lgkmcnt(0)407; GFX9-NEXT: s_mov_b64 s[4:5], s[2:3]408; GFX9-NEXT: s_and_b32 s4, s4, 0xffffff409; GFX9-NEXT: s_and_b32 s5, s5, 0xffffff410; GFX9-NEXT: s_mul_hi_u32 s4, s4, s5411; GFX9-NEXT: s_mov_b32 s3, 0xf000412; GFX9-NEXT: s_mov_b32 s2, -1413; GFX9-NEXT: v_mov_b32_e32 v0, s4414; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0415; GFX9-NEXT: s_endpgm416entry:417 %a.24 = and i32 %a, 16777215418 %b.24 = and i32 %b, 16777215419 %a.24.i64 = zext i32 %a.24 to i64420 %b.24.i64 = zext i32 %b.24 to i64421 %mul48 = mul i64 %a.24.i64, %b.24.i64422 %mul48.hi = lshr i64 %mul48, 32423 %mul24hi = trunc i64 %mul48.hi to i32424 store i32 %mul24hi, ptr addrspace(1) %out425 ret void426}427 428define amdgpu_kernel void @test_umulhi24(ptr addrspace(1) %out, i64 %a, i64 %b) {429; SI-LABEL: test_umulhi24:430; SI: ; %bb.0: ; %entry431; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9432; SI-NEXT: s_waitcnt lgkmcnt(0)433; SI-NEXT: s_load_dword s3, s[4:5], 0xd434; SI-NEXT: s_mov_b32 s7, 0xf000435; SI-NEXT: s_mov_b32 s6, -1436; SI-NEXT: s_mov_b32 s4, s0437; SI-NEXT: s_mov_b32 s5, s1438; SI-NEXT: s_waitcnt lgkmcnt(0)439; SI-NEXT: v_mov_b32_e32 v0, s3440; SI-NEXT: v_mul_hi_u32_u24_e32 v0, s2, v0441; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0442; SI-NEXT: s_endpgm443;444; VI-LABEL: test_umulhi24:445; VI: ; %bb.0: ; %entry446; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24447; VI-NEXT: s_waitcnt lgkmcnt(0)448; VI-NEXT: s_load_dword s3, s[4:5], 0x34449; VI-NEXT: s_mov_b32 s7, 0xf000450; VI-NEXT: s_mov_b32 s6, -1451; VI-NEXT: s_mov_b32 s4, s0452; VI-NEXT: s_waitcnt lgkmcnt(0)453; VI-NEXT: v_mov_b32_e32 v0, s3454; VI-NEXT: s_mov_b32 s5, s1455; VI-NEXT: v_mul_hi_u32_u24_e32 v0, s2, v0456; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0457; VI-NEXT: s_endpgm458;459; GFX9-LABEL: test_umulhi24:460; GFX9: ; %bb.0: ; %entry461; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24462; GFX9-NEXT: s_waitcnt lgkmcnt(0)463; GFX9-NEXT: s_load_dword s3, s[4:5], 0x34464; GFX9-NEXT: s_mov_b32 s7, 0xf000465; GFX9-NEXT: s_mov_b32 s6, -1466; GFX9-NEXT: s_mov_b32 s4, s0467; GFX9-NEXT: s_mov_b32 s5, s1468; GFX9-NEXT: s_and_b32 s0, s2, 0xffffff469; GFX9-NEXT: s_waitcnt lgkmcnt(0)470; GFX9-NEXT: s_and_b32 s1, s3, 0xffffff471; GFX9-NEXT: s_mul_hi_u32 s0, s0, s1472; GFX9-NEXT: v_mov_b32_e32 v0, s0473; GFX9-NEXT: buffer_store_dword v0, off, s[4:7], 0474; GFX9-NEXT: s_endpgm475entry:476 %a.24 = and i64 %a, 16777215477 %b.24 = and i64 %b, 16777215478 %mul48 = mul i64 %a.24, %b.24479 %mul48.hi = lshr i64 %mul48, 32480 %mul24.hi = trunc i64 %mul48.hi to i32481 store i32 %mul24.hi, ptr addrspace(1) %out482 ret void483}484 485; Multiply with 24-bit inputs and 64-bit output.486define amdgpu_kernel void @test_umul24_i64(ptr addrspace(1) %out, i64 %a, i64 %b) {487; SI-LABEL: test_umul24_i64:488; SI: ; %bb.0: ; %entry489; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9490; SI-NEXT: s_waitcnt lgkmcnt(0)491; SI-NEXT: s_load_dword s3, s[4:5], 0xd492; SI-NEXT: s_mov_b32 s7, 0xf000493; SI-NEXT: s_mov_b32 s6, -1494; SI-NEXT: s_mov_b32 s4, s0495; SI-NEXT: s_mov_b32 s5, s1496; SI-NEXT: s_and_b32 s0, s2, 0xffffff497; SI-NEXT: s_waitcnt lgkmcnt(0)498; SI-NEXT: s_and_b32 s1, s3, 0xffffff499; SI-NEXT: v_mov_b32_e32 v0, s3500; SI-NEXT: s_mul_i32 s0, s0, s1501; SI-NEXT: v_mul_hi_u32_u24_e32 v1, s2, v0502; SI-NEXT: v_mov_b32_e32 v0, s0503; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0504; SI-NEXT: s_endpgm505;506; VI-LABEL: test_umul24_i64:507; VI: ; %bb.0: ; %entry508; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24509; VI-NEXT: s_waitcnt lgkmcnt(0)510; VI-NEXT: s_load_dword s3, s[4:5], 0x34511; VI-NEXT: s_mov_b32 s7, 0xf000512; VI-NEXT: s_mov_b32 s6, -1513; VI-NEXT: s_mov_b32 s4, s0514; VI-NEXT: s_waitcnt lgkmcnt(0)515; VI-NEXT: v_mov_b32_e32 v0, s3516; VI-NEXT: s_mov_b32 s5, s1517; VI-NEXT: v_mul_hi_u32_u24_e32 v1, s2, v0518; VI-NEXT: v_mul_u32_u24_e32 v0, s2, v0519; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0520; VI-NEXT: s_endpgm521;522; GFX9-LABEL: test_umul24_i64:523; GFX9: ; %bb.0: ; %entry524; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24525; GFX9-NEXT: s_waitcnt lgkmcnt(0)526; GFX9-NEXT: s_load_dword s3, s[4:5], 0x34527; GFX9-NEXT: s_mov_b32 s7, 0xf000528; GFX9-NEXT: s_mov_b32 s6, -1529; GFX9-NEXT: s_mov_b32 s4, s0530; GFX9-NEXT: s_mov_b32 s5, s1531; GFX9-NEXT: s_and_b32 s0, s2, 0xffffff532; GFX9-NEXT: s_waitcnt lgkmcnt(0)533; GFX9-NEXT: s_and_b32 s1, s3, 0xffffff534; GFX9-NEXT: s_mul_hi_u32 s2, s0, s1535; GFX9-NEXT: s_mul_i32 s0, s0, s1536; GFX9-NEXT: v_mov_b32_e32 v0, s0537; GFX9-NEXT: v_mov_b32_e32 v1, s2538; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0539; GFX9-NEXT: s_endpgm540entry:541 %tmp0 = shl i64 %a, 40542 %a_24 = lshr i64 %tmp0, 40543 %tmp1 = shl i64 %b, 40544 %b_24 = lshr i64 %tmp1, 40545 %tmp2 = mul i64 %a_24, %b_24546 store i64 %tmp2, ptr addrspace(1) %out547 ret void548}549 550define i64 @test_umul48_i64(i64 %lhs, i64 %rhs) {551; GCN-LABEL: test_umul48_i64:552; GCN: ; %bb.0:553; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)554; GCN-NEXT: v_mul_hi_u32_u24_e32 v1, v0, v2555; GCN-NEXT: v_mul_u32_u24_e32 v0, v0, v2556; GCN-NEXT: s_setpc_b64 s[30:31]557 %lhs24 = and i64 %lhs, 16777215558 %rhs24 = and i64 %rhs, 16777215559 %mul = mul i64 %lhs24, %rhs24560 ret i64 %mul561}562 563define <2 x i64> @test_umul48_v2i64(<2 x i64> %lhs, <2 x i64> %rhs) {564; GCN-LABEL: test_umul48_v2i64:565; GCN: ; %bb.0:566; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)567; GCN-NEXT: v_mul_hi_u32_u24_e32 v1, v0, v4568; GCN-NEXT: v_mul_u32_u24_e32 v0, v0, v4569; GCN-NEXT: v_mul_hi_u32_u24_e32 v3, v2, v6570; GCN-NEXT: v_mul_u32_u24_e32 v2, v2, v6571; GCN-NEXT: s_setpc_b64 s[30:31]572 %lhs24 = and <2 x i64> %lhs, <i64 16777215, i64 16777215>573 %rhs24 = and <2 x i64> %rhs, <i64 16777215, i64 16777215>574 %mul = mul <2 x i64> %lhs24, %rhs24575 ret <2 x i64> %mul576}577 578define amdgpu_kernel void @test_umul24_i64_square(ptr addrspace(1) %out, [8 x i32], i64 %a) {579; SI-LABEL: test_umul24_i64_square:580; SI: ; %bb.0: ; %entry581; SI-NEXT: s_load_dword s6, s[4:5], 0x13582; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9583; SI-NEXT: s_mov_b32 s3, 0xf000584; SI-NEXT: s_mov_b32 s2, -1585; SI-NEXT: s_waitcnt lgkmcnt(0)586; SI-NEXT: s_and_b32 s4, s6, 0xffffff587; SI-NEXT: s_mul_i32 s4, s4, s4588; SI-NEXT: v_mul_hi_u32_u24_e64 v1, s6, s6589; SI-NEXT: v_mov_b32_e32 v0, s4590; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0591; SI-NEXT: s_endpgm592;593; VI-LABEL: test_umul24_i64_square:594; VI: ; %bb.0: ; %entry595; VI-NEXT: s_load_dword s6, s[4:5], 0x4c596; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24597; VI-NEXT: s_mov_b32 s3, 0xf000598; VI-NEXT: s_mov_b32 s2, -1599; VI-NEXT: s_waitcnt lgkmcnt(0)600; VI-NEXT: v_mul_hi_u32_u24_e64 v1, s6, s6601; VI-NEXT: v_mul_u32_u24_e64 v0, s6, s6602; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0603; VI-NEXT: s_endpgm604;605; GFX9-LABEL: test_umul24_i64_square:606; GFX9: ; %bb.0: ; %entry607; GFX9-NEXT: s_load_dword s6, s[4:5], 0x4c608; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24609; GFX9-NEXT: s_mov_b32 s3, 0xf000610; GFX9-NEXT: s_mov_b32 s2, -1611; GFX9-NEXT: s_waitcnt lgkmcnt(0)612; GFX9-NEXT: s_and_b32 s4, s6, 0xffffff613; GFX9-NEXT: s_mul_hi_u32 s5, s4, s4614; GFX9-NEXT: s_mul_i32 s4, s4, s4615; GFX9-NEXT: v_mov_b32_e32 v0, s4616; GFX9-NEXT: v_mov_b32_e32 v1, s5617; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0618; GFX9-NEXT: s_endpgm619entry:620 %tmp0 = shl i64 %a, 40621 %a.24 = lshr i64 %tmp0, 40622 %tmp2 = mul i64 %a.24, %a.24623 store i64 %tmp2, ptr addrspace(1) %out624 ret void625}626 627define amdgpu_kernel void @test_umulhi16_i32(ptr addrspace(1) %out, i32 %a, i32 %b) {628; SI-LABEL: test_umulhi16_i32:629; SI: ; %bb.0: ; %entry630; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9631; SI-NEXT: s_waitcnt lgkmcnt(0)632; SI-NEXT: s_mov_b64 s[4:5], s[2:3]633; SI-NEXT: s_mov_b32 s3, 0xf000634; SI-NEXT: s_and_b32 s2, s4, 0xffff635; SI-NEXT: s_and_b32 s4, s5, 0xffff636; SI-NEXT: s_mul_i32 s2, s2, s4637; SI-NEXT: s_lshr_b32 s4, s2, 16638; SI-NEXT: s_mov_b32 s2, -1639; SI-NEXT: v_mov_b32_e32 v0, s4640; SI-NEXT: buffer_store_short v0, off, s[0:3], 0641; SI-NEXT: s_endpgm642;643; VI-LABEL: test_umulhi16_i32:644; VI: ; %bb.0: ; %entry645; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24646; VI-NEXT: s_waitcnt lgkmcnt(0)647; VI-NEXT: s_mov_b64 s[4:5], s[2:3]648; VI-NEXT: s_and_b32 s4, s4, 0xffff649; VI-NEXT: s_and_b32 s5, s5, 0xffff650; VI-NEXT: s_mul_i32 s4, s4, s5651; VI-NEXT: s_lshr_b32 s4, s4, 16652; VI-NEXT: s_mov_b32 s3, 0xf000653; VI-NEXT: s_mov_b32 s2, -1654; VI-NEXT: v_mov_b32_e32 v0, s4655; VI-NEXT: buffer_store_short v0, off, s[0:3], 0656; VI-NEXT: s_endpgm657;658; GFX9-LABEL: test_umulhi16_i32:659; GFX9: ; %bb.0: ; %entry660; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24661; GFX9-NEXT: v_mov_b32_e32 v0, 0662; GFX9-NEXT: s_waitcnt lgkmcnt(0)663; GFX9-NEXT: s_and_b32 s2, s2, 0xffff664; GFX9-NEXT: s_and_b32 s3, s3, 0xffff665; GFX9-NEXT: s_mul_i32 s2, s2, s3666; GFX9-NEXT: v_mov_b32_e32 v1, s2667; GFX9-NEXT: global_store_short_d16_hi v0, v1, s[0:1]668; GFX9-NEXT: s_endpgm669entry:670 %a.16 = and i32 %a, 65535671 %b.16 = and i32 %b, 65535672 %mul = mul i32 %a.16, %b.16673 %hi = lshr i32 %mul, 16674 %mulhi = trunc i32 %hi to i16675 store i16 %mulhi, ptr addrspace(1) %out676 ret void677}678 679define amdgpu_kernel void @test_umul24_i33(ptr addrspace(1) %out, i33 %a, i33 %b) {680; SI-LABEL: test_umul24_i33:681; SI: ; %bb.0: ; %entry682; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9683; SI-NEXT: s_load_dword s6, s[4:5], 0xb684; SI-NEXT: s_load_dword s4, s[4:5], 0xd685; SI-NEXT: s_mov_b32 s3, 0xf000686; SI-NEXT: s_mov_b32 s2, -1687; SI-NEXT: s_waitcnt lgkmcnt(0)688; SI-NEXT: s_and_b32 s5, s6, 0xffffff689; SI-NEXT: s_and_b32 s7, s4, 0xffffff690; SI-NEXT: v_mov_b32_e32 v0, s4691; SI-NEXT: v_mul_hi_u32_u24_e32 v0, s6, v0692; SI-NEXT: s_mul_i32 s5, s5, s7693; SI-NEXT: v_and_b32_e32 v1, 1, v0694; SI-NEXT: v_mov_b32_e32 v0, s5695; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0696; SI-NEXT: s_endpgm697;698; VI-LABEL: test_umul24_i33:699; VI: ; %bb.0: ; %entry700; VI-NEXT: s_load_dword s6, s[4:5], 0x34701; VI-NEXT: s_load_dword s7, s[4:5], 0x2c702; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24703; VI-NEXT: s_mov_b32 s3, 0xf000704; VI-NEXT: s_mov_b32 s2, -1705; VI-NEXT: s_waitcnt lgkmcnt(0)706; VI-NEXT: v_mov_b32_e32 v1, s6707; VI-NEXT: v_mul_u32_u24_e32 v0, s7, v1708; VI-NEXT: v_mul_hi_u32_u24_e32 v1, s7, v1709; VI-NEXT: v_and_b32_e32 v1, 1, v1710; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0711; VI-NEXT: s_endpgm712;713; GFX9-LABEL: test_umul24_i33:714; GFX9: ; %bb.0: ; %entry715; GFX9-NEXT: s_load_dword s6, s[4:5], 0x2c716; GFX9-NEXT: s_load_dword s7, s[4:5], 0x34717; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24718; GFX9-NEXT: s_mov_b32 s3, 0xf000719; GFX9-NEXT: s_mov_b32 s2, -1720; GFX9-NEXT: s_waitcnt lgkmcnt(0)721; GFX9-NEXT: s_and_b32 s4, s6, 0xffffff722; GFX9-NEXT: s_and_b32 s5, s7, 0xffffff723; GFX9-NEXT: s_mul_i32 s6, s4, s5724; GFX9-NEXT: s_mul_hi_u32 s4, s4, s5725; GFX9-NEXT: s_and_b32 s4, s4, 1726; GFX9-NEXT: v_mov_b32_e32 v0, s6727; GFX9-NEXT: v_mov_b32_e32 v1, s4728; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0729; GFX9-NEXT: s_endpgm730entry:731 %tmp0 = shl i33 %a, 9732 %a_24 = lshr i33 %tmp0, 9733 %tmp1 = shl i33 %b, 9734 %b_24 = lshr i33 %tmp1, 9735 %tmp2 = mul i33 %a_24, %b_24736 %ext = zext i33 %tmp2 to i64737 store i64 %ext, ptr addrspace(1) %out738 ret void739}740 741define amdgpu_kernel void @test_umulhi24_i33(ptr addrspace(1) %out, i33 %a, i33 %b) {742; SI-LABEL: test_umulhi24_i33:743; SI: ; %bb.0: ; %entry744; SI-NEXT: s_load_dword s6, s[4:5], 0xd745; SI-NEXT: s_load_dword s7, s[4:5], 0xb746; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9747; SI-NEXT: s_mov_b32 s3, 0xf000748; SI-NEXT: s_mov_b32 s2, -1749; SI-NEXT: s_waitcnt lgkmcnt(0)750; SI-NEXT: v_mov_b32_e32 v0, s6751; SI-NEXT: v_mul_hi_u32_u24_e32 v0, s7, v0752; SI-NEXT: v_and_b32_e32 v0, 1, v0753; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0754; SI-NEXT: s_endpgm755;756; VI-LABEL: test_umulhi24_i33:757; VI: ; %bb.0: ; %entry758; VI-NEXT: s_load_dword s6, s[4:5], 0x34759; VI-NEXT: s_load_dword s7, s[4:5], 0x2c760; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24761; VI-NEXT: s_mov_b32 s3, 0xf000762; VI-NEXT: s_mov_b32 s2, -1763; VI-NEXT: s_waitcnt lgkmcnt(0)764; VI-NEXT: v_mov_b32_e32 v0, s6765; VI-NEXT: v_mul_hi_u32_u24_e32 v0, s7, v0766; VI-NEXT: v_and_b32_e32 v0, 1, v0767; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0768; VI-NEXT: s_endpgm769;770; GFX9-LABEL: test_umulhi24_i33:771; GFX9: ; %bb.0: ; %entry772; GFX9-NEXT: s_load_dword s6, s[4:5], 0x2c773; GFX9-NEXT: s_load_dword s7, s[4:5], 0x34774; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24775; GFX9-NEXT: s_mov_b32 s3, 0xf000776; GFX9-NEXT: s_mov_b32 s2, -1777; GFX9-NEXT: s_waitcnt lgkmcnt(0)778; GFX9-NEXT: s_and_b32 s4, s6, 0xffffff779; GFX9-NEXT: s_and_b32 s5, s7, 0xffffff780; GFX9-NEXT: s_mul_hi_u32 s4, s4, s5781; GFX9-NEXT: s_and_b32 s4, s4, 1782; GFX9-NEXT: v_mov_b32_e32 v0, s4783; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0784; GFX9-NEXT: s_endpgm785entry:786 %tmp0 = shl i33 %a, 9787 %a_24 = lshr i33 %tmp0, 9788 %tmp1 = shl i33 %b, 9789 %b_24 = lshr i33 %tmp1, 9790 %tmp2 = mul i33 %a_24, %b_24791 %hi = lshr i33 %tmp2, 32792 %trunc = trunc i33 %hi to i32793 store i32 %trunc, ptr addrspace(1) %out794 ret void795}796 797 798; Make sure the created any_extend is ignored to use the real bits799; being multiplied.800define i17 @test_umul24_anyextend_i24_src0_src1(i24 %a, i24 %b) {801; GCN-LABEL: test_umul24_anyextend_i24_src0_src1:802; GCN: ; %bb.0: ; %entry803; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)804; GCN-NEXT: v_mul_u32_u24_e32 v0, 0xea, v0805; GCN-NEXT: v_mul_u32_u24_e32 v1, 0x39b, v1806; GCN-NEXT: v_mul_u32_u24_e32 v0, v0, v1807; GCN-NEXT: v_and_b32_e32 v0, 0x1fffe, v0808; GCN-NEXT: v_mul_u32_u24_e32 v0, 0x63, v0809; GCN-NEXT: s_setpc_b64 s[30:31]810entry:811 %aa = mul i24 %a, 234812 %bb = mul i24 %b, 923813 %a_32 = zext i24 %aa to i32814 %b_32 = zext i24 %bb to i32815 %mul = mul i32 %a_32, %b_32816 %trunc = trunc i32 %mul to i17817 %arst = mul i17 %trunc, 99818 ret i17 %arst819}820 821define i17 @test_umul24_anyextend_i23_src0_src1(i23 %a, i23 %b) {822; GCN-LABEL: test_umul24_anyextend_i23_src0_src1:823; GCN: ; %bb.0: ; %entry824; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)825; GCN-NEXT: v_and_b32_e32 v0, 0x7fffff, v0826; GCN-NEXT: v_and_b32_e32 v1, 0x7fffff, v1827; GCN-NEXT: v_mul_u32_u24_e32 v0, 0xea, v0828; GCN-NEXT: v_mul_u32_u24_e32 v1, 0x39b, v1829; GCN-NEXT: v_and_b32_e32 v0, 0x7ffffe, v0830; GCN-NEXT: v_and_b32_e32 v1, 0x7fffff, v1831; GCN-NEXT: v_mul_u32_u24_e32 v0, v0, v1832; GCN-NEXT: v_and_b32_e32 v0, 0x1fffe, v0833; GCN-NEXT: v_mul_u32_u24_e32 v0, 0x63, v0834; GCN-NEXT: s_setpc_b64 s[30:31]835entry:836 %aa = mul i23 %a, 234837 %bb = mul i23 %b, 923838 %a_32 = zext i23 %aa to i32839 %b_32 = zext i23 %bb to i32840 %mul = mul i32 %a_32, %b_32841 %trunc = trunc i32 %mul to i17842 %arst = mul i17 %trunc, 99843 ret i17 %arst844}845