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1; RUN: llc -mtriple=amdgcn -mcpu=gfx600 < %s | FileCheck --check-prefix=GCN %s2; RUN: llc -mtriple=amdgcn -mcpu=gfx700 < %s | FileCheck --check-prefix=GCN %s3; RUN: llc -mtriple=amdgcn -mcpu=gfx801 < %s | FileCheck --check-prefix=GCN %s4; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck --check-prefix=GCN %s5 6; GCN-LABEL: {{^}}scalar_nand_i32_one_use7; GCN: s_nand_b328define amdgpu_kernel void @scalar_nand_i32_one_use(9 ptr addrspace(1) %r0, i32 %a, i32 %b) {10entry:11 %and = and i32 %a, %b12 %r0.val = xor i32 %and, -113 store i32 %r0.val, ptr addrspace(1) %r014 ret void15}16 17; GCN-LABEL: {{^}}scalar_nand_i32_mul_use18; GCN-NOT: s_nand_b3219; GCN: s_and_b3220; GCN: s_not_b3221; GCN: s_add_i3222define amdgpu_kernel void @scalar_nand_i32_mul_use(23 ptr addrspace(1) %r0, ptr addrspace(1) %r1, i32 %a, i32 %b) {24entry:25 %and = and i32 %a, %b26 %r0.val = xor i32 %and, -127 %r1.val = add i32 %and, %a28 store i32 %r0.val, ptr addrspace(1) %r029 store i32 %r1.val, ptr addrspace(1) %r130 ret void31}32 33; GCN-LABEL: {{^}}scalar_nand_i64_one_use34; GCN: s_nand_b6435define amdgpu_kernel void @scalar_nand_i64_one_use(36 ptr addrspace(1) %r0, i64 %a, i64 %b) {37entry:38 %and = and i64 %a, %b39 %r0.val = xor i64 %and, -140 store i64 %r0.val, ptr addrspace(1) %r041 ret void42}43 44; GCN-LABEL: {{^}}scalar_nand_i64_mul_use45; GCN-NOT: s_nand_b6446; GCN: s_and_b6447; GCN: s_not_b6448; GCN: s_add_u3249; GCN: s_addc_u3250define amdgpu_kernel void @scalar_nand_i64_mul_use(51 ptr addrspace(1) %r0, ptr addrspace(1) %r1, i64 %a, i64 %b) {52entry:53 %and = and i64 %a, %b54 %r0.val = xor i64 %and, -155 %r1.val = add i64 %and, %a56 store i64 %r0.val, ptr addrspace(1) %r057 store i64 %r1.val, ptr addrspace(1) %r158 ret void59}60 61; GCN-LABEL: {{^}}vector_nand_i32_one_use62; GCN-NOT: s_nand_b3263; GCN: v_and_b3264; GCN: v_not_b3265define i32 @vector_nand_i32_one_use(i32 %a, i32 %b) {66entry:67 %and = and i32 %a, %b68 %r = xor i32 %and, -169 ret i32 %r70}71 72; GCN-LABEL: {{^}}vector_nand_i64_one_use73; GCN-NOT: s_nand_b6474; GCN: v_and_b3275; GCN: v_and_b3276; GCN: v_not_b3277; GCN: v_not_b3278define i64 @vector_nand_i64_one_use(i64 %a, i64 %b) {79entry:80 %and = and i64 %a, %b81 %r = xor i64 %and, -182 ret i64 %r83}84