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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52 3; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck %s4 5define i64 @narrow_add(i64 %a, i64 %b) {6; CHECK-LABEL: narrow_add:7; CHECK: ; %bb.0:8; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)9; CHECK-NEXT: v_and_b32_e32 v0, 0x7fffffff, v010; CHECK-NEXT: v_and_b32_e32 v1, 0x7fffffff, v211; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)12; CHECK-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v0, v0, v113; CHECK-NEXT: s_setpc_b64 s[30:31]14 %zext0 = and i64 %a, 214748364715 %zext1 = and i64 %b, 214748364716 %add = add i64 %zext0, %zext117 ret i64 %add18}19 20define i64 @narrow_add_1(i64 %a, i64 %b) {21; CHECK-LABEL: narrow_add_1:22; CHECK: ; %bb.0:23; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)24; CHECK-NEXT: v_bfi_b32 v0, 0x7fffffff, v0, v225; CHECK-NEXT: v_mov_b32_e32 v1, 026; CHECK-NEXT: s_setpc_b64 s[30:31]27 %zext0 = and i64 %a, 214748364728 %zext1 = and i64 %b, 214748364829 %add = add i64 %zext0, %zext130 ret i64 %add31}32 33define <2 x i64> @narrow_add_vec(<2 x i64> %a, <2 x i64> %b) #0 {34; CHECK-LABEL: narrow_add_vec:35; CHECK: ; %bb.0:36; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)37; CHECK-NEXT: v_and_b32_e32 v1, 30, v238; CHECK-NEXT: v_and_b32_e32 v0, 0x7fffffff, v039; CHECK-NEXT: v_and_b32_e32 v2, 0x7fffffff, v440; CHECK-NEXT: v_and_b32_e32 v3, 0x7ffffffe, v641; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)42; CHECK-NEXT: v_add_nc_u32_e32 v0, v0, v243; CHECK-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_add_nc_u32 v2, v1, v344; CHECK-NEXT: v_mov_b32_e32 v3, 045; CHECK-NEXT: s_setpc_b64 s[30:31]46 %zext0 = and <2 x i64> %a, <i64 2147483647, i64 30>47 %zext1 = and <2 x i64> %b, <i64 2147483647, i64 2147483646>48 %add = add <2 x i64> %zext0, %zext149 ret <2 x i64> %add50}51 52define <2 x i32> @narrow_add_vec_1(<2 x i32> %a, <2 x i32> %b) #0 {53; CHECK-LABEL: narrow_add_vec_1:54; CHECK: ; %bb.0:55; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)56; CHECK-NEXT: v_and_b32_e32 v1, 0x3fff, v157; CHECK-NEXT: v_and_b32_e32 v0, 0x4000, v058; CHECK-NEXT: v_and_b32_e32 v2, 0x4000, v259; CHECK-NEXT: v_and_b32_e32 v3, 0x4001, v360; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)61; CHECK-NEXT: v_add_nc_u32_e32 v0, v0, v262; CHECK-NEXT: v_add_nc_u32_e32 v1, v1, v363; CHECK-NEXT: s_setpc_b64 s[30:31]64 %zext0 = and <2 x i32> %a, <i32 16384, i32 16383>65 %zext1 = and <2 x i32> %b, <i32 16384, i32 16385>66 %add = add <2 x i32> %zext0, %zext167 ret <2 x i32> %add68}69 70define i64 @narrow_mul(i64 %a, i64 %b) {71; CHECK-LABEL: narrow_mul:72; CHECK: ; %bb.0:73; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)74; CHECK-NEXT: v_and_b32_e32 v1, 2, v275; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)76; CHECK-NEXT: v_mul_lo_u32 v0, v0, v177; CHECK-NEXT: v_mov_b32_e32 v1, 078; CHECK-NEXT: s_setpc_b64 s[30:31]79 %zext0 = and i64 %a, 214748364780 %zext1 = and i64 %b, 281 %mul = mul i64 %zext0, %zext182 ret i64 %mul83}84 85define i64 @narrow_mul_1(i64 %a, i64 %b) {86; CHECK-LABEL: narrow_mul_1:87; CHECK: ; %bb.0:88; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)89; CHECK-NEXT: v_and_b32_e32 v1, 0xf73594, v090; CHECK-NEXT: v_and_b32_e32 v2, 0x100, v291; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)92; CHECK-NEXT: v_mul_u32_u24_e32 v0, v1, v293; CHECK-NEXT: v_mul_hi_u32_u24_e32 v1, v1, v294; CHECK-NEXT: s_setpc_b64 s[30:31]95 %zext0 = and i64 %a, 1620110896 %zext1 = and i64 %b, 25697 %mul = mul i64 %zext0, %zext198 ret i64 %mul99}100 101define <2 x i64> @narrow_mul_vec(<2 x i64> %a, <2 x i64> %b) #0 {102; CHECK-LABEL: narrow_mul_vec:103; CHECK: ; %bb.0:104; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)105; CHECK-NEXT: v_and_b32_e32 v0, 0x2d48aff, v0106; CHECK-NEXT: v_and_b32_e32 v1, 0x50, v4107; CHECK-NEXT: v_and_b32_e32 v2, 50, v2108; CHECK-NEXT: v_and_b32_e32 v3, 20, v6109; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)110; CHECK-NEXT: v_mul_lo_u32 v0, v0, v1111; CHECK-NEXT: v_mov_b32_e32 v1, 0112; CHECK-NEXT: v_mul_u32_u24_e32 v2, v2, v3113; CHECK-NEXT: v_mov_b32_e32 v3, 0114; CHECK-NEXT: s_setpc_b64 s[30:31]115 %zext0 = and <2 x i64> %a, <i64 47483647, i64 50>116 %zext1 = and <2 x i64> %b, <i64 80, i64 20>117 %mul = mul <2 x i64> %zext0, %zext1118 ret <2 x i64> %mul119}120 121define <2 x i32> @narrow_add_mul_1(<2 x i32> %a, <2 x i32> %b) #0 {122; CHECK-LABEL: narrow_add_mul_1:123; CHECK: ; %bb.0:124; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)125; CHECK-NEXT: v_and_b32_e32 v1, 0x4000, v1126; CHECK-NEXT: v_and_b32_e32 v0, 0x4000, v0127; CHECK-NEXT: v_and_b32_e32 v2, 3, v2128; CHECK-NEXT: v_and_b32_e32 v3, 2, v3129; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)130; CHECK-NEXT: v_mul_u32_u24_e32 v0, v0, v2131; CHECK-NEXT: v_mul_u32_u24_e32 v1, v1, v3132; CHECK-NEXT: s_setpc_b64 s[30:31]133 %zext0 = and <2 x i32> %a, <i32 16384, i32 16384>134 %zext1 = and <2 x i32> %b, <i32 3, i32 2>135 %mul = mul <2 x i32> %zext0, %zext1136 ret <2 x i32> %mul137}138 139define i64 @no_narrow_add(i64 %a, i64 %b) {140; CHECK-LABEL: no_narrow_add:141; CHECK: ; %bb.0:142; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)143; CHECK-NEXT: v_and_b32_e32 v0, 0x80000000, v0144; CHECK-NEXT: v_and_b32_e32 v1, 0x80000000, v2145; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)146; CHECK-NEXT: v_add_co_u32 v0, s0, v0, v1147; CHECK-NEXT: v_add_co_ci_u32_e64 v1, null, 0, 0, s0148; CHECK-NEXT: s_setpc_b64 s[30:31]149 %zext0 = and i64 %a, 2147483648150 %zext1 = and i64 %b, 2147483648151 %add = add i64 %zext0, %zext1152 ret i64 %add153}154 155define i64 @no_narrow_add_1(i64 %a, i64 %b) {156; CHECK-LABEL: no_narrow_add_1:157; CHECK: ; %bb.0:158; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)159; CHECK-NEXT: v_and_b32_e32 v1, 1, v2160; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)161; CHECK-NEXT: v_add_co_u32 v0, s0, v0, v1162; CHECK-NEXT: v_add_co_ci_u32_e64 v1, null, 0, 0, s0163; CHECK-NEXT: s_setpc_b64 s[30:31]164 %zext0 = and i64 %a, 4294967295165 %zext1 = and i64 %b, 1166 %add = add i64 %zext0, %zext1167 ret i64 %add168}169 170define <2 x i64> @no_narrow_add_vec(<2 x i64> %a, <2 x i64> %b) #0 {171; CHECK-LABEL: no_narrow_add_vec:172; CHECK: ; %bb.0:173; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)174; CHECK-NEXT: v_and_b32_e32 v0, 0x80000000, v0175; CHECK-NEXT: v_and_b32_e32 v1, 0x80000000, v4176; CHECK-NEXT: v_and_b32_e32 v2, 30, v2177; CHECK-NEXT: v_and_b32_e32 v3, 0x7ffffffe, v6178; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)179; CHECK-NEXT: v_add_co_u32 v0, s0, v0, v1180; CHECK-NEXT: v_add_co_ci_u32_e64 v1, null, 0, 0, s0181; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_1)182; CHECK-NEXT: v_add_co_u32 v2, s0, v2, v3183; CHECK-NEXT: v_add_co_ci_u32_e64 v3, null, 0, 0, s0184; CHECK-NEXT: s_setpc_b64 s[30:31]185 %zext0 = and <2 x i64> %a, <i64 2147483648, i64 30>186 %zext1 = and <2 x i64> %b, <i64 2147483648, i64 2147483646>187 %add = add <2 x i64> %zext0, %zext1188 ret <2 x i64> %add189}190 191define i64 @no_narrow_mul(i64 %a, i64 %b) {192; CHECK-LABEL: no_narrow_mul:193; CHECK: ; %bb.0:194; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)195; CHECK-NEXT: v_and_b32_e32 v0, 0x80000000, v0196; CHECK-NEXT: v_and_b32_e32 v1, 2, v2197; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_1)198; CHECK-NEXT: v_mul_hi_u32 v1, v0, v1199; CHECK-NEXT: v_mov_b32_e32 v0, 0200; CHECK-NEXT: s_setpc_b64 s[30:31]201 %zext0 = and i64 %a, 2147483648202 %zext1 = and i64 %b, 2203 %mul = mul i64 %zext0, %zext1204 ret i64 %mul205}206 207define <2 x i64> @no_narrow_mul_vec(<2 x i64> %a, <2 x i64> %b) #0 {208; CHECK-LABEL: no_narrow_mul_vec:209; CHECK: ; %bb.0:210; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)211; CHECK-NEXT: v_and_b32_e32 v1, 0x8000, v0212; CHECK-NEXT: v_and_b32_e32 v3, 0x20000, v4213; CHECK-NEXT: v_and_b32_e32 v4, 50, v2214; CHECK-NEXT: v_and_b32_e32 v5, 20, v6215; CHECK-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)216; CHECK-NEXT: v_mul_u32_u24_e32 v0, v1, v3217; CHECK-NEXT: v_mul_hi_u32_u24_e32 v1, v1, v3218; CHECK-NEXT: v_mul_u32_u24_e32 v2, v4, v5219; CHECK-NEXT: v_mul_hi_u32_u24_e32 v3, v4, v5220; CHECK-NEXT: s_setpc_b64 s[30:31]221 %zext0 = and <2 x i64> %a, <i64 32768, i64 50>222 %zext1 = and <2 x i64> %b, <i64 131072, i64 20>223 %mul = mul <2 x i64> %zext0, %zext1224 ret <2 x i64> %mul225}226