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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx900 < %s | FileCheck %s3 4; Test that negative 64-bit values shifted by [32-63] bits have5; a hi-result created by moving an all-ones constant.6 7; FIXME: Range metadata is invalidated when i64 types are legalized to v2i32 types.8; We could call performSraCombine before legalization, but other optimizations only work9; with 64-bit sra.10define i64 @scalar_ashr_metadata(ptr %arg0.ptr, ptr %arg1.ptr) {11; CHECK-LABEL: scalar_ashr_metadata:12; CHECK: ; %bb.0:13; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)14; CHECK-NEXT: flat_load_dwordx2 v[4:5], v[0:1]15; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)16; CHECK-NEXT: flat_load_dword v4, v[2:3]17; CHECK-NEXT: ; kill: killed $vgpr0 killed $vgpr118; CHECK-NEXT: ; kill: killed $vgpr2 killed $vgpr319; CHECK-NEXT: v_ashrrev_i32_e32 v1, 31, v520; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)21; CHECK-NEXT: v_ashrrev_i32_e32 v0, v4, v522; CHECK-NEXT: s_setpc_b64 s[30:31]23 %val = load i64, ptr %arg0.ptr, !range !0, !noundef !{}24 %shift.amt = load i64, ptr %arg1.ptr, !range !1, !noundef !{}25 %ashr = ashr i64 %val, %shift.amt26 ret i64 %ashr27}28 29define <2 x i64> @v2_ashr_metadata(ptr %arg0.ptr, ptr %arg1.ptr) {30; CHECK-LABEL: v2_ashr_metadata:31; CHECK: ; %bb.0:32; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)33; CHECK-NEXT: flat_load_dwordx4 v[4:7], v[0:1]34; CHECK-NEXT: flat_load_dwordx4 v[8:11], v[2:3]35; CHECK-NEXT: v_mov_b32_e32 v1, -136; CHECK-NEXT: v_mov_b32_e32 v3, -137; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)38; CHECK-NEXT: v_ashrrev_i32_e32 v0, v8, v539; CHECK-NEXT: v_ashrrev_i32_e32 v2, v10, v740; CHECK-NEXT: s_setpc_b64 s[30:31]41 %val = load <2 x i64>, ptr %arg0.ptr, !range !2, !noundef !{}42 %shift.amt = load <2 x i64>, ptr %arg1.ptr, !range !3, !noundef !{}43 %ashr = ashr <2 x i64> %val, %shift.amt44 ret <2 x i64> %ashr45}46 47define <3 x i64> @v3_ashr_metadata(ptr %arg0.ptr, ptr %arg1.ptr) {48; CHECK-LABEL: v3_ashr_metadata:49; CHECK: ; %bb.0:50; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)51; CHECK-NEXT: flat_load_dwordx4 v[4:7], v[0:1]52; CHECK-NEXT: v_add_co_u32_e32 v0, vcc, 20, v053; CHECK-NEXT: v_addc_co_u32_e32 v1, vcc, 0, v1, vcc54; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)55; CHECK-NEXT: flat_load_dword v4, v[2:3] offset:1656; CHECK-NEXT: flat_load_dwordx4 v[8:11], v[2:3]57; CHECK-NEXT: v_mov_b32_e32 v3, -158; CHECK-NEXT: flat_load_dword v1, v[0:1]59; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)60; CHECK-NEXT: v_ashrrev_i32_e32 v0, v8, v561; CHECK-NEXT: v_ashrrev_i32_e32 v2, v10, v762; CHECK-NEXT: v_ashrrev_i32_e32 v4, v4, v163; CHECK-NEXT: v_mov_b32_e32 v1, -164; CHECK-NEXT: v_mov_b32_e32 v5, -165; CHECK-NEXT: s_setpc_b64 s[30:31]66 %val = load <3 x i64>, ptr %arg0.ptr, !range !4, !noundef !{}67 %shift.amt = load <3 x i64>, ptr %arg1.ptr, !range !5, !noundef !{}68 %ashr = ashr <3 x i64> %val, %shift.amt69 ret <3 x i64> %ashr70}71 72define <4 x i64> @v4_ashr_metadata(ptr %arg0.ptr, ptr %arg1.ptr) {73; CHECK-LABEL: v4_ashr_metadata:74; CHECK: ; %bb.0:75; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)76; CHECK-NEXT: flat_load_dwordx4 v[4:7], v[2:3]77; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)78; CHECK-NEXT: flat_load_dwordx4 v[7:10], v[0:1]79; CHECK-NEXT: flat_load_dwordx4 v[11:14], v[0:1] offset:1680; CHECK-NEXT: flat_load_dwordx4 v[15:18], v[2:3] offset:1681; CHECK-NEXT: v_mov_b32_e32 v1, -182; CHECK-NEXT: v_mov_b32_e32 v3, -183; CHECK-NEXT: v_mov_b32_e32 v5, -184; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)85; CHECK-NEXT: v_mov_b32_e32 v7, -186; CHECK-NEXT: v_ashrrev_i32_e32 v0, v4, v887; CHECK-NEXT: v_ashrrev_i32_e32 v2, v6, v1088; CHECK-NEXT: v_ashrrev_i32_e32 v4, v15, v1289; CHECK-NEXT: v_ashrrev_i32_e32 v6, v17, v1490; CHECK-NEXT: s_setpc_b64 s[30:31]91 %val = load <4 x i64>, ptr %arg0.ptr, !range !6, !noundef !{}92 %shift.amt = load <4 x i64>, ptr %arg1.ptr, !range !7, !noundef !{}93 %ashr = ashr <4 x i64> %val, %shift.amt94 ret <4 x i64> %ashr95}96 97; Ranges used when transformation is valid98!0 = !{i64 -6000000000, i64 0}99!1 = !{i64 32, i64 64}100!2 = !{i64 -7000000000, i64 -1000}101!3 = !{i64 38, i64 64}102!4 = !{i64 -8000000000, i64 -2001}103!5 = !{i64 38, i64 60}104!6 = !{i64 -9000000000, i64 -3002}105!7 = !{i64 38, i64 50}106 107; Test that negative 64-bit values shifted by [2?-63] bits do NOT have108; a hi-result created by moving an all-ones constant.109 110define i64 @no_transform_scalar_ashr_metadata(ptr %arg0.ptr, ptr %arg1.ptr) {111; CHECK-LABEL: no_transform_scalar_ashr_metadata:112; CHECK: ; %bb.0:113; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)114; CHECK-NEXT: flat_load_dwordx2 v[4:5], v[0:1]115; CHECK-NEXT: flat_load_dword v6, v[2:3]116; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)117; CHECK-NEXT: v_ashrrev_i64 v[0:1], v6, v[4:5]118; CHECK-NEXT: s_setpc_b64 s[30:31]119 %val = load i64, ptr %arg0.ptr, !range !8, !noundef !{}120 %shift.amt = load i64, ptr %arg1.ptr, !range !9, !noundef !{}121 %ashr = ashr i64 %val, %shift.amt122 ret i64 %ashr123}124 125define <2 x i64> @no_transform_v2_ashr_metadata(ptr %arg0.ptr, ptr %arg1.ptr) {126; CHECK-LABEL: no_transform_v2_ashr_metadata:127; CHECK: ; %bb.0:128; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)129; CHECK-NEXT: flat_load_dwordx4 v[4:7], v[0:1]130; CHECK-NEXT: flat_load_dwordx4 v[8:11], v[2:3]131; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)132; CHECK-NEXT: v_ashrrev_i64 v[0:1], v8, v[4:5]133; CHECK-NEXT: v_ashrrev_i64 v[2:3], v10, v[6:7]134; CHECK-NEXT: s_setpc_b64 s[30:31]135 %val = load <2 x i64>, ptr %arg0.ptr, !range !10, !noundef !{}136 %shift.amt = load <2 x i64>, ptr %arg1.ptr, !range !11, !noundef !{}137 %ashr = ashr <2 x i64> %val, %shift.amt138 ret <2 x i64> %ashr139}140 141define <3 x i64> @no_transform_v3_ashr_metadata(ptr %arg0.ptr, ptr %arg1.ptr) {142; CHECK-LABEL: no_transform_v3_ashr_metadata:143; CHECK: ; %bb.0:144; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)145; CHECK-NEXT: flat_load_dwordx4 v[4:7], v[2:3]146; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)147; CHECK-NEXT: flat_load_dwordx4 v[7:10], v[0:1]148; CHECK-NEXT: flat_load_dwordx2 v[11:12], v[0:1] offset:16149; CHECK-NEXT: flat_load_dword v5, v[2:3] offset:16150; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)151; CHECK-NEXT: v_ashrrev_i64 v[0:1], v4, v[7:8]152; CHECK-NEXT: v_ashrrev_i64 v[2:3], v6, v[9:10]153; CHECK-NEXT: v_ashrrev_i64 v[4:5], v5, v[11:12]154; CHECK-NEXT: s_setpc_b64 s[30:31]155 %val = load <3 x i64>, ptr %arg0.ptr, !range !12, !noundef !{}156 %shift.amt = load <3 x i64>, ptr %arg1.ptr, !range !13, !noundef !{}157 %ashr = ashr <3 x i64> %val, %shift.amt158 ret <3 x i64> %ashr159}160 161define <4 x i64> @no_transform_v4_ashr_metadata(ptr %arg0.ptr, ptr %arg1.ptr) {162; CHECK-LABEL: no_transform_v4_ashr_metadata:163; CHECK: ; %bb.0:164; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)165; CHECK-NEXT: flat_load_dwordx4 v[4:7], v[2:3]166; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)167; CHECK-NEXT: flat_load_dwordx4 v[7:10], v[0:1]168; CHECK-NEXT: flat_load_dwordx4 v[11:14], v[0:1] offset:16169; CHECK-NEXT: flat_load_dwordx4 v[15:18], v[2:3] offset:16170; CHECK-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)171; CHECK-NEXT: v_ashrrev_i64 v[0:1], v4, v[7:8]172; CHECK-NEXT: v_ashrrev_i64 v[2:3], v6, v[9:10]173; CHECK-NEXT: v_ashrrev_i64 v[4:5], v15, v[11:12]174; CHECK-NEXT: v_ashrrev_i64 v[6:7], v17, v[13:14]175; CHECK-NEXT: s_setpc_b64 s[30:31]176 %val = load <4 x i64>, ptr %arg0.ptr, !range !14, !noundef !{}177 %shift.amt = load <4 x i64>, ptr %arg1.ptr, !range !15, !noundef !{}178 %ashr = ashr <4 x i64> %val, %shift.amt179 ret <4 x i64> %ashr180}181 182; Ranges used when transformation is invalid183!8 = !{i64 -10000000000, i64 0}184!9 = !{i64 29, i64 64}185!10 = !{i64 -11000000000, i64 -1000}186!11 = !{i64 28, i64 64}187!12 = !{i64 -12000000000, i64 -2001}188!13 = !{i64 27, i64 60}189!14 = !{i64 -13000000000, i64 -3002}190!15 = !{i64 26, i64 50}191 192