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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 < %s | FileCheck --check-prefix=GFX10 %s3; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 < %s | FileCheck --check-prefix=GFX12 %s4 5define amdgpu_cs void @_amdgpu_cs_main(float %0, i32 %1) {6; GFX10-LABEL: _amdgpu_cs_main:7; GFX10: ; %bb.0: ; %branch1_true8; GFX10-NEXT: v_mov_b32_e32 v2, 09; GFX10-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v110; GFX10-NEXT: v_mov_b32_e32 v1, 011; GFX10-NEXT: s_mov_b32 s4, 012; GFX10-NEXT: s_mov_b32 s1, 013; GFX10-NEXT: ; implicit-def: $sgpr214; GFX10-NEXT: s_inst_prefetch 0x115; GFX10-NEXT: s_branch .LBB0_216; GFX10-NEXT: .p2align 617; GFX10-NEXT: .LBB0_1: ; %Flow18; GFX10-NEXT: ; in Loop: Header=BB0_2 Depth=119; GFX10-NEXT: s_or_b32 exec_lo, exec_lo, s320; GFX10-NEXT: v_mov_b32_e32 v1, v021; GFX10-NEXT: s_and_b32 s0, exec_lo, s222; GFX10-NEXT: s_or_b32 s1, s0, s123; GFX10-NEXT: s_andn2_b32 exec_lo, exec_lo, s124; GFX10-NEXT: s_cbranch_execz .LBB0_425; GFX10-NEXT: .LBB0_2: ; %bb26; GFX10-NEXT: ; =>This Inner Loop Header: Depth=127; GFX10-NEXT: s_or_b32 s2, s2, exec_lo28; GFX10-NEXT: s_and_saveexec_b32 s3, vcc_lo29; GFX10-NEXT: s_cbranch_execz .LBB0_130; GFX10-NEXT: ; %bb.3: ; %branch2_merge31; GFX10-NEXT: ; in Loop: Header=BB0_2 Depth=132; GFX10-NEXT: s_mov_b32 s5, s433; GFX10-NEXT: s_mov_b32 s6, s434; GFX10-NEXT: s_mov_b32 s7, s435; GFX10-NEXT: s_mov_b32 s8, s436; GFX10-NEXT: s_mov_b32 s9, s437; GFX10-NEXT: s_mov_b32 s10, s438; GFX10-NEXT: s_mov_b32 s11, s439; GFX10-NEXT: s_mov_b32 s12, s440; GFX10-NEXT: s_mov_b32 s13, s441; GFX10-NEXT: s_mov_b32 s14, s442; GFX10-NEXT: s_mov_b32 s15, s443; GFX10-NEXT: s_andn2_b32 s2, s2, exec_lo44; GFX10-NEXT: image_sample_lz v1, [v2, v2, v1], s[8:15], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_3D45; GFX10-NEXT: s_waitcnt vmcnt(0)46; GFX10-NEXT: v_fma_f32 v1, v1, v0, 047; GFX10-NEXT: v_cmp_le_f32_e64 s0, 0, v148; GFX10-NEXT: s_and_b32 s0, s0, exec_lo49; GFX10-NEXT: s_or_b32 s2, s2, s050; GFX10-NEXT: s_branch .LBB0_151; GFX10-NEXT: .LBB0_4: ; %loop0_merge52; GFX10-NEXT: s_inst_prefetch 0x253; GFX10-NEXT: s_endpgm54;55; GFX12-LABEL: _amdgpu_cs_main:56; GFX12: ; %bb.0: ; %branch1_true57; GFX12-NEXT: v_mov_b32_e32 v2, 058; GFX12-NEXT: v_cmp_ne_u32_e32 vcc_lo, 0, v159; GFX12-NEXT: v_mov_b32_e32 v1, 060; GFX12-NEXT: s_mov_b32 s4, 061; GFX12-NEXT: s_mov_b32 s1, 062; GFX12-NEXT: ; implicit-def: $sgpr263; GFX12-NEXT: s_branch .LBB0_264; GFX12-NEXT: .LBB0_1: ; %Flow65; GFX12-NEXT: ; in Loop: Header=BB0_2 Depth=166; GFX12-NEXT: s_or_b32 exec_lo, exec_lo, s367; GFX12-NEXT: v_mov_b32_e32 v1, v068; GFX12-NEXT: s_and_b32 s0, exec_lo, s269; GFX12-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)70; GFX12-NEXT: s_or_b32 s1, s0, s171; GFX12-NEXT: s_and_not1_b32 exec_lo, exec_lo, s172; GFX12-NEXT: s_cbranch_execz .LBB0_473; GFX12-NEXT: .LBB0_2: ; %bb74; GFX12-NEXT: ; =>This Inner Loop Header: Depth=175; GFX12-NEXT: s_or_b32 s2, s2, exec_lo76; GFX12-NEXT: s_and_saveexec_b32 s3, vcc_lo77; GFX12-NEXT: s_cbranch_execz .LBB0_178; GFX12-NEXT: ; %bb.3: ; %branch2_merge79; GFX12-NEXT: ; in Loop: Header=BB0_2 Depth=180; GFX12-NEXT: s_mov_b32 s5, s481; GFX12-NEXT: s_mov_b32 s6, s482; GFX12-NEXT: s_mov_b32 s7, s483; GFX12-NEXT: s_mov_b32 s8, s484; GFX12-NEXT: s_mov_b32 s9, s485; GFX12-NEXT: s_mov_b32 s10, s486; GFX12-NEXT: s_mov_b32 s11, s487; GFX12-NEXT: s_mov_b32 s12, s488; GFX12-NEXT: s_mov_b32 s13, s489; GFX12-NEXT: s_mov_b32 s14, s490; GFX12-NEXT: s_mov_b32 s15, s491; GFX12-NEXT: s_and_not1_b32 s2, s2, exec_lo92; GFX12-NEXT: image_sample_lz v1, [v2, v2, v1], s[8:15], s[4:7] dmask:0x1 dim:SQ_RSRC_IMG_3D93; GFX12-NEXT: s_wait_samplecnt 0x094; GFX12-NEXT: v_fma_f32 v1, v1, v0, 095; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)96; GFX12-NEXT: v_cmp_le_f32_e64 s0, 0, v197; GFX12-NEXT: s_and_b32 s0, s0, exec_lo98; GFX12-NEXT: s_or_b32 s2, s2, s099; GFX12-NEXT: s_branch .LBB0_1100; GFX12-NEXT: .LBB0_4: ; %loop0_merge101; GFX12-NEXT: s_endpgm102branch1_true:103 br label %bb104 105bb: ; preds = %branch2_merge, %branch1_true106 %r1.8.vec.insert14.i1 = phi float [ 0.000000e+00, %branch1_true ], [ %0, %branch2_merge ]107 %i = icmp eq i32 %1, 0108 br i1 %i, label %loop0_merge, label %branch2_merge109 110branch2_merge: ; preds = %bb111 %i2 = call float @llvm.amdgcn.image.sample.lz.3d.f32.f32(i32 1, float 0.000000e+00, float 0.000000e+00, float %r1.8.vec.insert14.i1, <8 x i32> zeroinitializer, <4 x i32> zeroinitializer, i1 false, i32 0, i32 0)112 %i3 = call reassoc nnan nsz arcp contract afn float @llvm.fma.f32(float %i2, float %0, float 0.000000e+00)113 %i4 = fcmp ult float %i3, 0.000000e+00114 br i1 %i4, label %bb, label %loop0_merge115 116loop0_merge: ; preds = %branch2_merge, %bb117 ret void118}119 120; Function Attrs: nocallback nofree nosync nounwind readnone speculatable willreturn121declare float @llvm.fma.f32(float, float, float) #0122 123; Function Attrs: nounwind readonly willreturn124declare float @llvm.amdgcn.image.sample.lz.3d.f32.f32(i32 immarg, float, float, float, <8 x i32>, <4 x i32>, i1 immarg, i32 immarg, i32 immarg) #1125 126attributes #0 = { nocallback nofree nosync nounwind readnone speculatable willreturn }127attributes #1 = { nounwind readonly willreturn }128