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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx942 %s -o - | FileCheck %s --check-prefixes=GFX9423; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx908 %s -o - | FileCheck %s --check-prefixes=GFX9084 5define amdgpu_kernel void @matmul_kernel(i32 %a0, i32 %a1) {6; GFX942-LABEL: matmul_kernel:7; GFX942: ; %bb.0: ; %entry8; GFX942-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x09; GFX942-NEXT: s_mov_b32 s2, 010; GFX942-NEXT: v_mov_b32_e32 v0, 011; GFX942-NEXT: v_accvgpr_write_b32 a1, 012; GFX942-NEXT: s_mov_b32 s3, 013; GFX942-NEXT: s_waitcnt lgkmcnt(0)14; GFX942-NEXT: s_cmp_lg_u32 s0, 015; GFX942-NEXT: s_cselect_b64 s[0:1], -1, 016; GFX942-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]17; GFX942-NEXT: v_cmp_ne_u32_e64 s[0:1], 1, v118; GFX942-NEXT: s_branch .LBB0_219; GFX942-NEXT: .LBB0_1: ; %bb220; GFX942-NEXT: ; in Loop: Header=BB0_2 Depth=121; GFX942-NEXT: s_or_b32 s4, s3, 122; GFX942-NEXT: s_ashr_i32 s5, s3, 3123; GFX942-NEXT: s_mov_b32 s3, s224; GFX942-NEXT: v_mov_b64_e32 v[2:3], s[2:3]25; GFX942-NEXT: v_accvgpr_write_b32 a0, v026; GFX942-NEXT: v_accvgpr_mov_b32 a2, a127; GFX942-NEXT: v_accvgpr_mov_b32 a3, a128; GFX942-NEXT: s_and_b32 s3, s5, s429; GFX942-NEXT: s_nop 030; GFX942-NEXT: v_mfma_f32_16x16x16_f16 a[2:5], v[2:3], v[2:3], a[0:3]31; GFX942-NEXT: s_nop 632; GFX942-NEXT: v_accvgpr_read_b32 v0, a233; GFX942-NEXT: s_cbranch_execz .LBB0_434; GFX942-NEXT: .LBB0_2: ; %bb35; GFX942-NEXT: ; =>This Inner Loop Header: Depth=136; GFX942-NEXT: s_and_b64 vcc, exec, s[0:1]37; GFX942-NEXT: s_cbranch_vccz .LBB0_138; GFX942-NEXT: ; %bb.3:39; GFX942-NEXT: ; implicit-def: $sgpr340; GFX942-NEXT: ; implicit-def: $vgpr041; GFX942-NEXT: .LBB0_4: ; %common.ret42; GFX942-NEXT: s_endpgm43;44; GFX908-LABEL: matmul_kernel:45; GFX908: ; %bb.0: ; %entry46; GFX908-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x047; GFX908-NEXT: v_accvgpr_write_b32 a2, 048; GFX908-NEXT: v_accvgpr_write_b32 a1, 049; GFX908-NEXT: s_mov_b32 s2, 050; GFX908-NEXT: s_mov_b32 s3, 051; GFX908-NEXT: s_waitcnt lgkmcnt(0)52; GFX908-NEXT: s_cmp_lg_u32 s0, 053; GFX908-NEXT: s_cselect_b64 s[0:1], -1, 054; GFX908-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]55; GFX908-NEXT: v_cmp_ne_u32_e64 s[0:1], 1, v056; GFX908-NEXT: s_branch .LBB0_257; GFX908-NEXT: .LBB0_1: ; %bb258; GFX908-NEXT: ; in Loop: Header=BB0_2 Depth=159; GFX908-NEXT: s_nop 660; GFX908-NEXT: v_accvgpr_read_b32 v3, a261; GFX908-NEXT: s_or_b32 s4, s3, 162; GFX908-NEXT: s_ashr_i32 s5, s3, 3163; GFX908-NEXT: s_mov_b32 s3, s264; GFX908-NEXT: v_mov_b32_e32 v1, s265; GFX908-NEXT: v_mov_b32_e32 v2, s366; GFX908-NEXT: v_accvgpr_write_b32 a0, v367; GFX908-NEXT: v_accvgpr_read_b32 v4, a168; GFX908-NEXT: v_accvgpr_read_b32 v3, a169; GFX908-NEXT: s_and_b32 s3, s5, s470; GFX908-NEXT: v_accvgpr_write_b32 a2, v471; GFX908-NEXT: v_accvgpr_write_b32 a3, v372; GFX908-NEXT: s_nop 073; GFX908-NEXT: v_mfma_f32_16x16x16f16 a[2:5], v[1:2], v[1:2], a[0:3]74; GFX908-NEXT: s_cbranch_execz .LBB0_475; GFX908-NEXT: .LBB0_2: ; %bb76; GFX908-NEXT: ; =>This Inner Loop Header: Depth=177; GFX908-NEXT: s_and_b64 vcc, exec, s[0:1]78; GFX908-NEXT: s_cbranch_vccz .LBB0_179; GFX908-NEXT: ; %bb.3:80; GFX908-NEXT: ; implicit-def: $sgpr381; GFX908-NEXT: ; implicit-def: $agpr282; GFX908-NEXT: .LBB0_4: ; %common.ret83; GFX908-NEXT: s_endpgm84entry:85 br label %bb86 87bb:88 %i = phi { float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float } [ %i10, %bb2 ], [ zeroinitializer, %entry ]89 %i1 = phi i32 [ %i5, %bb2 ], [ 0, %entry ]90 %c0 = icmp ne i32 %a0, 091 br i1 %c0, label %bb2, label %bb1192 93bb2:94 %i3 = or i32 %i1, 195 %i4 = icmp slt i32 %i1, 096 %i5 = select i1 %i4, i32 %i3, i32 097 %i6 = extractvalue { float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float } %i, 12398 %i7 = insertelement <4 x float> zeroinitializer, float %i6, i32 099 %i8 = call <4 x float> @llvm.amdgcn.mfma.f32.16x16x16f16(<4 x half> zeroinitializer, <4 x half> zeroinitializer, <4 x float> %i7, i32 0, i32 0, i32 0)100 %i9 = extractelement <4 x float> %i8, i32 0101 %i10 = insertvalue { float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float } zeroinitializer, float %i9, 123102 br label %bb103 104bb11:105 %c1 = icmp ne i32 %a1, 0106 br i1 %c1, label %bb12, label %common.ret107 108common.ret:109 ret void110 111bb12:112 %i13 = extractvalue { float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float } %i, 0113 %i14 = insertelement <4 x float> zeroinitializer, float %i13, i32 0114 %i15 = insertelement <4 x float> %i14, float 0.000000e+00, i32 0115 %i16 = insertelement <4 x float> %i15, float 0.000000e+00, i32 0116 br label %common.ret117}118 119; Function Attrs: convergent nocallback nofree nosync nounwind willreturn memory(none)120declare <4 x float> @llvm.amdgcn.mfma.f32.16x16x16f16(<4 x half>, <4 x half>, <4 x float>, i32 immarg, i32 immarg, i32 immarg)121