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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 52# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx942 -run-pass si-fold-operands %s -o - | FileCheck %s3# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx942 -start-before=si-fold-operands -stop-after=register-coalescer %s -o - | FileCheck %s --check-prefixes=COALESCE4# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx908 -start-before=si-fold-operands -stop-after=register-coalescer %s -o - | FileCheck %s --check-prefixes=GFX908-COALESCE5 6...7---8name: test9tracksRegLiveness: true10body: |11 ; CHECK-LABEL: name: test12 ; CHECK: bb.0:13 ; CHECK-NEXT: successors: %bb.1(0x80000000)14 ; CHECK-NEXT: liveins: $sgpr4_sgpr515 ; CHECK-NEXT: {{ $}}16 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr4_sgpr517 ; CHECK-NEXT: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[COPY]](p4), 0, 0 :: (dereferenceable invariant load (s32), align 16, addrspace 4)18 ; CHECK-NEXT: S_BITCMP1_B32 killed [[S_LOAD_DWORD_IMM]], 0, implicit-def $scc19 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 020 ; CHECK-NEXT: [[S_CSELECT_B64_:%[0-9]+]]:sreg_64_xexec = S_CSELECT_B64 -1, 0, implicit $scc21 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec22 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:agpr_32 = COPY [[V_MOV_B32_e32_]]23 ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF24 ; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[S_CSELECT_B64_]], implicit $exec25 ; CHECK-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 [[V_CNDMASK_B32_e64_]], 1, implicit $exec26 ; CHECK-NEXT: {{ $}}27 ; CHECK-NEXT: bb.1:28 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)29 ; CHECK-NEXT: {{ $}}30 ; CHECK-NEXT: [[PHI:%[0-9]+]]:agpr_32 = PHI [[COPY1]], %bb.0, %24, %bb.331 ; CHECK-NEXT: [[PHI1:%[0-9]+]]:sreg_32 = PHI [[S_MOV_B32_]], %bb.0, %11, %bb.332 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[PHI]]33 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:agpr_32 = COPY [[PHI]]34 ; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64 = S_MOV_B64 -135 ; CHECK-NEXT: $vcc = S_AND_B64 $exec, [[V_CMP_NE_U32_e64_]], implicit-def $scc36 ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.3, implicit $vcc37 ; CHECK-NEXT: S_BRANCH %bb.238 ; CHECK-NEXT: {{ $}}39 ; CHECK-NEXT: bb.2:40 ; CHECK-NEXT: successors: %bb.3(0x80000000)41 ; CHECK-NEXT: {{ $}}42 ; CHECK-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[PHI1]], 1, implicit-def dead $scc43 ; CHECK-NEXT: [[S_ASHR_I32_:%[0-9]+]]:sreg_32 = S_ASHR_I32 [[PHI1]], 31, implicit-def dead $scc44 ; CHECK-NEXT: [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 killed [[S_ASHR_I32_]], killed [[S_OR_B32_]], implicit-def dead $scc45 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[V_MOV_B32_e32_]], %subreg.sub1, [[V_MOV_B32_e32_]], %subreg.sub2, [[V_MOV_B32_e32_]], %subreg.sub346 ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_MOV_B32_]], %subreg.sub0, [[S_MOV_B32_]], %subreg.sub147 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE1]]48 ; CHECK-NEXT: [[V_ACCVGPR_WRITE_B32_e64_:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec49 ; CHECK-NEXT: [[V_ACCVGPR_WRITE_B32_e64_1:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec50 ; CHECK-NEXT: [[V_ACCVGPR_WRITE_B32_e64_2:%[0-9]+]]:agpr_32 = V_ACCVGPR_WRITE_B32_e64 0, implicit $exec51 ; CHECK-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:areg_128_align2 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[V_ACCVGPR_WRITE_B32_e64_]], %subreg.sub1, [[V_ACCVGPR_WRITE_B32_e64_1]], %subreg.sub2, [[V_ACCVGPR_WRITE_B32_e64_2]], %subreg.sub352 ; CHECK-NEXT: [[V_MFMA_F32_16X16X16F16_e64_:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 [[COPY4]], [[COPY4]], killed [[REG_SEQUENCE2]], 0, 0, 0, implicit $mode, implicit $exec53 ; CHECK-NEXT: [[S_MOV_B64_1:%[0-9]+]]:sreg_64 = S_MOV_B64 054 ; CHECK-NEXT: {{ $}}55 ; CHECK-NEXT: bb.3:56 ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.1(0x40000000)57 ; CHECK-NEXT: {{ $}}58 ; CHECK-NEXT: [[PHI2:%[0-9]+]]:sreg_32 = PHI [[DEF]], %bb.1, [[S_AND_B32_]], %bb.259 ; CHECK-NEXT: [[PHI3:%[0-9]+]]:agpr_32 = PHI [[COPY3]], %bb.1, [[V_MFMA_F32_16X16X16F16_e64_]].sub0, %bb.260 ; CHECK-NEXT: [[PHI4:%[0-9]+]]:sreg_64_xexec = PHI [[S_MOV_B64_]], %bb.1, [[S_MOV_B64_1]], %bb.261 ; CHECK-NEXT: [[V_CNDMASK_B32_e64_1:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[PHI4]], implicit $exec62 ; CHECK-NEXT: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 [[V_CNDMASK_B32_e64_1]], 1, implicit $exec63 ; CHECK-NEXT: $vcc = S_AND_B64 $exec, [[V_CMP_NE_U32_e64_1]], implicit-def $scc64 ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit $vcc65 ; CHECK-NEXT: S_BRANCH %bb.466 ; CHECK-NEXT: {{ $}}67 ; CHECK-NEXT: bb.4:68 ; CHECK-NEXT: successors: %bb.5(0x80000000)69 ; CHECK-NEXT: {{ $}}70 ; CHECK-NEXT: bb.5:71 ; CHECK-NEXT: S_ENDPGM 072 ;73 ; COALESCE-LABEL: name: test74 ; COALESCE: bb.0:75 ; COALESCE-NEXT: successors: %bb.1(0x80000000)76 ; COALESCE-NEXT: liveins: $sgpr4_sgpr577 ; COALESCE-NEXT: {{ $}}78 ; COALESCE-NEXT: [[COPY:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr4_sgpr579 ; COALESCE-NEXT: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[COPY]](p4), 0, 0 :: (dereferenceable invariant load (s32), align 16, addrspace 4)80 ; COALESCE-NEXT: S_BITCMP1_B32 [[S_LOAD_DWORD_IMM]], 0, implicit-def $scc81 ; COALESCE-NEXT: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_64 = S_MOV_B32 082 ; COALESCE-NEXT: [[S_CSELECT_B64_:%[0-9]+]]:sreg_64_xexec = S_CSELECT_B64 -1, 0, implicit killed $scc83 ; COALESCE-NEXT: undef [[AV_MOV_:%[0-9]+]].sub0:areg_128_align2 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec84 ; COALESCE-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[S_CSELECT_B64_]], implicit $exec85 ; COALESCE-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 1, [[V_CNDMASK_B32_e64_]], implicit $exec86 ; COALESCE-NEXT: undef [[AV_MOV_1:%[0-9]+]].sub1:areg_128_align2 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec87 ; COALESCE-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 088 ; COALESCE-NEXT: {{ $}}89 ; COALESCE-NEXT: bb.1:90 ; COALESCE-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)91 ; COALESCE-NEXT: {{ $}}92 ; COALESCE-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[AV_MOV_]].sub093 ; COALESCE-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 -194 ; COALESCE-NEXT: $vcc = S_AND_B64 $exec, [[V_CMP_NE_U32_e64_]], implicit-def dead $scc95 ; COALESCE-NEXT: S_CBRANCH_VCCNZ %bb.3, implicit killed $vcc96 ; COALESCE-NEXT: S_BRANCH %bb.297 ; COALESCE-NEXT: {{ $}}98 ; COALESCE-NEXT: bb.2:99 ; COALESCE-NEXT: successors: %bb.3(0x80000000)100 ; COALESCE-NEXT: {{ $}}101 ; COALESCE-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_MOV_B32_1]], 1, implicit-def dead $scc102 ; COALESCE-NEXT: [[S_ASHR_I32_:%[0-9]+]]:sreg_32 = S_ASHR_I32 [[S_MOV_B32_1]], 31, implicit-def dead $scc103 ; COALESCE-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_ASHR_I32_]], [[S_OR_B32_]], implicit-def dead $scc104 ; COALESCE-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_64 = COPY [[S_MOV_B32_]].sub0105 ; COALESCE-NEXT: [[COPY2:%[0-9]+]]:vreg_64_align2 = COPY [[S_MOV_B32_]]106 ; COALESCE-NEXT: [[AV_MOV_1:%[0-9]+]].sub0:areg_128_align2 = COPY [[COPY1]]107 ; COALESCE-NEXT: [[AV_MOV_1:%[0-9]+]].sub2:areg_128_align2 = COPY [[AV_MOV_1]].sub1108 ; COALESCE-NEXT: [[AV_MOV_1:%[0-9]+]].sub3:areg_128_align2 = COPY [[AV_MOV_1]].sub1109 ; COALESCE-NEXT: [[AV_MOV_:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 [[COPY2]], [[COPY2]], [[AV_MOV_1]], 0, 0, 0, implicit $mode, implicit $exec110 ; COALESCE-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 0111 ; COALESCE-NEXT: {{ $}}112 ; COALESCE-NEXT: bb.3:113 ; COALESCE-NEXT: successors: %bb.4(0x40000000), %bb.1(0x40000000)114 ; COALESCE-NEXT: {{ $}}115 ; COALESCE-NEXT: [[V_CNDMASK_B32_e64_1:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[S_MOV_B64_]], implicit $exec116 ; COALESCE-NEXT: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 1, [[V_CNDMASK_B32_e64_1]], implicit $exec117 ; COALESCE-NEXT: $vcc = S_AND_B64 $exec, [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc118 ; COALESCE-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit killed $vcc119 ; COALESCE-NEXT: S_BRANCH %bb.4120 ; COALESCE-NEXT: {{ $}}121 ; COALESCE-NEXT: bb.4:122 ; COALESCE-NEXT: successors: %bb.5(0x80000000)123 ; COALESCE-NEXT: {{ $}}124 ; COALESCE-NEXT: bb.5:125 ; COALESCE-NEXT: S_ENDPGM 0126 ;127 ; GFX908-COALESCE-LABEL: name: test128 ; GFX908-COALESCE: bb.0:129 ; GFX908-COALESCE-NEXT: successors: %bb.1(0x80000000)130 ; GFX908-COALESCE-NEXT: liveins: $sgpr4_sgpr5131 ; GFX908-COALESCE-NEXT: {{ $}}132 ; GFX908-COALESCE-NEXT: [[COPY:%[0-9]+]]:sgpr_64(p4) = COPY $sgpr4_sgpr5133 ; GFX908-COALESCE-NEXT: [[S_LOAD_DWORD_IMM:%[0-9]+]]:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM [[COPY]](p4), 0, 0 :: (dereferenceable invariant load (s32), align 16, addrspace 4)134 ; GFX908-COALESCE-NEXT: S_BITCMP1_B32 [[S_LOAD_DWORD_IMM]], 0, implicit-def $scc135 ; GFX908-COALESCE-NEXT: undef [[S_MOV_B32_:%[0-9]+]].sub0:sgpr_64 = S_MOV_B32 0136 ; GFX908-COALESCE-NEXT: [[S_CSELECT_B64_:%[0-9]+]]:sreg_64_xexec = S_CSELECT_B64 -1, 0, implicit killed $scc137 ; GFX908-COALESCE-NEXT: undef [[AV_MOV_:%[0-9]+]].sub0:areg_128_align2 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec138 ; GFX908-COALESCE-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[S_CSELECT_B64_]], implicit $exec139 ; GFX908-COALESCE-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 1, [[V_CNDMASK_B32_e64_]], implicit $exec140 ; GFX908-COALESCE-NEXT: undef [[AV_MOV_1:%[0-9]+]].sub1:areg_128_align2 = AV_MOV_B32_IMM_PSEUDO 0, implicit $exec141 ; GFX908-COALESCE-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_MOV_B32 0142 ; GFX908-COALESCE-NEXT: {{ $}}143 ; GFX908-COALESCE-NEXT: bb.1:144 ; GFX908-COALESCE-NEXT: successors: %bb.2(0x40000000), %bb.3(0x40000000)145 ; GFX908-COALESCE-NEXT: {{ $}}146 ; GFX908-COALESCE-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[AV_MOV_]].sub0147 ; GFX908-COALESCE-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 -1148 ; GFX908-COALESCE-NEXT: $vcc = S_AND_B64 $exec, [[V_CMP_NE_U32_e64_]], implicit-def dead $scc149 ; GFX908-COALESCE-NEXT: S_CBRANCH_VCCNZ %bb.3, implicit killed $vcc150 ; GFX908-COALESCE-NEXT: S_BRANCH %bb.2151 ; GFX908-COALESCE-NEXT: {{ $}}152 ; GFX908-COALESCE-NEXT: bb.2:153 ; GFX908-COALESCE-NEXT: successors: %bb.3(0x80000000)154 ; GFX908-COALESCE-NEXT: {{ $}}155 ; GFX908-COALESCE-NEXT: [[S_OR_B32_:%[0-9]+]]:sreg_32 = S_OR_B32 [[S_MOV_B32_1]], 1, implicit-def dead $scc156 ; GFX908-COALESCE-NEXT: [[S_ASHR_I32_:%[0-9]+]]:sreg_32 = S_ASHR_I32 [[S_MOV_B32_1]], 31, implicit-def dead $scc157 ; GFX908-COALESCE-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 [[S_ASHR_I32_]], [[S_OR_B32_]], implicit-def dead $scc158 ; GFX908-COALESCE-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_64 = COPY [[S_MOV_B32_]].sub0159 ; GFX908-COALESCE-NEXT: [[COPY2:%[0-9]+]]:vreg_64_align2 = COPY [[S_MOV_B32_]]160 ; GFX908-COALESCE-NEXT: [[AV_MOV_1:%[0-9]+]].sub0:areg_128_align2 = COPY [[COPY1]]161 ; GFX908-COALESCE-NEXT: [[AV_MOV_1:%[0-9]+]].sub2:areg_128_align2 = COPY [[AV_MOV_1]].sub1162 ; GFX908-COALESCE-NEXT: [[AV_MOV_1:%[0-9]+]].sub3:areg_128_align2 = COPY [[AV_MOV_1]].sub1163 ; GFX908-COALESCE-NEXT: [[AV_MOV_:%[0-9]+]]:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 [[COPY2]], [[COPY2]], [[AV_MOV_1]], 0, 0, 0, implicit $mode, implicit $exec164 ; GFX908-COALESCE-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 0165 ; GFX908-COALESCE-NEXT: {{ $}}166 ; GFX908-COALESCE-NEXT: bb.3:167 ; GFX908-COALESCE-NEXT: successors: %bb.4(0x40000000), %bb.1(0x40000000)168 ; GFX908-COALESCE-NEXT: {{ $}}169 ; GFX908-COALESCE-NEXT: [[V_CNDMASK_B32_e64_1:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[S_MOV_B64_]], implicit $exec170 ; GFX908-COALESCE-NEXT: [[V_CMP_NE_U32_e64_1:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 1, [[V_CNDMASK_B32_e64_1]], implicit $exec171 ; GFX908-COALESCE-NEXT: $vcc = S_AND_B64 $exec, [[V_CMP_NE_U32_e64_1]], implicit-def dead $scc172 ; GFX908-COALESCE-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit killed $vcc173 ; GFX908-COALESCE-NEXT: S_BRANCH %bb.4174 ; GFX908-COALESCE-NEXT: {{ $}}175 ; GFX908-COALESCE-NEXT: bb.4:176 ; GFX908-COALESCE-NEXT: successors: %bb.5(0x80000000)177 ; GFX908-COALESCE-NEXT: {{ $}}178 ; GFX908-COALESCE-NEXT: bb.5:179 ; GFX908-COALESCE-NEXT: S_ENDPGM 0180 bb.0:181 successors: %bb.1182 liveins: $sgpr4_sgpr5183 184 %0:sgpr_64(p4) = COPY $sgpr4_sgpr5185 %1:sreg_32_xm0_xexec = S_LOAD_DWORD_IMM %0(p4), 0, 0 :: (dereferenceable invariant load (s32), align 16, addrspace 4)186 S_BITCMP1_B32 killed %1, 0, implicit-def $scc187 %2:sgpr_32 = S_MOV_B32 0188 %3:sreg_64_xexec = S_CSELECT_B64 -1, 0, implicit $scc189 %4:vgpr_32 = V_MOV_B32_e32 0, implicit $exec190 %5:sreg_32 = IMPLICIT_DEF191 %6:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %3, implicit $exec192 %7:sreg_64_xexec = V_CMP_NE_U32_e64 %6, 1, implicit $exec193 194 bb.1:195 successors: %bb.2, %bb.3196 197 %8:vgpr_32 = PHI %4, %bb.0, %9, %bb.3198 %10:sreg_32 = PHI %2, %bb.0, %11, %bb.3199 %12:agpr_32 = COPY %8200 %13:sreg_64 = S_MOV_B64 -1201 $vcc = S_AND_B64 $exec, %7, implicit-def $scc202 S_CBRANCH_VCCNZ %bb.3, implicit $vcc203 S_BRANCH %bb.2204 205 bb.2:206 successors: %bb.3207 208 %14:sreg_32 = S_OR_B32 %10, 1, implicit-def dead $scc209 %15:sreg_32 = S_ASHR_I32 %10, 31, implicit-def dead $scc210 %16:sreg_32 = S_AND_B32 killed %15, killed %14, implicit-def dead $scc211 %17:vreg_128_align2 = REG_SEQUENCE %8, %subreg.sub0, %4, %subreg.sub1, %4, %subreg.sub2, %4, %subreg.sub3212 %18:sreg_64 = REG_SEQUENCE %2, %subreg.sub0, %2, %subreg.sub1213 %19:vreg_64_align2 = COPY %18214 %20:areg_128_align2 = COPY %17215 %21:areg_128_align2 = V_MFMA_F32_16X16X16F16_e64 %19, %19, killed %20, 0, 0, 0, implicit $mode, implicit $exec216 %22:vgpr_32 = COPY %21.sub0217 %23:sreg_64 = S_MOV_B64 0218 219 bb.3:220 successors: %bb.4, %bb.1221 222 %11:sreg_32 = PHI %5, %bb.1, %16, %bb.2223 %24:agpr_32 = PHI %12, %bb.1, %21.sub0, %bb.2224 %25:sreg_64_xexec = PHI %13, %bb.1, %23, %bb.2225 %9:vgpr_32 = COPY %24226 %26:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %25, implicit $exec227 %27:sreg_64_xexec = V_CMP_NE_U32_e64 %26, 1, implicit $exec228 $vcc = S_AND_B64 $exec, %27, implicit-def $scc229 S_CBRANCH_VCCNZ %bb.1, implicit $vcc230 S_BRANCH %bb.4231 232 bb.4:233 successors: %bb.5234 235 bb.5:236 S_ENDPGM 0237 238...239