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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 53; RUN: opt -mtriple=amdgcn -mcpu=gfx900 -amdgpu-aa -amdgpu-aa-wrapper -amdgpu-annotate-uniform -S < %s | FileCheck %s4; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -amdgpu-atomic-optimizer-strategy=None < %s | FileCheck -check-prefix=GCN %s5 6; Check that barrier or fence in between of loads is not considered a clobber7; for the purpose of converting vector loads into scalar.8 9@LDS = linkonce_odr hidden local_unnamed_addr addrspace(3) global i32 poison10 11define amdgpu_kernel void @simple_barrier(ptr addrspace(1) %arg) {12; CHECK-LABEL: @simple_barrier(13; CHECK-NEXT: bb:14; CHECK-NEXT: [[I:%.*]] = load i32, ptr addrspace(1) [[ARG:%.*]], align 4, !amdgpu.noclobber !015; CHECK-NEXT: fence syncscope("workgroup") release16; CHECK-NEXT: tail call void @llvm.amdgcn.s.barrier()17; CHECK-NEXT: fence syncscope("workgroup") acquire18; CHECK-NEXT: tail call void @llvm.amdgcn.wave.barrier()19; CHECK-NEXT: [[I1:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[ARG]], i64 1, !amdgpu.uniform !020; CHECK-NEXT: [[I2:%.*]] = load i32, ptr addrspace(1) [[I1]], align 4, !amdgpu.noclobber !021; CHECK-NEXT: [[I3:%.*]] = add i32 [[I2]], [[I]]22; CHECK-NEXT: [[I4:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[ARG]], i64 223; CHECK-NEXT: store i32 [[I3]], ptr addrspace(1) [[I4]], align 424; CHECK-NEXT: ret void25;26; GCN-LABEL: simple_barrier:27; GCN: ; %bb.0: ; %bb28; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2429; GCN-NEXT: v_mov_b32_e32 v0, 030; GCN-NEXT: s_waitcnt lgkmcnt(0)31; GCN-NEXT: s_load_dword s2, s[0:1], 0x032; GCN-NEXT: s_waitcnt lgkmcnt(0)33; GCN-NEXT: s_barrier34; GCN-NEXT: ; wave barrier35; GCN-NEXT: s_load_dword s3, s[0:1], 0x436; GCN-NEXT: s_waitcnt lgkmcnt(0)37; GCN-NEXT: s_add_i32 s2, s3, s238; GCN-NEXT: v_mov_b32_e32 v1, s239; GCN-NEXT: global_store_dword v0, v1, s[0:1] offset:840; GCN-NEXT: s_endpgm41bb:42 %i = load i32, ptr addrspace(1) %arg, align 443 fence syncscope("workgroup") release44 tail call void @llvm.amdgcn.s.barrier()45 fence syncscope("workgroup") acquire46 tail call void @llvm.amdgcn.wave.barrier()47 %i1 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 148 %i2 = load i32, ptr addrspace(1) %i1, align 449 %i3 = add i32 %i2, %i50 %i4 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 251 store i32 %i3, ptr addrspace(1) %i4, align 452 ret void53}54 55define amdgpu_kernel void @memory_phi_no_clobber(ptr addrspace(1) %arg, i1 %cond) {56; CHECK-LABEL: @memory_phi_no_clobber(57; CHECK-NEXT: bb:58; CHECK-NEXT: [[I:%.*]] = load i32, ptr addrspace(1) [[ARG:%.*]], align 4, !amdgpu.noclobber !059; CHECK-NEXT: br i1 %cond, label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]], !amdgpu.uniform !060; CHECK: if.then:61; CHECK-NEXT: tail call void @llvm.amdgcn.s.barrier()62; CHECK-NEXT: br label [[IF_END:%.*]], !amdgpu.uniform !063; CHECK: if.else:64; CHECK-NEXT: fence syncscope("workgroup") release65; CHECK-NEXT: br label [[IF_END]], !amdgpu.uniform !066; CHECK: if.end:67; CHECK-NEXT: [[I1:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[ARG]], i64 1, !amdgpu.uniform !068; CHECK-NEXT: [[I2:%.*]] = load i32, ptr addrspace(1) [[I1]], align 4, !amdgpu.noclobber !069; CHECK-NEXT: [[I3:%.*]] = add i32 [[I2]], [[I]]70; CHECK-NEXT: [[I4:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[ARG]], i64 271; CHECK-NEXT: store i32 [[I3]], ptr addrspace(1) [[I4]], align 472; CHECK-NEXT: ret void73;74; GCN-LABEL: memory_phi_no_clobber:75; GCN: ; %bb.0: ; %bb76; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2477; GCN-NEXT: s_load_dword s2, s[4:5], 0x2c78; GCN-NEXT: s_waitcnt lgkmcnt(0)79; GCN-NEXT: s_bitcmp0_b32 s2, 080; GCN-NEXT: s_load_dword s4, s[0:1], 0x081; GCN-NEXT: s_mov_b64 s[2:3], -182; GCN-NEXT: s_cbranch_scc0 .LBB1_283; GCN-NEXT: ; %bb.1: ; %if.else84; GCN-NEXT: s_waitcnt lgkmcnt(0)85; GCN-NEXT: s_mov_b64 s[2:3], 086; GCN-NEXT: .LBB1_2: ; %Flow87; GCN-NEXT: s_andn2_b64 vcc, exec, s[2:3]88; GCN-NEXT: s_cbranch_vccnz .LBB1_489; GCN-NEXT: ; %bb.3: ; %if.then90; GCN-NEXT: s_waitcnt lgkmcnt(0)91; GCN-NEXT: s_barrier92; GCN-NEXT: .LBB1_4: ; %if.end93; GCN-NEXT: s_load_dword s2, s[0:1], 0x494; GCN-NEXT: v_mov_b32_e32 v0, 095; GCN-NEXT: s_waitcnt lgkmcnt(0)96; GCN-NEXT: s_add_i32 s2, s2, s497; GCN-NEXT: v_mov_b32_e32 v1, s298; GCN-NEXT: global_store_dword v0, v1, s[0:1] offset:899; GCN-NEXT: s_endpgm100bb:101 %i = load i32, ptr addrspace(1) %arg, align 4102 br i1 %cond, label %if.then, label %if.else103 104if.then:105 tail call void @llvm.amdgcn.s.barrier()106 br label %if.end107 108if.else:109 fence syncscope("workgroup") release110 br label %if.end111 112if.end:113 %i1 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 1114 %i2 = load i32, ptr addrspace(1) %i1, align 4115 %i3 = add i32 %i2, %i116 %i4 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 2117 store i32 %i3, ptr addrspace(1) %i4, align 4118 ret void119}120 121define amdgpu_kernel void @memory_phi_clobber1(ptr addrspace(1) %arg, i1 %cond) {122; CHECK-LABEL: @memory_phi_clobber1(123; CHECK-NEXT: bb:124; CHECK-NEXT: [[I:%.*]] = load i32, ptr addrspace(1) [[ARG:%.*]], align 4, !amdgpu.noclobber !0125; CHECK-NEXT: br i1 %cond, label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]], !amdgpu.uniform !0126; CHECK: if.then:127; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[ARG]], i64 3128; CHECK-NEXT: store i32 1, ptr addrspace(1) [[GEP]], align 4129; CHECK-NEXT: br label [[IF_END:%.*]], !amdgpu.uniform !0130; CHECK: if.else:131; CHECK-NEXT: tail call void @llvm.amdgcn.s.barrier()132; CHECK-NEXT: br label [[IF_END]], !amdgpu.uniform !0133; CHECK: if.end:134; CHECK-NEXT: [[I1:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[ARG]], i64 1, !amdgpu.uniform !0135; CHECK-NEXT: [[I2:%.*]] = load i32, ptr addrspace(1) [[I1]], align 4136; CHECK-NEXT: [[I3:%.*]] = add i32 [[I2]], [[I]]137; CHECK-NEXT: [[I4:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[ARG]], i64 2138; CHECK-NEXT: store i32 [[I3]], ptr addrspace(1) [[I4]], align 4139; CHECK-NEXT: ret void140;141; GCN-LABEL: memory_phi_clobber1:142; GCN: ; %bb.0: ; %bb143; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24144; GCN-NEXT: s_load_dword s2, s[4:5], 0x2c145; GCN-NEXT: s_waitcnt lgkmcnt(0)146; GCN-NEXT: s_bitcmp0_b32 s2, 0147; GCN-NEXT: s_load_dword s4, s[0:1], 0x0148; GCN-NEXT: s_mov_b64 s[2:3], -1149; GCN-NEXT: s_cbranch_scc0 .LBB2_2150; GCN-NEXT: ; %bb.1: ; %if.else151; GCN-NEXT: s_waitcnt lgkmcnt(0)152; GCN-NEXT: s_barrier153; GCN-NEXT: s_mov_b64 s[2:3], 0154; GCN-NEXT: .LBB2_2: ; %Flow155; GCN-NEXT: s_andn2_b64 vcc, exec, s[2:3]156; GCN-NEXT: s_cbranch_vccnz .LBB2_4157; GCN-NEXT: ; %bb.3: ; %if.then158; GCN-NEXT: v_mov_b32_e32 v0, 0159; GCN-NEXT: v_mov_b32_e32 v1, 1160; GCN-NEXT: global_store_dword v0, v1, s[0:1] offset:12161; GCN-NEXT: .LBB2_4: ; %if.end162; GCN-NEXT: v_mov_b32_e32 v0, 0163; GCN-NEXT: global_load_dword v1, v0, s[0:1] offset:4164; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)165; GCN-NEXT: v_add_u32_e32 v1, s4, v1166; GCN-NEXT: global_store_dword v0, v1, s[0:1] offset:8167; GCN-NEXT: s_endpgm168bb:169 %i = load i32, ptr addrspace(1) %arg, align 4170 br i1 %cond, label %if.then, label %if.else171 172if.then:173 %gep = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 3174 store i32 1, ptr addrspace(1) %gep, align 4175 br label %if.end176 177if.else:178 tail call void @llvm.amdgcn.s.barrier()179 br label %if.end180 181if.end:182 %i1 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 1183 %i2 = load i32, ptr addrspace(1) %i1, align 4184 %i3 = add i32 %i2, %i185 %i4 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 2186 store i32 %i3, ptr addrspace(1) %i4, align 4187 ret void188}189 190define amdgpu_kernel void @memory_phi_clobber2(ptr addrspace(1) %arg, i1 %cond) {191; CHECK-LABEL: @memory_phi_clobber2(192; CHECK-NEXT: bb:193; CHECK-NEXT: [[I:%.*]] = load i32, ptr addrspace(1) [[ARG:%.*]], align 4, !amdgpu.noclobber !0194; CHECK-NEXT: br i1 %cond, label [[IF_THEN:%.*]], label [[IF_ELSE:%.*]], !amdgpu.uniform !0195; CHECK: if.then:196; CHECK-NEXT: tail call void @llvm.amdgcn.s.barrier()197; CHECK-NEXT: br label [[IF_END:%.*]], !amdgpu.uniform !0198; CHECK: if.else:199; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[ARG]], i64 3200; CHECK-NEXT: store i32 1, ptr addrspace(1) [[GEP]], align 4201; CHECK-NEXT: br label [[IF_END]], !amdgpu.uniform !0202; CHECK: if.end:203; CHECK-NEXT: [[I1:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[ARG]], i64 1, !amdgpu.uniform !0204; CHECK-NEXT: [[I2:%.*]] = load i32, ptr addrspace(1) [[I1]], align 4205; CHECK-NEXT: [[I3:%.*]] = add i32 [[I2]], [[I]]206; CHECK-NEXT: [[I4:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[ARG]], i64 2207; CHECK-NEXT: store i32 [[I3]], ptr addrspace(1) [[I4]], align 4208; CHECK-NEXT: ret void209;210; GCN-LABEL: memory_phi_clobber2:211; GCN: ; %bb.0: ; %bb212; GCN-NEXT: s_load_dword s2, s[4:5], 0x2c213; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24214; GCN-NEXT: s_waitcnt lgkmcnt(0)215; GCN-NEXT: s_bitcmp0_b32 s2, 0216; GCN-NEXT: s_mov_b64 s[2:3], -1217; GCN-NEXT: s_cbranch_scc0 .LBB3_2218; GCN-NEXT: ; %bb.1: ; %if.else219; GCN-NEXT: v_mov_b32_e32 v0, 0220; GCN-NEXT: v_mov_b32_e32 v1, 1221; GCN-NEXT: global_store_dword v0, v1, s[0:1] offset:12222; GCN-NEXT: s_mov_b64 s[2:3], 0223; GCN-NEXT: .LBB3_2: ; %Flow224; GCN-NEXT: s_load_dword s4, s[0:1], 0x0225; GCN-NEXT: s_andn2_b64 vcc, exec, s[2:3]226; GCN-NEXT: s_cbranch_vccnz .LBB3_4227; GCN-NEXT: ; %bb.3: ; %if.then228; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)229; GCN-NEXT: s_barrier230; GCN-NEXT: .LBB3_4: ; %if.end231; GCN-NEXT: v_mov_b32_e32 v0, 0232; GCN-NEXT: global_load_dword v1, v0, s[0:1] offset:4233; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)234; GCN-NEXT: v_add_u32_e32 v1, s4, v1235; GCN-NEXT: global_store_dword v0, v1, s[0:1] offset:8236; GCN-NEXT: s_endpgm237bb:238 %i = load i32, ptr addrspace(1) %arg, align 4239 br i1 %cond, label %if.then, label %if.else240 241if.then:242 tail call void @llvm.amdgcn.s.barrier()243 br label %if.end244 245if.else:246 %gep = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 3247 store i32 1, ptr addrspace(1) %gep, align 4248 br label %if.end249 250if.end:251 %i1 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 1252 %i2 = load i32, ptr addrspace(1) %i1, align 4253 %i3 = add i32 %i2, %i254 %i4 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 2255 store i32 %i3, ptr addrspace(1) %i4, align 4256 ret void257}258 259define amdgpu_kernel void @no_clobbering_loop1(ptr addrspace(1) %arg, i1 %cc) {260; CHECK-LABEL: @no_clobbering_loop1(261; CHECK-NEXT: bb:262; CHECK-NEXT: [[I:%.*]] = load i32, ptr addrspace(1) [[ARG:%.*]], align 4, !amdgpu.noclobber !0263; CHECK-NEXT: br label [[WHILE_COND:%.*]], !amdgpu.uniform !0264; CHECK: while.cond:265; CHECK-NEXT: [[I1:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[ARG]], i64 1, !amdgpu.uniform !0266; CHECK-NEXT: [[I2:%.*]] = load i32, ptr addrspace(1) [[I1]], align 4, !amdgpu.noclobber !0267; CHECK-NEXT: [[I3:%.*]] = add i32 [[I2]], [[I]]268; CHECK-NEXT: [[I4:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[ARG]], i64 2269; CHECK-NEXT: store i32 [[I3]], ptr addrspace(1) [[I4]], align 4270; CHECK-NEXT: tail call void @llvm.amdgcn.wave.barrier()271; CHECK-NEXT: br i1 [[CC:%.*]], label [[WHILE_COND]], label [[END:%.*]], !amdgpu.uniform !0272; CHECK: end:273; CHECK-NEXT: ret void274;275; GCN-LABEL: no_clobbering_loop1:276; GCN: ; %bb.0: ; %bb277; GCN-NEXT: s_load_dword s0, s[4:5], 0x2c278; GCN-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x24279; GCN-NEXT: v_mov_b32_e32 v0, 0280; GCN-NEXT: s_waitcnt lgkmcnt(0)281; GCN-NEXT: s_bitcmp1_b32 s0, 0282; GCN-NEXT: s_load_dword s4, s[2:3], 0x0283; GCN-NEXT: s_cselect_b64 s[0:1], -1, 0284; GCN-NEXT: s_xor_b64 s[0:1], s[0:1], -1285; GCN-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]286; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 1, v1287; GCN-NEXT: .LBB4_1: ; %while.cond288; GCN-NEXT: ; =>This Inner Loop Header: Depth=1289; GCN-NEXT: s_load_dword s5, s[2:3], 0x4290; GCN-NEXT: s_and_b64 vcc, exec, s[0:1]291; GCN-NEXT: s_waitcnt lgkmcnt(0)292; GCN-NEXT: s_add_i32 s5, s5, s4293; GCN-NEXT: v_mov_b32_e32 v1, s5294; GCN-NEXT: global_store_dword v0, v1, s[2:3] offset:8295; GCN-NEXT: ; wave barrier296; GCN-NEXT: s_cbranch_vccnz .LBB4_1297; GCN-NEXT: ; %bb.2: ; %end298; GCN-NEXT: s_endpgm299bb:300 %i = load i32, ptr addrspace(1) %arg, align 4301 br label %while.cond302 303while.cond:304 %i1 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 1305 %i2 = load i32, ptr addrspace(1) %i1, align 4306 %i3 = add i32 %i2, %i307 %i4 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 2308 store i32 %i3, ptr addrspace(1) %i4, align 4309 tail call void @llvm.amdgcn.wave.barrier()310 br i1 %cc, label %while.cond, label %end311 312end:313 ret void314}315 316define amdgpu_kernel void @no_clobbering_loop2(ptr addrspace(1) noalias %arg, ptr addrspace(1) noalias %out, i32 %n) {317; CHECK-LABEL: @no_clobbering_loop2(318; CHECK-NEXT: bb:319; CHECK-NEXT: [[I:%.*]] = load i32, ptr addrspace(1) [[ARG:%.*]], align 4, !amdgpu.noclobber !0320; CHECK-NEXT: br label [[WHILE_COND:%.*]], !amdgpu.uniform !0321; CHECK: while.cond:322; CHECK-NEXT: [[C:%.*]] = phi i32 [ 0, [[BB:%.*]] ], [ [[INC:%.*]], [[WHILE_COND]] ]323; CHECK-NEXT: [[ACC:%.*]] = phi i32 [ [[I]], [[BB]] ], [ [[I3:%.*]], [[WHILE_COND]] ]324; CHECK-NEXT: [[I1:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[ARG]], i32 [[C]], !amdgpu.uniform !0325; CHECK-NEXT: [[I2:%.*]] = load i32, ptr addrspace(1) [[I1]], align 4, !amdgpu.noclobber !0326; CHECK-NEXT: [[I3]] = add i32 [[I2]], [[ACC]]327; CHECK-NEXT: tail call void @llvm.amdgcn.wave.barrier()328; CHECK-NEXT: [[INC]] = add nuw nsw i32 [[C]], 1329; CHECK-NEXT: [[CC:%.*]] = icmp eq i32 [[INC]], [[N:%.*]]330; CHECK-NEXT: br i1 [[CC]], label [[WHILE_COND]], label [[END:%.*]], !amdgpu.uniform !0331; CHECK: end:332; CHECK-NEXT: store i32 [[I3]], ptr addrspace(1) [[OUT:%.*]], align 4333; CHECK-NEXT: ret void334;335; GCN-LABEL: no_clobbering_loop2:336; GCN: ; %bb.0: ; %bb337; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24338; GCN-NEXT: s_load_dword s6, s[4:5], 0x34339; GCN-NEXT: s_waitcnt lgkmcnt(0)340; GCN-NEXT: s_load_dword s4, s[0:1], 0x0341; GCN-NEXT: .LBB5_1: ; %while.cond342; GCN-NEXT: ; =>This Inner Loop Header: Depth=1343; GCN-NEXT: s_load_dword s5, s[0:1], 0x0344; GCN-NEXT: ; wave barrier345; GCN-NEXT: s_waitcnt lgkmcnt(0)346; GCN-NEXT: s_add_i32 s4, s5, s4347; GCN-NEXT: s_add_u32 s0, s0, 4348; GCN-NEXT: s_addc_u32 s1, s1, 0349; GCN-NEXT: s_add_i32 s6, s6, -1350; GCN-NEXT: s_cmp_eq_u32 s6, 0351; GCN-NEXT: s_cbranch_scc1 .LBB5_1352; GCN-NEXT: ; %bb.2: ; %end353; GCN-NEXT: v_mov_b32_e32 v0, 0354; GCN-NEXT: v_mov_b32_e32 v1, s4355; GCN-NEXT: global_store_dword v0, v1, s[2:3]356; GCN-NEXT: s_endpgm357bb:358 %i = load i32, ptr addrspace(1) %arg, align 4359 br label %while.cond360 361while.cond:362 %c = phi i32 [ 0, %bb ], [ %inc, %while.cond ]363 %acc = phi i32 [ %i, %bb ], [ %i3, %while.cond ]364 %i1 = getelementptr inbounds i32, ptr addrspace(1) %arg, i32 %c365 %i2 = load i32, ptr addrspace(1) %i1, align 4366 %i3 = add i32 %i2, %acc367 tail call void @llvm.amdgcn.wave.barrier()368 %inc = add nuw nsw i32 %c, 1369 %cc = icmp eq i32 %inc, %n370 br i1 %cc, label %while.cond, label %end371 372end:373 store i32 %i3, ptr addrspace(1) %out, align 4374 ret void375}376 377define amdgpu_kernel void @clobbering_loop(ptr addrspace(1) %arg, ptr addrspace(1) %out, i1 %cc) {378; CHECK-LABEL: @clobbering_loop(379; CHECK-NEXT: bb:380; CHECK-NEXT: [[I:%.*]] = load i32, ptr addrspace(1) [[ARG:%.*]], align 4, !amdgpu.noclobber !0381; CHECK-NEXT: br label [[WHILE_COND:%.*]], !amdgpu.uniform !0382; CHECK: while.cond:383; CHECK-NEXT: [[I1:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[ARG]], i64 1, !amdgpu.uniform !0384; CHECK-NEXT: [[I2:%.*]] = load i32, ptr addrspace(1) [[I1]], align 4385; CHECK-NEXT: [[I3:%.*]] = add i32 [[I2]], [[I]]386; CHECK-NEXT: [[I4:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[OUT:%.*]], i64 1387; CHECK-NEXT: store i32 [[I3]], ptr addrspace(1) [[I4]], align 4388; CHECK-NEXT: tail call void @llvm.amdgcn.wave.barrier()389; CHECK-NEXT: br i1 [[CC:%.*]], label [[WHILE_COND]], label [[END:%.*]], !amdgpu.uniform !0390; CHECK: end:391; CHECK-NEXT: ret void392;393; GCN-LABEL: clobbering_loop:394; GCN: ; %bb.0: ; %bb395; GCN-NEXT: s_load_dword s0, s[4:5], 0x34396; GCN-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x24397; GCN-NEXT: v_mov_b32_e32 v0, 0398; GCN-NEXT: s_waitcnt lgkmcnt(0)399; GCN-NEXT: s_bitcmp1_b32 s0, 0400; GCN-NEXT: s_load_dword s2, s[8:9], 0x0401; GCN-NEXT: s_cselect_b64 s[0:1], -1, 0402; GCN-NEXT: s_xor_b64 s[0:1], s[0:1], -1403; GCN-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]404; GCN-NEXT: v_cmp_ne_u32_e64 s[0:1], 1, v1405; GCN-NEXT: .LBB6_1: ; %while.cond406; GCN-NEXT: ; =>This Inner Loop Header: Depth=1407; GCN-NEXT: global_load_dword v1, v0, s[8:9] offset:4408; GCN-NEXT: s_and_b64 vcc, exec, s[0:1]409; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)410; GCN-NEXT: v_add_u32_e32 v1, s2, v1411; GCN-NEXT: global_store_dword v0, v1, s[10:11] offset:4412; GCN-NEXT: ; wave barrier413; GCN-NEXT: s_cbranch_vccnz .LBB6_1414; GCN-NEXT: ; %bb.2: ; %end415; GCN-NEXT: s_endpgm416bb:417 %i = load i32, ptr addrspace(1) %arg, align 4418 br label %while.cond419 420while.cond:421 %i1 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 1422 %i2 = load i32, ptr addrspace(1) %i1, align 4423 %i3 = add i32 %i2, %i424 %i4 = getelementptr inbounds i32, ptr addrspace(1) %out, i64 1425 store i32 %i3, ptr addrspace(1) %i4, align 4426 tail call void @llvm.amdgcn.wave.barrier()427 br i1 %cc, label %while.cond, label %end428 429end:430 ret void431}432 433define amdgpu_kernel void @clobber_by_atomic_load(ptr addrspace(1) %arg) {434; CHECK-LABEL: @clobber_by_atomic_load(435; CHECK-NEXT: bb:436; CHECK-NEXT: [[I:%.*]] = load i32, ptr addrspace(1) [[ARG:%.*]], align 4, !amdgpu.noclobber !0437; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[ARG]], i64 2, !amdgpu.uniform !0438; CHECK-NEXT: [[VAL:%.*]] = load atomic i32, ptr addrspace(1) [[GEP]] seq_cst, align 4, !amdgpu.noclobber !0439; CHECK-NEXT: [[I1:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[ARG]], i64 3, !amdgpu.uniform !0440; CHECK-NEXT: [[I2:%.*]] = load i32, ptr addrspace(1) [[I1]], align 4441; CHECK-NEXT: [[I3:%.*]] = add i32 [[I2]], [[I]]442; CHECK-NEXT: [[I4:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[ARG]], i64 4443; CHECK-NEXT: store i32 [[I3]], ptr addrspace(1) [[I4]], align 4444; CHECK-NEXT: ret void445;446; GCN-LABEL: clobber_by_atomic_load:447; GCN: ; %bb.0: ; %bb448; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24449; GCN-NEXT: v_mov_b32_e32 v0, 0450; GCN-NEXT: s_waitcnt lgkmcnt(0)451; GCN-NEXT: s_load_dword s2, s[0:1], 0x0452; GCN-NEXT: s_waitcnt lgkmcnt(0)453; GCN-NEXT: global_load_dword v1, v0, s[0:1] offset:8 glc454; GCN-NEXT: s_waitcnt vmcnt(0)455; GCN-NEXT: buffer_wbinvl1_vol456; GCN-NEXT: global_load_dword v1, v0, s[0:1] offset:12457; GCN-NEXT: s_waitcnt vmcnt(0)458; GCN-NEXT: v_add_u32_e32 v1, s2, v1459; GCN-NEXT: global_store_dword v0, v1, s[0:1] offset:16460; GCN-NEXT: s_endpgm461bb:462 %i = load i32, ptr addrspace(1) %arg, align 4463 %gep = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 2464 %val = load atomic i32, ptr addrspace(1) %gep seq_cst, align 4465 %i1 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 3466 %i2 = load i32, ptr addrspace(1) %i1, align 4467 %i3 = add i32 %i2, %i468 %i4 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 4469 store i32 %i3, ptr addrspace(1) %i4, align 4470 ret void471}472 473define protected amdgpu_kernel void @no_alias_store(ptr addrspace(1) %in, ptr addrspace(1) %out) {474; CHECK-LABEL: @no_alias_store(475; CHECK-NEXT: entry:476; CHECK-NEXT: store i32 0, ptr addrspace(3) @LDS, align 4477; CHECK-NEXT: fence syncscope("workgroup") release478; CHECK-NEXT: tail call void @llvm.amdgcn.s.barrier()479; CHECK-NEXT: fence syncscope("workgroup") acquire480; CHECK-NEXT: [[LD:%.*]] = load i32, ptr addrspace(1) [[IN:%.*]], align 4, !amdgpu.noclobber !0481; CHECK-NEXT: store i32 [[LD]], ptr addrspace(1) [[OUT:%.*]], align 4482; CHECK-NEXT: ret void483;484; GCN-LABEL: no_alias_store:485; GCN: ; %bb.0: ; %entry486; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24487; GCN-NEXT: v_mov_b32_e32 v0, 0488; GCN-NEXT: ds_write_b32 v0, v0489; GCN-NEXT: s_waitcnt lgkmcnt(0)490; GCN-NEXT: s_barrier491; GCN-NEXT: s_load_dword s0, s[0:1], 0x0492; GCN-NEXT: s_waitcnt lgkmcnt(0)493; GCN-NEXT: v_mov_b32_e32 v1, s0494; GCN-NEXT: global_store_dword v0, v1, s[2:3]495; GCN-NEXT: s_endpgm496entry:497 store i32 0, ptr addrspace(3) @LDS, align 4498 fence syncscope("workgroup") release499 tail call void @llvm.amdgcn.s.barrier()500 fence syncscope("workgroup") acquire501 %ld = load i32, ptr addrspace(1) %in, align 4502 store i32 %ld, ptr addrspace(1) %out, align 4503 ret void504}505 506define protected amdgpu_kernel void @may_alias_store(ptr addrspace(1) %in, ptr addrspace(1) %out) {507; CHECK-LABEL: @may_alias_store(508; CHECK-NEXT: entry:509; CHECK-NEXT: store i32 0, ptr addrspace(1) [[OUT:%.*]], align 4510; CHECK-NEXT: fence syncscope("workgroup") release511; CHECK-NEXT: tail call void @llvm.amdgcn.s.barrier()512; CHECK-NEXT: fence syncscope("workgroup") acquire513; CHECK-NEXT: [[LD:%.*]] = load i32, ptr addrspace(1) [[IN:%.*]], align 4514; CHECK-NEXT: store i32 [[LD]], ptr addrspace(1) [[OUT]], align 4515; CHECK-NEXT: ret void516;517; GCN-LABEL: may_alias_store:518; GCN: ; %bb.0: ; %entry519; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24520; GCN-NEXT: v_mov_b32_e32 v0, 0521; GCN-NEXT: s_waitcnt lgkmcnt(0)522; GCN-NEXT: global_store_dword v0, v0, s[2:3]523; GCN-NEXT: s_waitcnt vmcnt(0)524; GCN-NEXT: s_barrier525; GCN-NEXT: global_load_dword v1, v0, s[0:1]526; GCN-NEXT: s_waitcnt vmcnt(0)527; GCN-NEXT: global_store_dword v0, v1, s[2:3]528; GCN-NEXT: s_endpgm529entry:530 store i32 0, ptr addrspace(1) %out, align 4531 fence syncscope("workgroup") release532 tail call void @llvm.amdgcn.s.barrier()533 fence syncscope("workgroup") acquire534 %ld = load i32, ptr addrspace(1) %in, align 4535 store i32 %ld, ptr addrspace(1) %out, align 4536 ret void537}538 539define protected amdgpu_kernel void @no_alias_volatile_store(ptr addrspace(1) %in, ptr addrspace(1) %out) {540; CHECK-LABEL: @no_alias_volatile_store(541; CHECK-NEXT: entry:542; CHECK-NEXT: store volatile i32 0, ptr addrspace(3) @LDS, align 4543; CHECK-NEXT: fence syncscope("workgroup") release544; CHECK-NEXT: tail call void @llvm.amdgcn.s.barrier()545; CHECK-NEXT: fence syncscope("workgroup") acquire546; CHECK-NEXT: [[LD:%.*]] = load i32, ptr addrspace(1) [[IN:%.*]], align 4, !amdgpu.noclobber !0547; CHECK-NEXT: store i32 [[LD]], ptr addrspace(1) [[OUT:%.*]], align 4548; CHECK-NEXT: ret void549;550; GCN-LABEL: no_alias_volatile_store:551; GCN: ; %bb.0: ; %entry552; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24553; GCN-NEXT: v_mov_b32_e32 v0, 0554; GCN-NEXT: ds_write_b32 v0, v0555; GCN-NEXT: s_waitcnt lgkmcnt(0)556; GCN-NEXT: s_barrier557; GCN-NEXT: s_load_dword s0, s[0:1], 0x0558; GCN-NEXT: s_waitcnt lgkmcnt(0)559; GCN-NEXT: v_mov_b32_e32 v1, s0560; GCN-NEXT: global_store_dword v0, v1, s[2:3]561; GCN-NEXT: s_endpgm562entry:563 store volatile i32 0, ptr addrspace(3) @LDS, align 4564 fence syncscope("workgroup") release565 tail call void @llvm.amdgcn.s.barrier()566 fence syncscope("workgroup") acquire567 %ld = load i32, ptr addrspace(1) %in, align 4568 store i32 %ld, ptr addrspace(1) %out, align 4569 ret void570}571 572define protected amdgpu_kernel void @no_alias_atomic_rmw_relaxed(ptr addrspace(1) %in, ptr addrspace(1) %out) {573; CHECK-LABEL: @no_alias_atomic_rmw_relaxed(574; CHECK-NEXT: entry:575; CHECK-NEXT: [[UNUSED:%.*]] = atomicrmw add ptr addrspace(3) @LDS, i32 5 monotonic, align 4576; CHECK-NEXT: [[LD:%.*]] = load i32, ptr addrspace(1) [[IN:%.*]], align 4, !amdgpu.noclobber !0577; CHECK-NEXT: store i32 [[LD]], ptr addrspace(1) [[OUT:%.*]], align 4578; CHECK-NEXT: ret void579;580; GCN-LABEL: no_alias_atomic_rmw_relaxed:581; GCN: ; %bb.0: ; %entry582; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24583; GCN-NEXT: v_mov_b32_e32 v0, 5584; GCN-NEXT: v_mov_b32_e32 v1, 0585; GCN-NEXT: ds_add_u32 v1, v0586; GCN-NEXT: s_waitcnt lgkmcnt(0)587; GCN-NEXT: s_load_dword s0, s[0:1], 0x0588; GCN-NEXT: s_waitcnt lgkmcnt(0)589; GCN-NEXT: v_mov_b32_e32 v0, s0590; GCN-NEXT: global_store_dword v1, v0, s[2:3]591; GCN-NEXT: s_endpgm592entry:593 %unused = atomicrmw add ptr addrspace(3) @LDS, i32 5 monotonic594 %ld = load i32, ptr addrspace(1) %in, align 4595 store i32 %ld, ptr addrspace(1) %out, align 4596 ret void597}598 599define protected amdgpu_kernel void @no_alias_atomic_cmpxchg(ptr addrspace(1) %in, ptr addrspace(1) %out, i32 %swap) {600; CHECK-LABEL: @no_alias_atomic_cmpxchg(601; CHECK-NEXT: entry:602; CHECK-NEXT: [[UNUSED:%.*]] = cmpxchg ptr addrspace(3) @LDS, i32 7, i32 [[SWAP:%.*]] seq_cst monotonic, align 4603; CHECK-NEXT: fence syncscope("workgroup") release604; CHECK-NEXT: tail call void @llvm.amdgcn.s.barrier()605; CHECK-NEXT: fence syncscope("workgroup") acquire606; CHECK-NEXT: [[LD:%.*]] = load i32, ptr addrspace(1) [[IN:%.*]], align 4, !amdgpu.noclobber !0607; CHECK-NEXT: store i32 [[LD]], ptr addrspace(1) [[OUT:%.*]], align 4608; CHECK-NEXT: ret void609;610; GCN-LABEL: no_alias_atomic_cmpxchg:611; GCN: ; %bb.0: ; %entry612; GCN-NEXT: s_load_dword s6, s[4:5], 0x34613; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24614; GCN-NEXT: v_mov_b32_e32 v0, 7615; GCN-NEXT: v_mov_b32_e32 v1, 0616; GCN-NEXT: s_waitcnt lgkmcnt(0)617; GCN-NEXT: v_mov_b32_e32 v2, s6618; GCN-NEXT: ds_cmpst_b32 v1, v0, v2619; GCN-NEXT: s_waitcnt lgkmcnt(0)620; GCN-NEXT: s_barrier621; GCN-NEXT: s_load_dword s0, s[0:1], 0x0622; GCN-NEXT: s_waitcnt lgkmcnt(0)623; GCN-NEXT: v_mov_b32_e32 v0, s0624; GCN-NEXT: global_store_dword v1, v0, s[2:3]625; GCN-NEXT: s_endpgm626entry:627 %unused = cmpxchg ptr addrspace(3) @LDS, i32 7, i32 %swap seq_cst monotonic628 fence syncscope("workgroup") release629 tail call void @llvm.amdgcn.s.barrier()630 fence syncscope("workgroup") acquire631 %ld = load i32, ptr addrspace(1) %in, align 4632 store i32 %ld, ptr addrspace(1) %out, align 4633 ret void634}635 636define protected amdgpu_kernel void @no_alias_atomic_rmw(ptr addrspace(1) %in, ptr addrspace(1) %out) {637; CHECK-LABEL: @no_alias_atomic_rmw(638; CHECK-NEXT: entry:639; CHECK-NEXT: [[UNUSED:%.*]] = atomicrmw add ptr addrspace(3) @LDS, i32 5 seq_cst, align 4640; CHECK-NEXT: fence syncscope("workgroup") release641; CHECK-NEXT: tail call void @llvm.amdgcn.s.barrier()642; CHECK-NEXT: fence syncscope("workgroup") acquire643; CHECK-NEXT: [[LD:%.*]] = load i32, ptr addrspace(1) [[IN:%.*]], align 4, !amdgpu.noclobber !0644; CHECK-NEXT: store i32 [[LD]], ptr addrspace(1) [[OUT:%.*]], align 4645; CHECK-NEXT: ret void646;647; GCN-LABEL: no_alias_atomic_rmw:648; GCN: ; %bb.0: ; %entry649; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24650; GCN-NEXT: v_mov_b32_e32 v0, 5651; GCN-NEXT: v_mov_b32_e32 v1, 0652; GCN-NEXT: s_waitcnt lgkmcnt(0)653; GCN-NEXT: ds_add_u32 v1, v0654; GCN-NEXT: s_waitcnt lgkmcnt(0)655; GCN-NEXT: s_barrier656; GCN-NEXT: s_load_dword s0, s[0:1], 0x0657; GCN-NEXT: s_waitcnt lgkmcnt(0)658; GCN-NEXT: v_mov_b32_e32 v0, s0659; GCN-NEXT: global_store_dword v1, v0, s[2:3]660; GCN-NEXT: s_endpgm661entry:662 %unused = atomicrmw add ptr addrspace(3) @LDS, i32 5 seq_cst663 fence syncscope("workgroup") release664 tail call void @llvm.amdgcn.s.barrier()665 fence syncscope("workgroup") acquire666 %ld = load i32, ptr addrspace(1) %in, align 4667 store i32 %ld, ptr addrspace(1) %out, align 4668 ret void669}670 671define protected amdgpu_kernel void @may_alias_atomic_cmpxchg(ptr addrspace(1) %in, ptr addrspace(1) %out, i32 %swap) {672; CHECK-LABEL: @may_alias_atomic_cmpxchg(673; CHECK-NEXT: entry:674; CHECK-NEXT: [[UNUSED:%.*]] = cmpxchg ptr addrspace(1) [[OUT:%.*]], i32 7, i32 [[SWAP:%.*]] seq_cst monotonic, align 4675; CHECK-NEXT: fence syncscope("workgroup") release676; CHECK-NEXT: tail call void @llvm.amdgcn.s.barrier()677; CHECK-NEXT: fence syncscope("workgroup") acquire678; CHECK-NEXT: [[LD:%.*]] = load i32, ptr addrspace(1) [[IN:%.*]], align 4679; CHECK-NEXT: store i32 [[LD]], ptr addrspace(1) [[OUT]], align 4680; CHECK-NEXT: ret void681;682; GCN-LABEL: may_alias_atomic_cmpxchg:683; GCN: ; %bb.0: ; %entry684; GCN-NEXT: s_load_dword s6, s[4:5], 0x34685; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24686; GCN-NEXT: v_mov_b32_e32 v2, 0687; GCN-NEXT: v_mov_b32_e32 v1, 7688; GCN-NEXT: s_waitcnt lgkmcnt(0)689; GCN-NEXT: v_mov_b32_e32 v0, s6690; GCN-NEXT: global_atomic_cmpswap v2, v[0:1], s[2:3]691; GCN-NEXT: s_waitcnt vmcnt(0)692; GCN-NEXT: buffer_wbinvl1_vol693; GCN-NEXT: s_barrier694; GCN-NEXT: global_load_dword v0, v2, s[0:1]695; GCN-NEXT: s_waitcnt vmcnt(0)696; GCN-NEXT: global_store_dword v2, v0, s[2:3]697; GCN-NEXT: s_endpgm698entry:699 %unused = cmpxchg ptr addrspace(1) %out, i32 7, i32 %swap seq_cst monotonic700 fence syncscope("workgroup") release701 tail call void @llvm.amdgcn.s.barrier()702 fence syncscope("workgroup") acquire703 %ld = load i32, ptr addrspace(1) %in, align 4704 store i32 %ld, ptr addrspace(1) %out, align 4705 ret void706}707 708define protected amdgpu_kernel void @may_alias_atomic_rmw(ptr addrspace(1) %in, ptr addrspace(1) %out) {709; CHECK-LABEL: @may_alias_atomic_rmw(710; CHECK-NEXT: entry:711; CHECK-NEXT: [[UNUSED:%.*]] = atomicrmw add ptr addrspace(1) [[OUT:%.*]], i32 5 syncscope("agent") seq_cst, align 4712; CHECK-NEXT: fence syncscope("workgroup") release713; CHECK-NEXT: tail call void @llvm.amdgcn.s.barrier()714; CHECK-NEXT: fence syncscope("workgroup") acquire715; CHECK-NEXT: [[LD:%.*]] = load i32, ptr addrspace(1) [[IN:%.*]], align 4716; CHECK-NEXT: store i32 [[LD]], ptr addrspace(1) [[OUT]], align 4717; CHECK-NEXT: ret void718;719; GCN-LABEL: may_alias_atomic_rmw:720; GCN: ; %bb.0: ; %entry721; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24722; GCN-NEXT: v_mov_b32_e32 v0, 0723; GCN-NEXT: v_mov_b32_e32 v1, 5724; GCN-NEXT: s_waitcnt lgkmcnt(0)725; GCN-NEXT: global_atomic_add v0, v1, s[2:3]726; GCN-NEXT: s_waitcnt vmcnt(0)727; GCN-NEXT: buffer_wbinvl1_vol728; GCN-NEXT: s_barrier729; GCN-NEXT: global_load_dword v1, v0, s[0:1]730; GCN-NEXT: s_waitcnt vmcnt(0)731; GCN-NEXT: global_store_dword v0, v1, s[2:3]732; GCN-NEXT: s_endpgm733entry:734 %unused = atomicrmw add ptr addrspace(1) %out, i32 5 syncscope("agent") seq_cst735 fence syncscope("workgroup") release736 tail call void @llvm.amdgcn.s.barrier()737 fence syncscope("workgroup") acquire738 %ld = load i32, ptr addrspace(1) %in, align 4739 store i32 %ld, ptr addrspace(1) %out, align 4740 ret void741}742 743define protected amdgpu_kernel void @no_alias_atomic_rmw_then_clobber(ptr addrspace(1) %in, ptr addrspace(1) %out, ptr addrspace(1) noalias %noalias) {744; CHECK-LABEL: @no_alias_atomic_rmw_then_clobber(745; CHECK-NEXT: entry:746; CHECK-NEXT: store i32 1, ptr addrspace(1) [[OUT:%.*]], align 4747; CHECK-NEXT: store i32 2, ptr addrspace(1) [[NOALIAS:%.*]], align 4748; CHECK-NEXT: [[UNUSED:%.*]] = atomicrmw add ptr addrspace(3) @LDS, i32 5 seq_cst, align 4749; CHECK-NEXT: fence syncscope("workgroup") release750; CHECK-NEXT: tail call void @llvm.amdgcn.s.barrier()751; CHECK-NEXT: fence syncscope("workgroup") acquire752; CHECK-NEXT: [[LD:%.*]] = load i32, ptr addrspace(1) [[IN:%.*]], align 4753; CHECK-NEXT: store i32 [[LD]], ptr addrspace(1) [[OUT]], align 4754; CHECK-NEXT: ret void755;756; GCN-LABEL: no_alias_atomic_rmw_then_clobber:757; GCN: ; %bb.0: ; %entry758; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24759; GCN-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34760; GCN-NEXT: v_mov_b32_e32 v0, 1761; GCN-NEXT: v_mov_b32_e32 v1, 0762; GCN-NEXT: v_mov_b32_e32 v2, 2763; GCN-NEXT: s_waitcnt lgkmcnt(0)764; GCN-NEXT: global_store_dword v1, v0, s[2:3]765; GCN-NEXT: global_store_dword v1, v2, s[6:7]766; GCN-NEXT: v_mov_b32_e32 v0, 5767; GCN-NEXT: ds_add_u32 v1, v0768; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)769; GCN-NEXT: s_barrier770; GCN-NEXT: global_load_dword v0, v1, s[0:1]771; GCN-NEXT: s_waitcnt vmcnt(0)772; GCN-NEXT: global_store_dword v1, v0, s[2:3]773; GCN-NEXT: s_endpgm774entry:775 store i32 1, ptr addrspace(1) %out, align 4776 store i32 2, ptr addrspace(1) %noalias, align 4777 %unused = atomicrmw add ptr addrspace(3) @LDS, i32 5 seq_cst778 fence syncscope("workgroup") release779 tail call void @llvm.amdgcn.s.barrier()780 fence syncscope("workgroup") acquire781 %ld = load i32, ptr addrspace(1) %in, align 4782 store i32 %ld, ptr addrspace(1) %out, align 4783 ret void784}785 786define protected amdgpu_kernel void @no_alias_atomic_rmw_then_no_alias_store(ptr addrspace(1) %in, ptr addrspace(1) %out, ptr addrspace(1) noalias %noalias) {787; CHECK-LABEL: @no_alias_atomic_rmw_then_no_alias_store(788; CHECK-NEXT: entry:789; CHECK-NEXT: store i32 2, ptr addrspace(1) [[NOALIAS:%.*]], align 4790; CHECK-NEXT: [[UNUSED:%.*]] = atomicrmw add ptr addrspace(3) @LDS, i32 5 seq_cst, align 4791; CHECK-NEXT: fence syncscope("workgroup") release792; CHECK-NEXT: tail call void @llvm.amdgcn.s.barrier()793; CHECK-NEXT: fence syncscope("workgroup") acquire794; CHECK-NEXT: [[LD:%.*]] = load i32, ptr addrspace(1) [[IN:%.*]], align 4, !amdgpu.noclobber !0795; CHECK-NEXT: store i32 [[LD]], ptr addrspace(1) [[OUT:%.*]], align 4796; CHECK-NEXT: ret void797;798; GCN-LABEL: no_alias_atomic_rmw_then_no_alias_store:799; GCN: ; %bb.0: ; %entry800; GCN-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34801; GCN-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24802; GCN-NEXT: v_mov_b32_e32 v0, 2803; GCN-NEXT: v_mov_b32_e32 v1, 0804; GCN-NEXT: v_mov_b32_e32 v2, 5805; GCN-NEXT: s_waitcnt lgkmcnt(0)806; GCN-NEXT: global_store_dword v1, v0, s[6:7]807; GCN-NEXT: ds_add_u32 v1, v2808; GCN-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)809; GCN-NEXT: s_barrier810; GCN-NEXT: s_load_dword s0, s[0:1], 0x0811; GCN-NEXT: s_waitcnt lgkmcnt(0)812; GCN-NEXT: v_mov_b32_e32 v0, s0813; GCN-NEXT: global_store_dword v1, v0, s[2:3]814; GCN-NEXT: s_endpgm815entry:816 store i32 2, ptr addrspace(1) %noalias, align 4817 %unused = atomicrmw add ptr addrspace(3) @LDS, i32 5 seq_cst818 fence syncscope("workgroup") release819 tail call void @llvm.amdgcn.s.barrier()820 fence syncscope("workgroup") acquire821 %ld = load i32, ptr addrspace(1) %in, align 4822 store i32 %ld, ptr addrspace(1) %out, align 4823 ret void824}825 826declare void @llvm.amdgcn.s.barrier()827declare void @llvm.amdgcn.wave.barrier()828