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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 32; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -mattr="-wavefrontsize32,+wavefrontsize64" -o - < %s | FileCheck -check-prefixes=SDAG-W64 %s3; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -mattr="-wavefrontsize32,+wavefrontsize64" -o - < %s | FileCheck -check-prefixes=GISEL-W64 %s4; RUN: llc -global-isel=0 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -mattr="+wavefrontsize32,-wavefrontsize64" -o - < %s | FileCheck -check-prefixes=SDAG-W32 %s5; RUN: llc -global-isel=1 -mtriple=amdgcn-amd-amdpal -mcpu=gfx1100 -mattr="+wavefrontsize32,-wavefrontsize64" -o - < %s | FileCheck -check-prefixes=GISEL-W32 %s6 7; Use ballot for easy access to lanemask8 9define amdgpu_ps i64 @test_nor(i64 inreg %a, i64 inreg %b) {10; SDAG-W64-LABEL: test_nor:11; SDAG-W64: ; %bb.0:12; SDAG-W64-NEXT: s_nor_b64 s[0:1], s[0:1], s[2:3]13; SDAG-W64-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_1)14; SDAG-W64-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]15; SDAG-W64-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v016; SDAG-W64-NEXT: s_waitcnt_depctr depctr_va_sdst(0)17; SDAG-W64-NEXT: ; return to shader part epilog18;19; GISEL-W64-LABEL: test_nor:20; GISEL-W64: ; %bb.0:21; GISEL-W64-NEXT: s_nor_b64 s[0:1], s[0:1], s[2:3]22; GISEL-W64-NEXT: s_delay_alu instid0(SALU_CYCLE_1)23; GISEL-W64-NEXT: s_and_b64 s[0:1], s[0:1], exec24; GISEL-W64-NEXT: ; return to shader part epilog25;26; SDAG-W32-LABEL: test_nor:27; SDAG-W32: ; %bb.0:28; SDAG-W32-NEXT: s_nor_b32 s0, s0, s229; SDAG-W32-NEXT: s_mov_b32 s1, 030; SDAG-W32-NEXT: v_cndmask_b32_e64 v0, 0, 1, s031; SDAG-W32-NEXT: s_delay_alu instid0(VALU_DEP_1)32; SDAG-W32-NEXT: v_cmp_ne_u32_e64 s0, 0, v033; SDAG-W32-NEXT: ; return to shader part epilog34;35; GISEL-W32-LABEL: test_nor:36; GISEL-W32: ; %bb.0:37; GISEL-W32-NEXT: s_nor_b32 s0, s0, s238; GISEL-W32-NEXT: s_mov_b32 s1, 039; GISEL-W32-NEXT: s_and_b32 s0, s0, exec_lo40; GISEL-W32-NEXT: ; return to shader part epilog41 %a.lanemask = call i1 @llvm.amdgcn.inverse.ballot.i64(i64 %a)42 %b.lanemask = call i1 @llvm.amdgcn.inverse.ballot.i64(i64 %b)43 %or = or i1 %a.lanemask, %b.lanemask44 %xor = xor i1 %or, true45 %r = call i64 @llvm.amdgcn.ballot.i64(i1 %xor)46 ret i64 %r47}48 49define amdgpu_ps i64 @test_or_two_uses(i64 inreg %a, i64 inreg %b) {50; SDAG-W64-LABEL: test_or_two_uses:51; SDAG-W64: ; %bb.0:52; SDAG-W64-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]53; SDAG-W64-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_3) | instid1(VALU_DEP_2)54; SDAG-W64-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]55; SDAG-W64-NEXT: s_xor_b64 s[0:1], s[0:1], -156; SDAG-W64-NEXT: s_waitcnt_depctr depctr_sa_sdst(0)57; SDAG-W64-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[0:1]58; SDAG-W64-NEXT: v_cmp_ne_u32_e32 vcc, 0, v059; SDAG-W64-NEXT: s_delay_alu instid0(VALU_DEP_2)60; SDAG-W64-NEXT: v_cmp_ne_u32_e64 s[0:1], 0, v161; SDAG-W64-NEXT: s_waitcnt_depctr depctr_va_sdst(0)62; SDAG-W64-NEXT: s_and_b64 s[0:1], s[0:1], vcc63; SDAG-W64-NEXT: ; return to shader part epilog64;65; GISEL-W64-LABEL: test_or_two_uses:66; GISEL-W64: ; %bb.0:67; GISEL-W64-NEXT: s_or_b64 s[0:1], s[0:1], s[2:3]68; GISEL-W64-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_2) | instid1(SALU_CYCLE_1)69; GISEL-W64-NEXT: s_xor_b64 s[2:3], s[0:1], -170; GISEL-W64-NEXT: s_and_b64 s[0:1], s[0:1], exec71; GISEL-W64-NEXT: s_and_b64 s[2:3], s[2:3], exec72; GISEL-W64-NEXT: s_and_b64 s[0:1], s[2:3], s[0:1]73; GISEL-W64-NEXT: ; return to shader part epilog74;75; SDAG-W32-LABEL: test_or_two_uses:76; SDAG-W32: ; %bb.0:77; SDAG-W32-NEXT: s_or_b32 s0, s0, s278; SDAG-W32-NEXT: s_mov_b32 s3, 079; SDAG-W32-NEXT: v_cndmask_b32_e64 v0, 0, 1, s080; SDAG-W32-NEXT: s_xor_b32 s0, s0, -181; SDAG-W32-NEXT: s_mov_b32 s1, s382; SDAG-W32-NEXT: v_cndmask_b32_e64 v1, 0, 1, s083; SDAG-W32-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)84; SDAG-W32-NEXT: v_cmp_ne_u32_e64 s0, 0, v085; SDAG-W32-NEXT: v_cmp_ne_u32_e64 s2, 0, v186; SDAG-W32-NEXT: s_and_b64 s[0:1], s[2:3], s[0:1]87; SDAG-W32-NEXT: ; return to shader part epilog88;89; GISEL-W32-LABEL: test_or_two_uses:90; GISEL-W32: ; %bb.0:91; GISEL-W32-NEXT: s_or_b32 s0, s0, s292; GISEL-W32-NEXT: s_mov_b32 s1, 093; GISEL-W32-NEXT: s_xor_b32 s4, s0, -194; GISEL-W32-NEXT: s_and_b32 s2, s0, exec_lo95; GISEL-W32-NEXT: s_mov_b32 s3, s196; GISEL-W32-NEXT: s_and_b32 s0, s4, exec_lo97; GISEL-W32-NEXT: s_delay_alu instid0(SALU_CYCLE_1)98; GISEL-W32-NEXT: s_and_b64 s[0:1], s[0:1], s[2:3]99; GISEL-W32-NEXT: ; return to shader part epilog100 %a.lanemask = call i1 @llvm.amdgcn.inverse.ballot.i64(i64 %a)101 %b.lanemask = call i1 @llvm.amdgcn.inverse.ballot.i64(i64 %b)102 %or = or i1 %a.lanemask, %b.lanemask103 %xor = xor i1 %or, true104 %r0 = call i64 @llvm.amdgcn.ballot.i64(i1 %xor)105 %r1 = call i64 @llvm.amdgcn.ballot.i64(i1 %or)106 %r = and i64 %r0, %r1107 ret i64 %r108}109