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1; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -mattr=-xnack -enable-misched=0 < %s | FileCheck -check-prefix=GCN %s2 3; GCN-LABEL: {{^}}sample_contig_nsa:4; GCN-DAG: image_sample_c_l v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}],5; GCN-DAG: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}],6define amdgpu_ps <2 x float> @sample_contig_nsa(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s1, float %t1, float %r1, float %lod, float %r2, float %s2, float %t2) {7main_body:8 %zcompare.1 = fadd float %zcompare, 1.09 %s1.1 = fadd float %s1, 1.010 %t1.1 = fadd float %t1, 1.011 %r1.1 = fadd float %r1, 1.012 %s2.1 = fadd float %s2, 1.013 %t2.1 = fadd float %t2, 1.014 %r2.1 = fadd float %r2, 1.015 %lod.1 = fadd float %lod, 1.016 %v1 = call float @llvm.amdgcn.image.sample.c.l.3d.f32.f32(i32 1, float %zcompare.1, float %s1.1, float %t1.1, float %r1.1, float %lod.1, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)17 %v2 = call float @llvm.amdgcn.image.sample.3d.f32.f32(i32 1, float %s2.1, float %t2.1, float %r2.1, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)18 %r.0 = insertelement <2 x float> poison, float %v1, i32 019 %r = insertelement <2 x float> %r.0, float %v2, i32 120 ret <2 x float> %r21}22 23; GCN-LABEL: {{^}}sample_contig_nsa_10vgprs:24; GCN-DAG: image_sample_c_l v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}],25; GCN-DAG: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}],26define amdgpu_ps <2 x float> @sample_contig_nsa_10vgprs(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s1, float %t1, float %r1, float %lod, float %r2, float %s2, float %t2) #0 {27main_body:28 %zcompare.1 = fadd float %zcompare, 1.029 %s1.1 = fadd float %s1, 1.030 %t1.1 = fadd float %t1, 1.031 %r1.1 = fadd float %r1, 1.032 %s2.1 = fadd float %s2, 1.033 %t2.1 = fadd float %t2, 1.034 %r2.1 = fadd float %r2, 1.035 %lod.1 = fadd float %lod, 1.036 %v1 = call float @llvm.amdgcn.image.sample.c.l.3d.f32.f32(i32 1, float %zcompare.1, float %s1.1, float %t1.1, float %r1.1, float %lod.1, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)37 %v2 = call float @llvm.amdgcn.image.sample.3d.f32.f32(i32 1, float %s2.1, float %t2.1, float %r2.1, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)38 %r.0 = insertelement <2 x float> poison, float %v1, i32 039 %r = insertelement <2 x float> %r.0, float %v2, i32 140 ret <2 x float> %r41}42 43; GCN-LABEL: {{^}}sample_contig_nsa_conflict:44; GCN-DAG: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}],45; GCN-DAG: image_sample v{{[0-9]+}}, [{{v[0-9]+, v[0-9]+, v[0-9]+}}],46define amdgpu_ps <2 x float> @sample_contig_nsa_conflict(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s1, float %t1, float %r1, float %lod, float %r2, float %s2, float %t2) {47main_body:48 %zcompare.1 = fadd float %zcompare, 1.049 %s1.1 = fadd float %s1, 1.050 %t1.1 = fadd float %t1, 1.051 %r1.1 = fadd float %r1, 1.052 %s2.1 = fadd float %s2, 1.053 %t2.1 = fadd float %t2, 1.054 %r2.1 = fadd float %r2, 1.055 %lod.1 = fadd float %lod, 1.056 %v2 = call float @llvm.amdgcn.image.sample.3d.f32.f32(i32 1, float %s2.1, float %t2.1, float %r2.1, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)57 %v1 = call float @llvm.amdgcn.image.sample.3d.f32.f32(i32 1, float %t2.1, float %s2.1, float %r2.1, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)58 %r.0 = insertelement <2 x float> poison, float %v1, i32 059 %r = insertelement <2 x float> %r.0, float %v2, i32 160 ret <2 x float> %r61}62 63; GCN-LABEL: {{^}}sample_contig_nsa_same_addr:64; GCN-DAG: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}],65; GCN-DAG: image_sample v{{[0-9]+}}, v[{{[0-9]+:[0-9]+}}],66define amdgpu_ps <2 x float> @sample_contig_nsa_same_addr(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s1, float %t1, float %r1, float %lod, float %r2, float %s2, float %t2) {67main_body:68 %zcompare.1 = fadd float %zcompare, 1.069 %s1.1 = fadd float %s1, 1.070 %t1.1 = fadd float %t1, 1.071 %r1.1 = fadd float %r1, 1.072 %s2.1 = fadd float %s2, 1.073 %t2.1 = fadd float %t2, 1.074 %r2.1 = fadd float %r2, 1.075 %lod.1 = fadd float %lod, 1.076 %v2 = call float @llvm.amdgcn.image.sample.3d.f32.f32(i32 1, float %s2.1, float %t2.1, float %r2.1, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 1)77 %v1 = call float @llvm.amdgcn.image.sample.3d.f32.f32(i32 1, float %s2.1, float %t2.1, float %r2.1, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)78 %r.0 = insertelement <2 x float> poison, float %v1, i32 079 %r = insertelement <2 x float> %r.0, float %v2, i32 180 ret <2 x float> %r81}82 83; GCN-LABEL: {{^}}sample_contig_nsa_same_reg:84; GCN-DAG: image_sample v{{[0-9]+}}, [{{v[0-9]+, v[0-9]+, v[0-9]+}}],85define amdgpu_ps float @sample_contig_nsa_same_reg(<8 x i32> inreg %rsrc, <4 x i32> inreg %samp, float %zcompare, float %s1, float %t1, float %r1, float %lod, float %r2, float %s2, float %t2) {86main_body:87 %zcompare.1 = fadd float %zcompare, 1.088 %s1.1 = fadd float %s1, 1.089 %t1.1 = fadd float %t1, 1.090 %r1.1 = fadd float %r1, 1.091 %s2.1 = fadd float %s2, 1.092 %t2.1 = fadd float %t2, 1.093 %r2.1 = fadd float %r2, 1.094 %lod.1 = fadd float %lod, 1.095 %v = call float @llvm.amdgcn.image.sample.3d.f32.f32(i32 1, float %t2.1, float %t2.1, float %r2.1, <8 x i32> %rsrc, <4 x i32> %samp, i1 0, i32 0, i32 0)96 ret float %v97}98 99declare float @llvm.amdgcn.image.sample.3d.f32.f32(i32, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32)100declare float @llvm.amdgcn.image.sample.c.l.3d.f32.f32(i32, float, float, float, float, float, <8 x i32>, <4 x i32>, i1, i32, i32)101 102attributes #0 = {"amdgpu-num-vgpr"="10"}103