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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck --check-prefixes=SI %s3; RUN: llc -mtriple=amdgcn -mcpu=fiji < %s | FileCheck --check-prefixes=VI %s4; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck --check-prefixes=GFX11PLUS,GFX11,GFX11-TRUE16 %s5; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck --check-prefixes=GFX11PLUS,GFX11,GFX11-FAKE16 %s6; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=+real-true16 < %s | FileCheck --check-prefixes=GFX11PLUS,GFX12,GFX12-TRUE16 %s7; RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -mattr=-real-true16 < %s | FileCheck --check-prefixes=GFX11PLUS,GFX12,GFX12-FAKE16 %s8 9; IEEE bit enabled for compute kernel, so shouldn't use.10define amdgpu_kernel void @v_omod_div2_f32_enable_ieee_signed_zeros(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #4 {11; SI-LABEL: v_omod_div2_f32_enable_ieee_signed_zeros:12; SI: ; %bb.0:13; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x914; SI-NEXT: s_mov_b32 s7, 0xf00015; SI-NEXT: s_mov_b32 s6, 016; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v017; SI-NEXT: v_mov_b32_e32 v1, 018; SI-NEXT: s_waitcnt lgkmcnt(0)19; SI-NEXT: s_mov_b64 s[4:5], s[2:3]20; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr6421; SI-NEXT: s_mov_b64 s[2:3], s[6:7]22; SI-NEXT: s_waitcnt vmcnt(0)23; SI-NEXT: v_add_f32_e32 v2, 1.0, v224; SI-NEXT: v_mul_f32_e32 v2, 0.5, v225; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr6426; SI-NEXT: s_endpgm27;28; VI-LABEL: v_omod_div2_f32_enable_ieee_signed_zeros:29; VI: ; %bb.0:30; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2431; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v032; VI-NEXT: s_waitcnt lgkmcnt(0)33; VI-NEXT: v_mov_b32_e32 v1, s334; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v235; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc36; VI-NEXT: flat_load_dword v3, v[0:1]37; VI-NEXT: v_mov_b32_e32 v1, s138; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v239; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc40; VI-NEXT: s_waitcnt vmcnt(0)41; VI-NEXT: v_add_f32_e32 v2, 1.0, v342; VI-NEXT: v_mul_f32_e32 v2, 0.5, v243; VI-NEXT: flat_store_dword v[0:1], v244; VI-NEXT: s_endpgm45;46; GFX11-LABEL: v_omod_div2_f32_enable_ieee_signed_zeros:47; GFX11: ; %bb.0:48; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x2449; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v050; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)51; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v052; GFX11-NEXT: s_waitcnt lgkmcnt(0)53; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]54; GFX11-NEXT: s_waitcnt vmcnt(0)55; GFX11-NEXT: v_add_f32_e32 v1, 1.0, v156; GFX11-NEXT: v_mul_f32_e32 v1, 0.5, v157; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]58; GFX11-NEXT: s_endpgm59;60; GFX12-LABEL: v_omod_div2_f32_enable_ieee_signed_zeros:61; GFX12: ; %bb.0:62; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x2463; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v064; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)65; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v066; GFX12-NEXT: s_wait_kmcnt 0x067; GFX12-NEXT: global_load_b32 v1, v0, s[2:3]68; GFX12-NEXT: s_wait_loadcnt 0x069; GFX12-NEXT: v_add_f32_e32 v1, 1.0, v170; GFX12-NEXT: v_mul_f32_e32 v1, 0.5, v171; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]72; GFX12-NEXT: s_endpgm73 %tid = call i32 @llvm.amdgcn.workitem.id.x()74 %gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid75 %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid76 %a = load float, ptr addrspace(1) %gep077 %add = fadd float %a, 1.078 %div2 = fmul float %add, 0.579 store float %div2, ptr addrspace(1) %out.gep80 ret void81}82 83; IEEE bit enabled for compute kernel, so shouldn't use.84define amdgpu_kernel void @v_omod_div2_f64_enable_ieee_signed_zeros(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #4 {85; SI-LABEL: v_omod_div2_f64_enable_ieee_signed_zeros:86; SI: ; %bb.0:87; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x988; SI-NEXT: s_mov_b32 s7, 0xf00089; SI-NEXT: s_mov_b32 s6, 090; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v091; SI-NEXT: v_mov_b32_e32 v1, 092; SI-NEXT: s_waitcnt lgkmcnt(0)93; SI-NEXT: s_mov_b64 s[4:5], s[2:3]94; SI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr6495; SI-NEXT: s_mov_b64 s[2:3], s[6:7]96; SI-NEXT: s_waitcnt vmcnt(0)97; SI-NEXT: v_add_f64 v[2:3], v[2:3], 1.098; SI-NEXT: v_mul_f64 v[2:3], v[2:3], 0.599; SI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64100; SI-NEXT: s_endpgm101;102; VI-LABEL: v_omod_div2_f64_enable_ieee_signed_zeros:103; VI: ; %bb.0:104; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24105; VI-NEXT: v_lshlrev_b32_e32 v2, 3, v0106; VI-NEXT: s_waitcnt lgkmcnt(0)107; VI-NEXT: v_mov_b32_e32 v1, s3108; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2109; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc110; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]111; VI-NEXT: v_mov_b32_e32 v3, s1112; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2113; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc114; VI-NEXT: s_waitcnt vmcnt(0)115; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0116; VI-NEXT: v_mul_f64 v[0:1], v[0:1], 0.5117; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]118; VI-NEXT: s_endpgm119;120; GFX11-LABEL: v_omod_div2_f64_enable_ieee_signed_zeros:121; GFX11: ; %bb.0:122; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24123; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0124; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)125; GFX11-NEXT: v_lshlrev_b32_e32 v2, 3, v0126; GFX11-NEXT: s_waitcnt lgkmcnt(0)127; GFX11-NEXT: global_load_b64 v[0:1], v2, s[2:3]128; GFX11-NEXT: s_waitcnt vmcnt(0)129; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0130; GFX11-NEXT: v_mul_f64 v[0:1], v[0:1], 0.5131; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]132; GFX11-NEXT: s_endpgm133;134; GFX12-LABEL: v_omod_div2_f64_enable_ieee_signed_zeros:135; GFX12: ; %bb.0:136; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24137; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0138; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)139; GFX12-NEXT: v_lshlrev_b32_e32 v2, 3, v0140; GFX12-NEXT: s_wait_kmcnt 0x0141; GFX12-NEXT: global_load_b64 v[0:1], v2, s[2:3]142; GFX12-NEXT: s_wait_loadcnt 0x0143; GFX12-NEXT: v_add_f64_e32 v[0:1], 1.0, v[0:1]144; GFX12-NEXT: v_mul_f64_e32 v[0:1], 0.5, v[0:1]145; GFX12-NEXT: global_store_b64 v2, v[0:1], s[0:1]146; GFX12-NEXT: s_endpgm147 %tid = call i32 @llvm.amdgcn.workitem.id.x()148 %gep0 = getelementptr double, ptr addrspace(1) %aptr, i32 %tid149 %out.gep = getelementptr double, ptr addrspace(1) %out, i32 %tid150 %a = load double, ptr addrspace(1) %gep0151 %add = fadd double %a, 1.0152 %div2 = fmul double %add, 0.5153 store double %div2, ptr addrspace(1) %out.gep154 ret void155}156 157; IEEE bit enabled for compute kernel, so shouldn't use even though nsz is allowed158define amdgpu_kernel void @v_omod_div2_f32_enable_ieee_nsz(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #0 {159; SI-LABEL: v_omod_div2_f32_enable_ieee_nsz:160; SI: ; %bb.0:161; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9162; SI-NEXT: s_mov_b32 s7, 0xf000163; SI-NEXT: s_mov_b32 s6, 0164; SI-NEXT: v_lshlrev_b32_e32 v0, 2, v0165; SI-NEXT: v_mov_b32_e32 v1, 0166; SI-NEXT: s_waitcnt lgkmcnt(0)167; SI-NEXT: s_mov_b64 s[4:5], s[2:3]168; SI-NEXT: buffer_load_dword v2, v[0:1], s[4:7], 0 addr64169; SI-NEXT: s_mov_b64 s[2:3], s[6:7]170; SI-NEXT: s_waitcnt vmcnt(0)171; SI-NEXT: v_add_f32_e32 v2, 1.0, v2172; SI-NEXT: v_mul_f32_e32 v2, 0.5, v2173; SI-NEXT: buffer_store_dword v2, v[0:1], s[0:3], 0 addr64174; SI-NEXT: s_endpgm175;176; VI-LABEL: v_omod_div2_f32_enable_ieee_nsz:177; VI: ; %bb.0:178; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24179; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0180; VI-NEXT: s_waitcnt lgkmcnt(0)181; VI-NEXT: v_mov_b32_e32 v1, s3182; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2183; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc184; VI-NEXT: flat_load_dword v3, v[0:1]185; VI-NEXT: v_mov_b32_e32 v1, s1186; VI-NEXT: v_add_u32_e32 v0, vcc, s0, v2187; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc188; VI-NEXT: s_waitcnt vmcnt(0)189; VI-NEXT: v_add_f32_e32 v2, 1.0, v3190; VI-NEXT: v_mul_f32_e32 v2, 0.5, v2191; VI-NEXT: flat_store_dword v[0:1], v2192; VI-NEXT: s_endpgm193;194; GFX11-LABEL: v_omod_div2_f32_enable_ieee_nsz:195; GFX11: ; %bb.0:196; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24197; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0198; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)199; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0200; GFX11-NEXT: s_waitcnt lgkmcnt(0)201; GFX11-NEXT: global_load_b32 v1, v0, s[2:3]202; GFX11-NEXT: s_waitcnt vmcnt(0)203; GFX11-NEXT: v_add_f32_e32 v1, 1.0, v1204; GFX11-NEXT: v_mul_f32_e32 v1, 0.5, v1205; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]206; GFX11-NEXT: s_endpgm207;208; GFX12-LABEL: v_omod_div2_f32_enable_ieee_nsz:209; GFX12: ; %bb.0:210; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24211; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0212; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)213; GFX12-NEXT: v_lshlrev_b32_e32 v0, 2, v0214; GFX12-NEXT: s_wait_kmcnt 0x0215; GFX12-NEXT: global_load_b32 v1, v0, s[2:3]216; GFX12-NEXT: s_wait_loadcnt 0x0217; GFX12-NEXT: v_add_f32_e32 v1, 1.0, v1218; GFX12-NEXT: v_mul_f32_e32 v1, 0.5, v1219; GFX12-NEXT: global_store_b32 v0, v1, s[0:1]220; GFX12-NEXT: s_endpgm221 %tid = call i32 @llvm.amdgcn.workitem.id.x()222 %gep0 = getelementptr float, ptr addrspace(1) %aptr, i32 %tid223 %out.gep = getelementptr float, ptr addrspace(1) %out, i32 %tid224 %a = load float, ptr addrspace(1) %gep0225 %add = fadd float %a, 1.0226 %div2 = fmul float %add, 0.5227 store float %div2, ptr addrspace(1) %out.gep228 ret void229}230 231; IEEE bit enabled for compute kernel, so shouldn't use even though nsz is allowed.232define amdgpu_kernel void @v_omod_div2_f64_enable_ieee_nsz(ptr addrspace(1) %out, ptr addrspace(1) %aptr) #5 {233; SI-LABEL: v_omod_div2_f64_enable_ieee_nsz:234; SI: ; %bb.0:235; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9236; SI-NEXT: s_mov_b32 s7, 0xf000237; SI-NEXT: s_mov_b32 s6, 0238; SI-NEXT: v_lshlrev_b32_e32 v0, 3, v0239; SI-NEXT: v_mov_b32_e32 v1, 0240; SI-NEXT: s_waitcnt lgkmcnt(0)241; SI-NEXT: s_mov_b64 s[4:5], s[2:3]242; SI-NEXT: buffer_load_dwordx2 v[2:3], v[0:1], s[4:7], 0 addr64243; SI-NEXT: s_mov_b64 s[2:3], s[6:7]244; SI-NEXT: s_waitcnt vmcnt(0)245; SI-NEXT: v_add_f64 v[2:3], v[2:3], 1.0246; SI-NEXT: v_mul_f64 v[2:3], v[2:3], 0.5247; SI-NEXT: buffer_store_dwordx2 v[2:3], v[0:1], s[0:3], 0 addr64248; SI-NEXT: s_endpgm249;250; VI-LABEL: v_omod_div2_f64_enable_ieee_nsz:251; VI: ; %bb.0:252; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24253; VI-NEXT: v_lshlrev_b32_e32 v2, 3, v0254; VI-NEXT: s_waitcnt lgkmcnt(0)255; VI-NEXT: v_mov_b32_e32 v1, s3256; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v2257; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc258; VI-NEXT: flat_load_dwordx2 v[0:1], v[0:1]259; VI-NEXT: v_mov_b32_e32 v3, s1260; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2261; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc262; VI-NEXT: s_waitcnt vmcnt(0)263; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0264; VI-NEXT: v_mul_f64 v[0:1], v[0:1], 0.5265; VI-NEXT: flat_store_dwordx2 v[2:3], v[0:1]266; VI-NEXT: s_endpgm267;268; GFX11-LABEL: v_omod_div2_f64_enable_ieee_nsz:269; GFX11: ; %bb.0:270; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24271; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0272; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)273; GFX11-NEXT: v_lshlrev_b32_e32 v2, 3, v0274; GFX11-NEXT: s_waitcnt lgkmcnt(0)275; GFX11-NEXT: global_load_b64 v[0:1], v2, s[2:3]276; GFX11-NEXT: s_waitcnt vmcnt(0)277; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0278; GFX11-NEXT: v_mul_f64 v[0:1], v[0:1], 0.5279; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]280; GFX11-NEXT: s_endpgm281;282; GFX12-LABEL: v_omod_div2_f64_enable_ieee_nsz:283; GFX12: ; %bb.0:284; GFX12-NEXT: s_load_b128 s[0:3], s[4:5], 0x24285; GFX12-NEXT: v_and_b32_e32 v0, 0x3ff, v0286; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_4) | instid1(VALU_DEP_1)287; GFX12-NEXT: v_lshlrev_b32_e32 v2, 3, v0288; GFX12-NEXT: s_wait_kmcnt 0x0289; GFX12-NEXT: global_load_b64 v[0:1], v2, s[2:3]290; GFX12-NEXT: s_wait_loadcnt 0x0291; GFX12-NEXT: v_add_f64_e32 v[0:1], 1.0, v[0:1]292; GFX12-NEXT: v_mul_f64_e32 v[0:1], 0.5, v[0:1]293; GFX12-NEXT: global_store_b64 v2, v[0:1], s[0:1]294; GFX12-NEXT: s_endpgm295 %tid = call i32 @llvm.amdgcn.workitem.id.x()296 %gep0 = getelementptr double, ptr addrspace(1) %aptr, i32 %tid297 %out.gep = getelementptr double, ptr addrspace(1) %out, i32 %tid298 %a = load double, ptr addrspace(1) %gep0299 %add = fadd double %a, 1.0300 %div2 = fmul double %add, 0.5301 store double %div2, ptr addrspace(1) %out.gep302 ret void303}304 305; Only allow without IEEE bit if signed zeros are significant.306define amdgpu_ps void @v_omod_div2_f32_signed_zeros(float %a) #4 {307; SI-LABEL: v_omod_div2_f32_signed_zeros:308; SI: ; %bb.0:309; SI-NEXT: v_add_f32_e32 v0, 1.0, v0310; SI-NEXT: v_mul_f32_e32 v0, 0.5, v0311; SI-NEXT: s_mov_b32 s3, 0xf000312; SI-NEXT: s_mov_b32 s2, -1313; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0314; SI-NEXT: s_endpgm315;316; VI-LABEL: v_omod_div2_f32_signed_zeros:317; VI: ; %bb.0:318; VI-NEXT: v_add_f32_e32 v0, 1.0, v0319; VI-NEXT: v_mul_f32_e32 v0, 0.5, v0320; VI-NEXT: flat_store_dword v[0:1], v0321; VI-NEXT: s_endpgm322;323; GFX11PLUS-LABEL: v_omod_div2_f32_signed_zeros:324; GFX11PLUS: ; %bb.0:325; GFX11PLUS-NEXT: v_add_f32_e32 v0, 1.0, v0326; GFX11PLUS-NEXT: s_delay_alu instid0(VALU_DEP_1)327; GFX11PLUS-NEXT: v_mul_f32_e32 v0, 0.5, v0328; GFX11PLUS-NEXT: global_store_b32 v[0:1], v0, off329; GFX11PLUS-NEXT: s_endpgm330 %add = fadd float %a, 1.0331 %div2 = fmul float %add, 0.5332 store float %div2, ptr addrspace(1) poison333 ret void334}335 336; Only allow without IEEE bit if signed zeros are significant.337define amdgpu_ps void @v_omod_div2_f64_signed_zeros(double %a) #4 {338; SI-LABEL: v_omod_div2_f64_signed_zeros:339; SI: ; %bb.0:340; SI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0341; SI-NEXT: s_mov_b32 s3, 0xf000342; SI-NEXT: v_mul_f64 v[0:1], v[0:1], 0.5343; SI-NEXT: s_mov_b32 s2, -1344; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0345; SI-NEXT: s_endpgm346;347; VI-LABEL: v_omod_div2_f64_signed_zeros:348; VI: ; %bb.0:349; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0350; VI-NEXT: v_mul_f64 v[0:1], v[0:1], 0.5351; VI-NEXT: flat_store_dwordx2 v[0:1], v[0:1]352; VI-NEXT: s_endpgm353;354; GFX11-LABEL: v_omod_div2_f64_signed_zeros:355; GFX11: ; %bb.0:356; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0357; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)358; GFX11-NEXT: v_mul_f64 v[0:1], v[0:1], 0.5359; GFX11-NEXT: global_store_b64 v[0:1], v[0:1], off360; GFX11-NEXT: s_endpgm361;362; GFX12-LABEL: v_omod_div2_f64_signed_zeros:363; GFX12: ; %bb.0:364; GFX12-NEXT: v_add_f64_e32 v[0:1], 1.0, v[0:1]365; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)366; GFX12-NEXT: v_mul_f64_e32 v[0:1], 0.5, v[0:1]367; GFX12-NEXT: global_store_b64 v[0:1], v[0:1], off368; GFX12-NEXT: s_endpgm369 %add = fadd double %a, 1.0370 %div2 = fmul double %add, 0.5371 store double %div2, ptr addrspace(1) poison372 ret void373}374 375define amdgpu_ps void @v_omod_div2_f32(float %a) #0 {376; SI-LABEL: v_omod_div2_f32:377; SI: ; %bb.0:378; SI-NEXT: v_add_f32_e64 v0, v0, 1.0 div:2379; SI-NEXT: s_mov_b32 s3, 0xf000380; SI-NEXT: s_mov_b32 s2, -1381; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0382; SI-NEXT: s_endpgm383;384; VI-LABEL: v_omod_div2_f32:385; VI: ; %bb.0:386; VI-NEXT: v_add_f32_e64 v0, v0, 1.0 div:2387; VI-NEXT: flat_store_dword v[0:1], v0388; VI-NEXT: s_endpgm389;390; GFX11PLUS-LABEL: v_omod_div2_f32:391; GFX11PLUS: ; %bb.0:392; GFX11PLUS-NEXT: v_add_f32_e64 v0, v0, 1.0 div:2393; GFX11PLUS-NEXT: global_store_b32 v[0:1], v0, off394; GFX11PLUS-NEXT: s_endpgm395 %add = fadd float %a, 1.0396 %div2 = fmul float %add, 0.5397 store float %div2, ptr addrspace(1) poison398 ret void399}400 401define amdgpu_ps void @v_omod_div2_f64(double %a) #5 {402; SI-LABEL: v_omod_div2_f64:403; SI: ; %bb.0:404; SI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 div:2405; SI-NEXT: s_mov_b32 s3, 0xf000406; SI-NEXT: s_mov_b32 s2, -1407; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0408; SI-NEXT: s_endpgm409;410; VI-LABEL: v_omod_div2_f64:411; VI: ; %bb.0:412; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 div:2413; VI-NEXT: flat_store_dwordx2 v[0:1], v[0:1]414; VI-NEXT: s_endpgm415;416; GFX11-LABEL: v_omod_div2_f64:417; GFX11: ; %bb.0:418; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 div:2419; GFX11-NEXT: global_store_b64 v[0:1], v[0:1], off420; GFX11-NEXT: s_endpgm421;422; GFX12-LABEL: v_omod_div2_f64:423; GFX12: ; %bb.0:424; GFX12-NEXT: v_add_f64_e64 v[0:1], v[0:1], 1.0 div:2425; GFX12-NEXT: global_store_b64 v[0:1], v[0:1], off426; GFX12-NEXT: s_endpgm427 %add = fadd nsz double %a, 1.0428 %div2 = fmul nsz double %add, 0.5429 store double %div2, ptr addrspace(1) poison430 ret void431}432 433define amdgpu_ps void @v_omod_mul2_f32(float %a) #0 {434; SI-LABEL: v_omod_mul2_f32:435; SI: ; %bb.0:436; SI-NEXT: v_add_f32_e64 v0, v0, 1.0 mul:2437; SI-NEXT: s_mov_b32 s3, 0xf000438; SI-NEXT: s_mov_b32 s2, -1439; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0440; SI-NEXT: s_endpgm441;442; VI-LABEL: v_omod_mul2_f32:443; VI: ; %bb.0:444; VI-NEXT: v_add_f32_e64 v0, v0, 1.0 mul:2445; VI-NEXT: flat_store_dword v[0:1], v0446; VI-NEXT: s_endpgm447;448; GFX11PLUS-LABEL: v_omod_mul2_f32:449; GFX11PLUS: ; %bb.0:450; GFX11PLUS-NEXT: v_add_f32_e64 v0, v0, 1.0 mul:2451; GFX11PLUS-NEXT: global_store_b32 v[0:1], v0, off452; GFX11PLUS-NEXT: s_endpgm453 %add = fadd float %a, 1.0454 %div2 = fmul float %add, 2.0455 store float %div2, ptr addrspace(1) poison456 ret void457}458 459define amdgpu_ps void @v_omod_mul2_med3(float %x, float %y, float %z) #0 {460; SI-LABEL: v_omod_mul2_med3:461; SI: ; %bb.0:462; SI-NEXT: v_med3_f32 v0, v0, v1, v2 mul:2463; SI-NEXT: s_mov_b32 s3, 0xf000464; SI-NEXT: s_mov_b32 s2, -1465; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0466; SI-NEXT: s_endpgm467;468; VI-LABEL: v_omod_mul2_med3:469; VI: ; %bb.0:470; VI-NEXT: v_med3_f32 v0, v0, v1, v2 mul:2471; VI-NEXT: flat_store_dword v[0:1], v0472; VI-NEXT: s_endpgm473;474; GFX11-LABEL: v_omod_mul2_med3:475; GFX11: ; %bb.0:476; GFX11-NEXT: v_med3_f32 v0, v0, v1, v2 mul:2477; GFX11-NEXT: global_store_b32 v[0:1], v0, off478; GFX11-NEXT: s_endpgm479;480; GFX12-LABEL: v_omod_mul2_med3:481; GFX12: ; %bb.0:482; GFX12-NEXT: v_med3_num_f32 v0, v0, v1, v2 mul:2483; GFX12-NEXT: global_store_b32 v[0:1], v0, off484; GFX12-NEXT: s_endpgm485 %fmed3 = call float @llvm.amdgcn.fmed3.f32(float %x, float %y, float %z)486 %div2 = fmul float %fmed3, 2.0487 store float %div2, ptr addrspace(1) poison488 ret void489}490 491define amdgpu_ps void @v_omod_mul2_f64(double %a) #5 {492; SI-LABEL: v_omod_mul2_f64:493; SI: ; %bb.0:494; SI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 mul:2495; SI-NEXT: s_mov_b32 s3, 0xf000496; SI-NEXT: s_mov_b32 s2, -1497; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0498; SI-NEXT: s_endpgm499;500; VI-LABEL: v_omod_mul2_f64:501; VI: ; %bb.0:502; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 mul:2503; VI-NEXT: flat_store_dwordx2 v[0:1], v[0:1]504; VI-NEXT: s_endpgm505;506; GFX11-LABEL: v_omod_mul2_f64:507; GFX11: ; %bb.0:508; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 mul:2509; GFX11-NEXT: global_store_b64 v[0:1], v[0:1], off510; GFX11-NEXT: s_endpgm511;512; GFX12-LABEL: v_omod_mul2_f64:513; GFX12: ; %bb.0:514; GFX12-NEXT: v_add_f64_e64 v[0:1], v[0:1], 1.0 mul:2515; GFX12-NEXT: global_store_b64 v[0:1], v[0:1], off516; GFX12-NEXT: s_endpgm517 %add = fadd nsz double %a, 1.0518 %div2 = fmul nsz double %add, 2.0519 store double %div2, ptr addrspace(1) poison520 ret void521}522 523define amdgpu_ps void @v_omod_mul4_f32(float %a) #0 {524; SI-LABEL: v_omod_mul4_f32:525; SI: ; %bb.0:526; SI-NEXT: v_add_f32_e64 v0, v0, 1.0 mul:4527; SI-NEXT: s_mov_b32 s3, 0xf000528; SI-NEXT: s_mov_b32 s2, -1529; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0530; SI-NEXT: s_endpgm531;532; VI-LABEL: v_omod_mul4_f32:533; VI: ; %bb.0:534; VI-NEXT: v_add_f32_e64 v0, v0, 1.0 mul:4535; VI-NEXT: flat_store_dword v[0:1], v0536; VI-NEXT: s_endpgm537;538; GFX11PLUS-LABEL: v_omod_mul4_f32:539; GFX11PLUS: ; %bb.0:540; GFX11PLUS-NEXT: v_add_f32_e64 v0, v0, 1.0 mul:4541; GFX11PLUS-NEXT: global_store_b32 v[0:1], v0, off542; GFX11PLUS-NEXT: s_endpgm543 %add = fadd float %a, 1.0544 %div2 = fmul float %add, 4.0545 store float %div2, ptr addrspace(1) poison546 ret void547}548 549define amdgpu_ps void @v_omod_mul4_f64(double %a) #5 {550; SI-LABEL: v_omod_mul4_f64:551; SI: ; %bb.0:552; SI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 mul:4553; SI-NEXT: s_mov_b32 s3, 0xf000554; SI-NEXT: s_mov_b32 s2, -1555; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0556; SI-NEXT: s_endpgm557;558; VI-LABEL: v_omod_mul4_f64:559; VI: ; %bb.0:560; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 mul:4561; VI-NEXT: flat_store_dwordx2 v[0:1], v[0:1]562; VI-NEXT: s_endpgm563;564; GFX11-LABEL: v_omod_mul4_f64:565; GFX11: ; %bb.0:566; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0 mul:4567; GFX11-NEXT: global_store_b64 v[0:1], v[0:1], off568; GFX11-NEXT: s_endpgm569;570; GFX12-LABEL: v_omod_mul4_f64:571; GFX12: ; %bb.0:572; GFX12-NEXT: v_add_f64_e64 v[0:1], v[0:1], 1.0 mul:4573; GFX12-NEXT: global_store_b64 v[0:1], v[0:1], off574; GFX12-NEXT: s_endpgm575 %add = fadd nsz double %a, 1.0576 %div2 = fmul nsz double %add, 4.0577 store double %div2, ptr addrspace(1) poison578 ret void579}580 581define amdgpu_ps void @v_omod_mul4_multi_use_f32(float %a) #0 {582; SI-LABEL: v_omod_mul4_multi_use_f32:583; SI: ; %bb.0:584; SI-NEXT: v_add_f32_e32 v0, 1.0, v0585; SI-NEXT: v_mul_f32_e32 v1, 4.0, v0586; SI-NEXT: s_mov_b32 s3, 0xf000587; SI-NEXT: s_mov_b32 s2, -1588; SI-NEXT: buffer_store_dword v1, off, s[0:3], 0589; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0590; SI-NEXT: s_waitcnt vmcnt(0)591; SI-NEXT: s_endpgm592;593; VI-LABEL: v_omod_mul4_multi_use_f32:594; VI: ; %bb.0:595; VI-NEXT: v_add_f32_e32 v0, 1.0, v0596; VI-NEXT: v_mul_f32_e32 v1, 4.0, v0597; VI-NEXT: flat_store_dword v[0:1], v1598; VI-NEXT: flat_store_dword v[0:1], v0599; VI-NEXT: s_waitcnt vmcnt(0)600; VI-NEXT: s_endpgm601;602; GFX11-LABEL: v_omod_mul4_multi_use_f32:603; GFX11: ; %bb.0:604; GFX11-NEXT: v_add_f32_e32 v0, 1.0, v0605; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)606; GFX11-NEXT: v_mul_f32_e32 v1, 4.0, v0607; GFX11-NEXT: s_clause 0x1608; GFX11-NEXT: global_store_b32 v[0:1], v1, off609; GFX11-NEXT: global_store_b32 v[0:1], v0, off dlc610; GFX11-NEXT: s_waitcnt_vscnt null, 0x0611; GFX11-NEXT: s_endpgm612;613; GFX12-LABEL: v_omod_mul4_multi_use_f32:614; GFX12: ; %bb.0:615; GFX12-NEXT: v_add_f32_e32 v0, 1.0, v0616; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)617; GFX12-NEXT: v_mul_f32_e32 v1, 4.0, v0618; GFX12-NEXT: global_store_b32 v[0:1], v1, off619; GFX12-NEXT: s_wait_storecnt 0x0620; GFX12-NEXT: global_store_b32 v[0:1], v0, off scope:SCOPE_SYS621; GFX12-NEXT: s_wait_storecnt 0x0622; GFX12-NEXT: s_endpgm623 %add = fadd float %a, 1.0624 %div2 = fmul float %add, 4.0625 store float %div2, ptr addrspace(1) poison626 store volatile float %add, ptr addrspace(1) poison627 ret void628}629 630define amdgpu_ps void @v_omod_mul4_dbg_use_f32(float %a) #0 {631; SI-LABEL: v_omod_mul4_dbg_use_f32:632; SI: ; %bb.0:633; SI-NEXT: v_add_f32_e64 v0, v0, 1.0 mul:4634; SI-NEXT: s_mov_b32 s3, 0xf000635; SI-NEXT: s_mov_b32 s2, -1636; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0637; SI-NEXT: s_endpgm638;639; VI-LABEL: v_omod_mul4_dbg_use_f32:640; VI: ; %bb.0:641; VI-NEXT: v_add_f32_e64 v0, v0, 1.0 mul:4642; VI-NEXT: flat_store_dword v[0:1], v0643; VI-NEXT: s_endpgm644;645; GFX11PLUS-LABEL: v_omod_mul4_dbg_use_f32:646; GFX11PLUS: ; %bb.0:647; GFX11PLUS-NEXT: v_add_f32_e64 v0, v0, 1.0 mul:4648; GFX11PLUS-NEXT: global_store_b32 v[0:1], v0, off649; GFX11PLUS-NEXT: s_endpgm650 %add = fadd float %a, 1.0651 call void @llvm.dbg.value(metadata float %add, i64 0, metadata !4, metadata !9), !dbg !10652 %div2 = fmul float %add, 4.0653 store float %div2, ptr addrspace(1) poison654 ret void655}656 657; Clamp is applied after omod, folding both into instruction is OK.658define amdgpu_ps void @v_clamp_omod_div2_f32(float %a) #0 {659; SI-LABEL: v_clamp_omod_div2_f32:660; SI: ; %bb.0:661; SI-NEXT: v_add_f32_e64 v0, v0, 1.0 clamp div:2662; SI-NEXT: s_mov_b32 s3, 0xf000663; SI-NEXT: s_mov_b32 s2, -1664; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0665; SI-NEXT: s_endpgm666;667; VI-LABEL: v_clamp_omod_div2_f32:668; VI: ; %bb.0:669; VI-NEXT: v_add_f32_e64 v0, v0, 1.0 clamp div:2670; VI-NEXT: flat_store_dword v[0:1], v0671; VI-NEXT: s_endpgm672;673; GFX11PLUS-LABEL: v_clamp_omod_div2_f32:674; GFX11PLUS: ; %bb.0:675; GFX11PLUS-NEXT: v_add_f32_e64 v0, v0, 1.0 clamp div:2676; GFX11PLUS-NEXT: global_store_b32 v[0:1], v0, off677; GFX11PLUS-NEXT: s_endpgm678 %add = fadd float %a, 1.0679 %div2 = fmul float %add, 0.5680 681 %max = call float @llvm.maxnum.f32(float %div2, float 0.0)682 %clamp = call float @llvm.minnum.f32(float %max, float 1.0)683 store float %clamp, ptr addrspace(1) poison684 ret void685}686 687; Cannot fold omod into clamp688define amdgpu_ps void @v_omod_div2_clamp_f32(float %a) #0 {689; SI-LABEL: v_omod_div2_clamp_f32:690; SI: ; %bb.0:691; SI-NEXT: v_add_f32_e64 v0, v0, 1.0 clamp692; SI-NEXT: v_mul_f32_e32 v0, 0.5, v0693; SI-NEXT: s_mov_b32 s3, 0xf000694; SI-NEXT: s_mov_b32 s2, -1695; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0696; SI-NEXT: s_endpgm697;698; VI-LABEL: v_omod_div2_clamp_f32:699; VI: ; %bb.0:700; VI-NEXT: v_add_f32_e64 v0, v0, 1.0 clamp701; VI-NEXT: v_mul_f32_e32 v0, 0.5, v0702; VI-NEXT: flat_store_dword v[0:1], v0703; VI-NEXT: s_endpgm704;705; GFX11PLUS-LABEL: v_omod_div2_clamp_f32:706; GFX11PLUS: ; %bb.0:707; GFX11PLUS-NEXT: v_add_f32_e64 v0, v0, 1.0 clamp708; GFX11PLUS-NEXT: s_delay_alu instid0(VALU_DEP_1)709; GFX11PLUS-NEXT: v_mul_f32_e32 v0, 0.5, v0710; GFX11PLUS-NEXT: global_store_b32 v[0:1], v0, off711; GFX11PLUS-NEXT: s_endpgm712 %add = fadd float %a, 1.0713 %max = call float @llvm.maxnum.f32(float %add, float 0.0)714 %clamp = call float @llvm.minnum.f32(float %max, float 1.0)715 %div2 = fmul float %clamp, 0.5716 store float %div2, ptr addrspace(1) poison717 ret void718}719 720define amdgpu_ps void @v_omod_div2_abs_src_f32(float %a) #0 {721; SI-LABEL: v_omod_div2_abs_src_f32:722; SI: ; %bb.0:723; SI-NEXT: v_add_f32_e32 v0, 1.0, v0724; SI-NEXT: v_mul_f32_e64 v0, |v0|, 0.5725; SI-NEXT: s_mov_b32 s3, 0xf000726; SI-NEXT: s_mov_b32 s2, -1727; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0728; SI-NEXT: s_endpgm729;730; VI-LABEL: v_omod_div2_abs_src_f32:731; VI: ; %bb.0:732; VI-NEXT: v_add_f32_e32 v0, 1.0, v0733; VI-NEXT: v_mul_f32_e64 v0, |v0|, 0.5734; VI-NEXT: flat_store_dword v[0:1], v0735; VI-NEXT: s_endpgm736;737; GFX11PLUS-LABEL: v_omod_div2_abs_src_f32:738; GFX11PLUS: ; %bb.0:739; GFX11PLUS-NEXT: v_add_f32_e32 v0, 1.0, v0740; GFX11PLUS-NEXT: s_delay_alu instid0(VALU_DEP_1)741; GFX11PLUS-NEXT: v_mul_f32_e64 v0, |v0|, 0.5742; GFX11PLUS-NEXT: global_store_b32 v[0:1], v0, off743; GFX11PLUS-NEXT: s_endpgm744 %add = fadd float %a, 1.0745 %abs.add = call float @llvm.fabs.f32(float %add)746 %div2 = fmul float %abs.add, 0.5747 store float %div2, ptr addrspace(1) poison748 ret void749}750 751define amdgpu_ps void @v_omod_add_self_clamp_f32(float %a) #0 {752; SI-LABEL: v_omod_add_self_clamp_f32:753; SI: ; %bb.0:754; SI-NEXT: v_add_f32_e64 v0, v0, v0 clamp755; SI-NEXT: s_mov_b32 s3, 0xf000756; SI-NEXT: s_mov_b32 s2, -1757; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0758; SI-NEXT: s_endpgm759;760; VI-LABEL: v_omod_add_self_clamp_f32:761; VI: ; %bb.0:762; VI-NEXT: v_add_f32_e64 v0, v0, v0 clamp763; VI-NEXT: flat_store_dword v[0:1], v0764; VI-NEXT: s_endpgm765;766; GFX11PLUS-LABEL: v_omod_add_self_clamp_f32:767; GFX11PLUS: ; %bb.0:768; GFX11PLUS-NEXT: v_add_f32_e64 v0, v0, v0 clamp769; GFX11PLUS-NEXT: global_store_b32 v[0:1], v0, off770; GFX11PLUS-NEXT: s_endpgm771 %add = fadd float %a, %a772 %max = call float @llvm.maxnum.f32(float %add, float 0.0)773 %clamp = call float @llvm.minnum.f32(float %max, float 1.0)774 store float %clamp, ptr addrspace(1) poison775 ret void776}777 778define amdgpu_ps void @v_omod_add_clamp_self_f32(float %a) #0 {779; SI-LABEL: v_omod_add_clamp_self_f32:780; SI: ; %bb.0:781; SI-NEXT: v_max_f32_e64 v0, v0, v0 clamp782; SI-NEXT: v_add_f32_e32 v0, v0, v0783; SI-NEXT: s_mov_b32 s3, 0xf000784; SI-NEXT: s_mov_b32 s2, -1785; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0786; SI-NEXT: s_endpgm787;788; VI-LABEL: v_omod_add_clamp_self_f32:789; VI: ; %bb.0:790; VI-NEXT: v_max_f32_e64 v0, v0, v0 clamp791; VI-NEXT: v_add_f32_e32 v0, v0, v0792; VI-NEXT: flat_store_dword v[0:1], v0793; VI-NEXT: s_endpgm794;795; GFX11-LABEL: v_omod_add_clamp_self_f32:796; GFX11: ; %bb.0:797; GFX11-NEXT: v_max_f32_e64 v0, v0, v0 clamp798; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)799; GFX11-NEXT: v_add_f32_e32 v0, v0, v0800; GFX11-NEXT: global_store_b32 v[0:1], v0, off801; GFX11-NEXT: s_endpgm802;803; GFX12-LABEL: v_omod_add_clamp_self_f32:804; GFX12: ; %bb.0:805; GFX12-NEXT: v_max_num_f32_e64 v0, v0, v0 clamp806; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)807; GFX12-NEXT: v_add_f32_e32 v0, v0, v0808; GFX12-NEXT: global_store_b32 v[0:1], v0, off809; GFX12-NEXT: s_endpgm810 %max = call float @llvm.maxnum.f32(float %a, float 0.0)811 %clamp = call float @llvm.minnum.f32(float %max, float 1.0)812 %add = fadd float %clamp, %clamp813 store float %add, ptr addrspace(1) poison814 ret void815}816 817define amdgpu_ps void @v_omod_add_abs_self_f32(float %a) #0 {818; SI-LABEL: v_omod_add_abs_self_f32:819; SI: ; %bb.0:820; SI-NEXT: v_add_f32_e32 v0, 1.0, v0821; SI-NEXT: v_add_f32_e64 v0, |v0|, |v0|822; SI-NEXT: s_mov_b32 s3, 0xf000823; SI-NEXT: s_mov_b32 s2, -1824; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0825; SI-NEXT: s_endpgm826;827; VI-LABEL: v_omod_add_abs_self_f32:828; VI: ; %bb.0:829; VI-NEXT: v_add_f32_e32 v0, 1.0, v0830; VI-NEXT: v_add_f32_e64 v0, |v0|, |v0|831; VI-NEXT: flat_store_dword v[0:1], v0832; VI-NEXT: s_endpgm833;834; GFX11PLUS-LABEL: v_omod_add_abs_self_f32:835; GFX11PLUS: ; %bb.0:836; GFX11PLUS-NEXT: v_add_f32_e32 v0, 1.0, v0837; GFX11PLUS-NEXT: s_delay_alu instid0(VALU_DEP_1)838; GFX11PLUS-NEXT: v_add_f32_e64 v0, |v0|, |v0|839; GFX11PLUS-NEXT: global_store_b32 v[0:1], v0, off840; GFX11PLUS-NEXT: s_endpgm841 %x = fadd float %a, 1.0842 %abs.x = call float @llvm.fabs.f32(float %x)843 %add = fadd float %abs.x, %abs.x844 store float %add, ptr addrspace(1) poison845 ret void846}847 848define amdgpu_ps void @v_omod_add_abs_x_x_f32(float %a) #0 {849; SI-LABEL: v_omod_add_abs_x_x_f32:850; SI: ; %bb.0:851; SI-NEXT: v_add_f32_e32 v0, 1.0, v0852; SI-NEXT: v_add_f32_e64 v0, |v0|, v0853; SI-NEXT: s_mov_b32 s3, 0xf000854; SI-NEXT: s_mov_b32 s2, -1855; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0856; SI-NEXT: s_endpgm857;858; VI-LABEL: v_omod_add_abs_x_x_f32:859; VI: ; %bb.0:860; VI-NEXT: v_add_f32_e32 v0, 1.0, v0861; VI-NEXT: v_add_f32_e64 v0, |v0|, v0862; VI-NEXT: flat_store_dword v[0:1], v0863; VI-NEXT: s_endpgm864;865; GFX11PLUS-LABEL: v_omod_add_abs_x_x_f32:866; GFX11PLUS: ; %bb.0:867; GFX11PLUS-NEXT: v_add_f32_e32 v0, 1.0, v0868; GFX11PLUS-NEXT: s_delay_alu instid0(VALU_DEP_1)869; GFX11PLUS-NEXT: v_add_f32_e64 v0, |v0|, v0870; GFX11PLUS-NEXT: global_store_b32 v[0:1], v0, off871; GFX11PLUS-NEXT: s_endpgm872 %x = fadd float %a, 1.0873 %abs.x = call float @llvm.fabs.f32(float %x)874 %add = fadd float %abs.x, %x875 store float %add, ptr addrspace(1) poison876 ret void877}878 879define amdgpu_ps void @v_omod_add_x_abs_x_f32(float %a) #0 {880; SI-LABEL: v_omod_add_x_abs_x_f32:881; SI: ; %bb.0:882; SI-NEXT: v_add_f32_e32 v0, 1.0, v0883; SI-NEXT: v_add_f32_e64 v0, v0, |v0|884; SI-NEXT: s_mov_b32 s3, 0xf000885; SI-NEXT: s_mov_b32 s2, -1886; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0887; SI-NEXT: s_endpgm888;889; VI-LABEL: v_omod_add_x_abs_x_f32:890; VI: ; %bb.0:891; VI-NEXT: v_add_f32_e32 v0, 1.0, v0892; VI-NEXT: v_add_f32_e64 v0, v0, |v0|893; VI-NEXT: flat_store_dword v[0:1], v0894; VI-NEXT: s_endpgm895;896; GFX11PLUS-LABEL: v_omod_add_x_abs_x_f32:897; GFX11PLUS: ; %bb.0:898; GFX11PLUS-NEXT: v_add_f32_e32 v0, 1.0, v0899; GFX11PLUS-NEXT: s_delay_alu instid0(VALU_DEP_1)900; GFX11PLUS-NEXT: v_add_f32_e64 v0, v0, |v0|901; GFX11PLUS-NEXT: global_store_b32 v[0:1], v0, off902; GFX11PLUS-NEXT: s_endpgm903 %x = fadd float %a, 1.0904 %abs.x = call float @llvm.fabs.f32(float %x)905 %add = fadd float %x, %abs.x906 store float %add, ptr addrspace(1) poison907 ret void908}909 910; Don't fold omod into omod into another omod.911define amdgpu_ps void @v_omod_div2_omod_div2_f32(float %a) #0 {912; SI-LABEL: v_omod_div2_omod_div2_f32:913; SI: ; %bb.0:914; SI-NEXT: v_add_f32_e64 v0, v0, 1.0 div:2915; SI-NEXT: v_mul_f32_e32 v0, 0.5, v0916; SI-NEXT: s_mov_b32 s3, 0xf000917; SI-NEXT: s_mov_b32 s2, -1918; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0919; SI-NEXT: s_endpgm920;921; VI-LABEL: v_omod_div2_omod_div2_f32:922; VI: ; %bb.0:923; VI-NEXT: v_add_f32_e64 v0, v0, 1.0 div:2924; VI-NEXT: v_mul_f32_e32 v0, 0.5, v0925; VI-NEXT: flat_store_dword v[0:1], v0926; VI-NEXT: s_endpgm927;928; GFX11PLUS-LABEL: v_omod_div2_omod_div2_f32:929; GFX11PLUS: ; %bb.0:930; GFX11PLUS-NEXT: v_add_f32_e64 v0, v0, 1.0 div:2931; GFX11PLUS-NEXT: s_delay_alu instid0(VALU_DEP_1)932; GFX11PLUS-NEXT: v_mul_f32_e32 v0, 0.5, v0933; GFX11PLUS-NEXT: global_store_b32 v[0:1], v0, off934; GFX11PLUS-NEXT: s_endpgm935 %add = fadd float %a, 1.0936 %div2.0 = fmul float %add, 0.5937 %div2.1 = fmul float %div2.0, 0.5938 store float %div2.1, ptr addrspace(1) poison939 ret void940}941 942; Don't fold omod if denorms enabled943define amdgpu_ps void @v_omod_div2_f32_denormals(float %a) #2 {944; SI-LABEL: v_omod_div2_f32_denormals:945; SI: ; %bb.0:946; SI-NEXT: v_add_f32_e32 v0, 1.0, v0947; SI-NEXT: v_mul_f32_e32 v0, 0.5, v0948; SI-NEXT: s_mov_b32 s3, 0xf000949; SI-NEXT: s_mov_b32 s2, -1950; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0951; SI-NEXT: s_endpgm952;953; VI-LABEL: v_omod_div2_f32_denormals:954; VI: ; %bb.0:955; VI-NEXT: v_add_f32_e32 v0, 1.0, v0956; VI-NEXT: v_mul_f32_e32 v0, 0.5, v0957; VI-NEXT: flat_store_dword v[0:1], v0958; VI-NEXT: s_endpgm959;960; GFX11PLUS-LABEL: v_omod_div2_f32_denormals:961; GFX11PLUS: ; %bb.0:962; GFX11PLUS-NEXT: v_add_f32_e32 v0, 1.0, v0963; GFX11PLUS-NEXT: s_delay_alu instid0(VALU_DEP_1)964; GFX11PLUS-NEXT: v_mul_f32_e32 v0, 0.5, v0965; GFX11PLUS-NEXT: global_store_b32 v[0:1], v0, off966; GFX11PLUS-NEXT: s_endpgm967 %add = fadd float %a, 1.0968 %div2 = fmul float %add, 0.5969 store float %div2, ptr addrspace(1) poison970 ret void971}972 973; Don't fold omod if denorms enabled.974define amdgpu_ps void @v_omod_div2_f64_denormals(double %a) #6 {975; SI-LABEL: v_omod_div2_f64_denormals:976; SI: ; %bb.0:977; SI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0978; SI-NEXT: s_mov_b32 s3, 0xf000979; SI-NEXT: v_mul_f64 v[0:1], v[0:1], 0.5980; SI-NEXT: s_mov_b32 s2, -1981; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0982; SI-NEXT: s_endpgm983;984; VI-LABEL: v_omod_div2_f64_denormals:985; VI: ; %bb.0:986; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.0987; VI-NEXT: v_mul_f64 v[0:1], v[0:1], 0.5988; VI-NEXT: flat_store_dwordx2 v[0:1], v[0:1]989; VI-NEXT: s_endpgm990;991; GFX11-LABEL: v_omod_div2_f64_denormals:992; GFX11: ; %bb.0:993; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.0994; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)995; GFX11-NEXT: v_mul_f64 v[0:1], v[0:1], 0.5996; GFX11-NEXT: global_store_b64 v[0:1], v[0:1], off997; GFX11-NEXT: s_endpgm998;999; GFX12-LABEL: v_omod_div2_f64_denormals:1000; GFX12: ; %bb.0:1001; GFX12-NEXT: v_add_f64_e32 v[0:1], 1.0, v[0:1]1002; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)1003; GFX12-NEXT: v_mul_f64_e32 v[0:1], 0.5, v[0:1]1004; GFX12-NEXT: global_store_b64 v[0:1], v[0:1], off1005; GFX12-NEXT: s_endpgm1006 %add = fadd double %a, 1.01007 %div2 = fmul double %add, 0.51008 store double %div2, ptr addrspace(1) poison1009 ret void1010}1011 1012; Don't fold omod if denorms enabled for add form.1013define amdgpu_ps void @v_omod_mul2_f32_denormals(float %a) #2 {1014; SI-LABEL: v_omod_mul2_f32_denormals:1015; SI: ; %bb.0:1016; SI-NEXT: v_add_f32_e32 v0, 1.0, v01017; SI-NEXT: v_add_f32_e32 v0, v0, v01018; SI-NEXT: s_mov_b32 s3, 0xf0001019; SI-NEXT: s_mov_b32 s2, -11020; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01021; SI-NEXT: s_endpgm1022;1023; VI-LABEL: v_omod_mul2_f32_denormals:1024; VI: ; %bb.0:1025; VI-NEXT: v_add_f32_e32 v0, 1.0, v01026; VI-NEXT: v_add_f32_e32 v0, v0, v01027; VI-NEXT: flat_store_dword v[0:1], v01028; VI-NEXT: s_endpgm1029;1030; GFX11PLUS-LABEL: v_omod_mul2_f32_denormals:1031; GFX11PLUS: ; %bb.0:1032; GFX11PLUS-NEXT: v_add_f32_e32 v0, 1.0, v01033; GFX11PLUS-NEXT: s_delay_alu instid0(VALU_DEP_1)1034; GFX11PLUS-NEXT: v_add_f32_e32 v0, v0, v01035; GFX11PLUS-NEXT: global_store_b32 v[0:1], v0, off1036; GFX11PLUS-NEXT: s_endpgm1037 %add = fadd float %a, 1.01038 %mul2 = fadd float %add, %add1039 store float %mul2, ptr addrspace(1) poison1040 ret void1041}1042 1043; Don't fold omod if denorms enabled for add form.1044define amdgpu_ps void @v_omod_mul2_f64_denormals(double %a) #2 {1045; SI-LABEL: v_omod_mul2_f64_denormals:1046; SI: ; %bb.0:1047; SI-NEXT: v_add_f64 v[0:1], v[0:1], 1.01048; SI-NEXT: s_mov_b32 s3, 0xf0001049; SI-NEXT: v_add_f64 v[0:1], v[0:1], v[0:1]1050; SI-NEXT: s_mov_b32 s2, -11051; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 01052; SI-NEXT: s_endpgm1053;1054; VI-LABEL: v_omod_mul2_f64_denormals:1055; VI: ; %bb.0:1056; VI-NEXT: v_add_f64 v[0:1], v[0:1], 1.01057; VI-NEXT: v_add_f64 v[0:1], v[0:1], v[0:1]1058; VI-NEXT: flat_store_dwordx2 v[0:1], v[0:1]1059; VI-NEXT: s_endpgm1060;1061; GFX11-LABEL: v_omod_mul2_f64_denormals:1062; GFX11: ; %bb.0:1063; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], 1.01064; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)1065; GFX11-NEXT: v_add_f64 v[0:1], v[0:1], v[0:1]1066; GFX11-NEXT: global_store_b64 v[0:1], v[0:1], off1067; GFX11-NEXT: s_endpgm1068;1069; GFX12-LABEL: v_omod_mul2_f64_denormals:1070; GFX12: ; %bb.0:1071; GFX12-NEXT: v_add_f64_e32 v[0:1], 1.0, v[0:1]1072; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1)1073; GFX12-NEXT: v_add_f64_e32 v[0:1], v[0:1], v[0:1]1074; GFX12-NEXT: global_store_b64 v[0:1], v[0:1], off1075; GFX12-NEXT: s_endpgm1076 %add = fadd double %a, 1.01077 %mul2 = fadd double %add, %add1078 store double %mul2, ptr addrspace(1) poison1079 ret void1080}1081 1082; Don't fold omod if denorms enabled1083define amdgpu_ps void @v_omod_div2_f16_denormals(half %a) #0 {1084; SI-LABEL: v_omod_div2_f16_denormals:1085; SI: ; %bb.0:1086; SI-NEXT: v_cvt_f16_f32_e32 v0, v01087; SI-NEXT: s_mov_b32 s3, 0xf0001088; SI-NEXT: s_mov_b32 s2, -11089; SI-NEXT: v_cvt_f32_f16_e32 v0, v01090; SI-NEXT: v_add_f32_e64 v0, v0, 1.0 div:21091; SI-NEXT: v_cvt_f16_f32_e32 v0, v01092; SI-NEXT: buffer_store_short v0, off, s[0:3], 01093; SI-NEXT: s_endpgm1094;1095; VI-LABEL: v_omod_div2_f16_denormals:1096; VI: ; %bb.0:1097; VI-NEXT: v_add_f16_e32 v0, 1.0, v01098; VI-NEXT: v_mul_f16_e32 v0, 0.5, v01099; VI-NEXT: flat_store_short v[0:1], v01100; VI-NEXT: s_endpgm1101;1102; GFX11-TRUE16-LABEL: v_omod_div2_f16_denormals:1103; GFX11-TRUE16: ; %bb.0:1104; GFX11-TRUE16-NEXT: v_add_f16_e32 v0.l, 1.0, v0.l1105; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)1106; GFX11-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0.5, v0.l1107; GFX11-TRUE16-NEXT: global_store_b16 v[0:1], v0, off1108; GFX11-TRUE16-NEXT: s_endpgm1109;1110; GFX11-FAKE16-LABEL: v_omod_div2_f16_denormals:1111; GFX11-FAKE16: ; %bb.0:1112; GFX11-FAKE16-NEXT: v_add_f16_e32 v0, 1.0, v01113; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)1114; GFX11-FAKE16-NEXT: v_mul_f16_e32 v0, 0.5, v01115; GFX11-FAKE16-NEXT: global_store_b16 v[0:1], v0, off1116; GFX11-FAKE16-NEXT: s_endpgm1117;1118; GFX12-TRUE16-LABEL: v_omod_div2_f16_denormals:1119; GFX12-TRUE16: ; %bb.0:1120; GFX12-TRUE16-NEXT: v_add_f16_e32 v0.l, 1.0, v0.l1121; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)1122; GFX12-TRUE16-NEXT: v_mul_f16_e32 v0.l, 0.5, v0.l1123; GFX12-TRUE16-NEXT: global_store_b16 v[0:1], v0, off1124; GFX12-TRUE16-NEXT: s_endpgm1125;1126; GFX12-FAKE16-LABEL: v_omod_div2_f16_denormals:1127; GFX12-FAKE16: ; %bb.0:1128; GFX12-FAKE16-NEXT: v_add_f16_e32 v0, 1.0, v01129; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)1130; GFX12-FAKE16-NEXT: v_mul_f16_e32 v0, 0.5, v01131; GFX12-FAKE16-NEXT: global_store_b16 v[0:1], v0, off1132; GFX12-FAKE16-NEXT: s_endpgm1133 %add = fadd half %a, 1.01134 %div2 = fmul half %add, 0.51135 store half %div2, ptr addrspace(1) poison1136 ret void1137}1138 1139; Don't fold omod if denorms enabled for add form.1140define amdgpu_ps void @v_omod_mul2_f16_denormals(half %a) #0 {1141; SI-LABEL: v_omod_mul2_f16_denormals:1142; SI: ; %bb.0:1143; SI-NEXT: v_cvt_f16_f32_e32 v0, v01144; SI-NEXT: s_mov_b32 s3, 0xf0001145; SI-NEXT: s_mov_b32 s2, -11146; SI-NEXT: v_cvt_f32_f16_e32 v0, v01147; SI-NEXT: v_add_f32_e64 v0, v0, 1.0 mul:21148; SI-NEXT: v_cvt_f16_f32_e32 v0, v01149; SI-NEXT: buffer_store_short v0, off, s[0:3], 01150; SI-NEXT: s_endpgm1151;1152; VI-LABEL: v_omod_mul2_f16_denormals:1153; VI: ; %bb.0:1154; VI-NEXT: v_add_f16_e32 v0, 1.0, v01155; VI-NEXT: v_add_f16_e32 v0, v0, v01156; VI-NEXT: flat_store_short v[0:1], v01157; VI-NEXT: s_endpgm1158;1159; GFX11-TRUE16-LABEL: v_omod_mul2_f16_denormals:1160; GFX11-TRUE16: ; %bb.0:1161; GFX11-TRUE16-NEXT: v_add_f16_e32 v0.l, 1.0, v0.l1162; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)1163; GFX11-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v0.l1164; GFX11-TRUE16-NEXT: global_store_b16 v[0:1], v0, off1165; GFX11-TRUE16-NEXT: s_endpgm1166;1167; GFX11-FAKE16-LABEL: v_omod_mul2_f16_denormals:1168; GFX11-FAKE16: ; %bb.0:1169; GFX11-FAKE16-NEXT: v_add_f16_e32 v0, 1.0, v01170; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)1171; GFX11-FAKE16-NEXT: v_add_f16_e32 v0, v0, v01172; GFX11-FAKE16-NEXT: global_store_b16 v[0:1], v0, off1173; GFX11-FAKE16-NEXT: s_endpgm1174;1175; GFX12-TRUE16-LABEL: v_omod_mul2_f16_denormals:1176; GFX12-TRUE16: ; %bb.0:1177; GFX12-TRUE16-NEXT: v_add_f16_e32 v0.l, 1.0, v0.l1178; GFX12-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)1179; GFX12-TRUE16-NEXT: v_add_f16_e32 v0.l, v0.l, v0.l1180; GFX12-TRUE16-NEXT: global_store_b16 v[0:1], v0, off1181; GFX12-TRUE16-NEXT: s_endpgm1182;1183; GFX12-FAKE16-LABEL: v_omod_mul2_f16_denormals:1184; GFX12-FAKE16: ; %bb.0:1185; GFX12-FAKE16-NEXT: v_add_f16_e32 v0, 1.0, v01186; GFX12-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_1)1187; GFX12-FAKE16-NEXT: v_add_f16_e32 v0, v0, v01188; GFX12-FAKE16-NEXT: global_store_b16 v[0:1], v0, off1189; GFX12-FAKE16-NEXT: s_endpgm1190 %add = fadd half %a, 1.01191 %mul2 = fadd half %add, %add1192 store half %mul2, ptr addrspace(1) poison1193 ret void1194}1195 1196define amdgpu_ps void @v_omod_div2_f16_no_denormals(half %a) #3 {1197; SI-LABEL: v_omod_div2_f16_no_denormals:1198; SI: ; %bb.0:1199; SI-NEXT: v_cvt_f16_f32_e32 v0, v01200; SI-NEXT: s_mov_b32 s3, 0xf0001201; SI-NEXT: s_mov_b32 s2, -11202; SI-NEXT: v_cvt_f32_f16_e32 v0, v01203; SI-NEXT: v_add_f32_e64 v0, v0, 1.0 div:21204; SI-NEXT: v_cvt_f16_f32_e32 v0, v01205; SI-NEXT: buffer_store_short v0, off, s[0:3], 01206; SI-NEXT: s_endpgm1207;1208; VI-LABEL: v_omod_div2_f16_no_denormals:1209; VI: ; %bb.0:1210; VI-NEXT: v_add_f16_e64 v0, v0, 1.0 div:21211; VI-NEXT: flat_store_short v[0:1], v01212; VI-NEXT: s_endpgm1213;1214; GFX11-TRUE16-LABEL: v_omod_div2_f16_no_denormals:1215; GFX11-TRUE16: ; %bb.0:1216; GFX11-TRUE16-NEXT: v_add_f16_e64 v0.l, v0.l, 1.0 div:21217; GFX11-TRUE16-NEXT: global_store_b16 v[0:1], v0, off1218; GFX11-TRUE16-NEXT: s_endpgm1219;1220; GFX11-FAKE16-LABEL: v_omod_div2_f16_no_denormals:1221; GFX11-FAKE16: ; %bb.0:1222; GFX11-FAKE16-NEXT: v_add_f16_e64 v0, v0, 1.0 div:21223; GFX11-FAKE16-NEXT: global_store_b16 v[0:1], v0, off1224; GFX11-FAKE16-NEXT: s_endpgm1225;1226; GFX12-TRUE16-LABEL: v_omod_div2_f16_no_denormals:1227; GFX12-TRUE16: ; %bb.0:1228; GFX12-TRUE16-NEXT: v_add_f16_e64 v0.l, v0.l, 1.0 div:21229; GFX12-TRUE16-NEXT: global_store_b16 v[0:1], v0, off1230; GFX12-TRUE16-NEXT: s_endpgm1231;1232; GFX12-FAKE16-LABEL: v_omod_div2_f16_no_denormals:1233; GFX12-FAKE16: ; %bb.0:1234; GFX12-FAKE16-NEXT: v_add_f16_e64 v0, v0, 1.0 div:21235; GFX12-FAKE16-NEXT: global_store_b16 v[0:1], v0, off1236; GFX12-FAKE16-NEXT: s_endpgm1237 %add = fadd half %a, 1.01238 %div2 = fmul half %add, 0.51239 store half %div2, ptr addrspace(1) poison1240 ret void1241}1242 1243define amdgpu_ps void @v_omod_mac_to_mad(float %b, float %a) #0 {1244; SI-LABEL: v_omod_mac_to_mad:1245; SI: ; %bb.0:1246; SI-NEXT: v_mad_f32 v1, v1, v1, v0 mul:21247; SI-NEXT: v_mul_f32_e32 v0, v1, v01248; SI-NEXT: s_mov_b32 s3, 0xf0001249; SI-NEXT: s_mov_b32 s2, -11250; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01251; SI-NEXT: s_endpgm1252;1253; VI-LABEL: v_omod_mac_to_mad:1254; VI: ; %bb.0:1255; VI-NEXT: v_mad_f32 v1, v1, v1, v0 mul:21256; VI-NEXT: v_mul_f32_e32 v0, v1, v01257; VI-NEXT: flat_store_dword v[0:1], v01258; VI-NEXT: s_endpgm1259;1260; GFX11PLUS-LABEL: v_omod_mac_to_mad:1261; GFX11PLUS: ; %bb.0:1262; GFX11PLUS-NEXT: v_mul_f32_e32 v1, v1, v11263; GFX11PLUS-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)1264; GFX11PLUS-NEXT: v_add_f32_e64 v1, v1, v0 mul:21265; GFX11PLUS-NEXT: v_mul_f32_e32 v0, v1, v01266; GFX11PLUS-NEXT: global_store_b32 v[0:1], v0, off1267; GFX11PLUS-NEXT: s_endpgm1268 %mul = fmul float %a, %a1269 %add = fadd float %mul, %b1270 %mad = fmul float %add, 2.01271 %res = fmul float %mad, %b1272 store float %res, ptr addrspace(1) poison1273 ret void1274}1275 1276define amdgpu_ps void @v_clamp_omod_div2_f32_minimumnum_maximumnum(float %a) #0 {1277; SI-LABEL: v_clamp_omod_div2_f32_minimumnum_maximumnum:1278; SI: ; %bb.0:1279; SI-NEXT: v_add_f32_e64 v0, v0, 1.0 clamp div:21280; SI-NEXT: s_mov_b32 s3, 0xf0001281; SI-NEXT: s_mov_b32 s2, -11282; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01283; SI-NEXT: s_endpgm1284;1285; VI-LABEL: v_clamp_omod_div2_f32_minimumnum_maximumnum:1286; VI: ; %bb.0:1287; VI-NEXT: v_add_f32_e64 v0, v0, 1.0 clamp div:21288; VI-NEXT: flat_store_dword v[0:1], v01289; VI-NEXT: s_endpgm1290;1291; GFX11PLUS-LABEL: v_clamp_omod_div2_f32_minimumnum_maximumnum:1292; GFX11PLUS: ; %bb.0:1293; GFX11PLUS-NEXT: v_add_f32_e64 v0, v0, 1.0 clamp div:21294; GFX11PLUS-NEXT: global_store_b32 v[0:1], v0, off1295; GFX11PLUS-NEXT: s_endpgm1296 %add = fadd float %a, 1.01297 %div2 = fmul float %add, 0.51298 1299 %max = call float @llvm.maximumnum.f32(float %div2, float 0.0)1300 %clamp = call float @llvm.minimumnum.f32(float %max, float 1.0)1301 store float %clamp, ptr addrspace(1) poison1302 ret void1303}1304 1305declare i32 @llvm.amdgcn.workitem.id.x() #11306declare float @llvm.fabs.f32(float) #11307declare float @llvm.floor.f32(float) #11308declare float @llvm.minnum.f32(float, float) #11309declare float @llvm.maxnum.f32(float, float) #11310declare float @llvm.amdgcn.fmed3.f32(float, float, float) #11311declare double @llvm.fabs.f64(double) #11312declare double @llvm.minnum.f64(double, double) #11313declare double @llvm.maxnum.f64(double, double) #11314declare half @llvm.fabs.f16(half) #11315declare half @llvm.minnum.f16(half, half) #11316declare half @llvm.maxnum.f16(half, half) #11317declare void @llvm.dbg.value(metadata, i64, metadata, metadata) #11318 1319attributes #0 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" "no-signed-zeros-fp-math"="true" }1320attributes #1 = { nounwind readnone }1321attributes #2 = { nounwind "denormal-fp-math-f32"="ieee,ieee" "no-signed-zeros-fp-math"="true" }1322attributes #3 = { nounwind "denormal-fp-math"="preserve-sign,preserve-sign" "no-signed-zeros-fp-math"="true" }1323attributes #4 = { nounwind "no-signed-zeros-fp-math"="false" }1324attributes #5 = { nounwind "denormal-fp-math"="preserve-sign,preserve-sign" }1325attributes #6 = { nounwind "denormal-fp-math"="ieee,ieee" "no-signed-zeros-fp-math"="true" }1326 1327!llvm.dbg.cu = !{!0}1328!llvm.module.flags = !{!2, !3}1329 1330!0 = distinct !DICompileUnit(language: DW_LANG_C99, file: !1, isOptimized: true, runtimeVersion: 0, emissionKind: NoDebug)1331!1 = !DIFile(filename: "/tmp/foo.cl", directory: "/dev/null")1332!2 = !{i32 2, !"Dwarf Version", i32 4}1333!3 = !{i32 2, !"Debug Info Version", i32 3}1334!4 = !DILocalVariable(name: "add", arg: 1, scope: !5, file: !1, line: 1)1335!5 = distinct !DISubprogram(name: "foo", scope: !1, file: !1, line: 1, type: !6, isLocal: false, isDefinition: true, scopeLine: 2, flags: DIFlagPrototyped, isOptimized: true, unit: !0)1336!6 = !DISubroutineType(types: !7)1337!7 = !{null, !8}1338!8 = !DIBasicType(name: "float", size: 32, align: 32)1339!9 = !DIExpression()1340!10 = !DILocation(line: 1, column: 42, scope: !5)1341