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1; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck %s2; RUN: llc -mtriple=amdgcn -mcpu=tahiti -early-live-intervals < %s | FileCheck %s3 4; CHECK-LABEL: {{^}}fold_sgpr:5; CHECK: v_add_i32_e32 v{{[0-9]+}}, vcc, s6define amdgpu_kernel void @fold_sgpr(ptr addrspace(1) %out, i32 %fold) #1 {7entry:8 %tmp0 = icmp ne i32 %fold, 09 br i1 %tmp0, label %if, label %endif10 11if:12 %id = call i32 @llvm.amdgcn.workitem.id.x()13 %offset = add i32 %fold, %id14 %tmp1 = getelementptr i32, ptr addrspace(1) %out, i32 %offset15 store i32 0, ptr addrspace(1) %tmp116 br label %endif17 18endif:19 ret void20}21 22; CHECK-LABEL: {{^}}fold_imm:23; CHECK: v_or_b32_e32 v{{[0-9]+}}, 524define amdgpu_kernel void @fold_imm(ptr addrspace(1) %out, i32 %cmp) #1 {25entry:26 %fold = add i32 3, 227 %tmp0 = icmp ne i32 %cmp, 028 br i1 %tmp0, label %if, label %endif29 30if:31 %id = call i32 @llvm.amdgcn.workitem.id.x()32 %val = or i32 %id, %fold33 store i32 %val, ptr addrspace(1) %out34 br label %endif35 36endif:37 ret void38}39 40; CHECK-LABEL: {{^}}fold_64bit_constant_add:41; CHECK-NOT: s_mov_b6442; FIXME: It would be better if we could use v_add here and drop the extra43; v_mov_b32 instructions.44; CHECK-DAG: s_add_u32 [[LO:s[0-9]+]], s{{[0-9]+}}, 145; CHECK-DAG: s_addc_u32 [[HI:s[0-9]+]], s{{[0-9]+}}, 046; CHECK-DAG: v_mov_b32_e32 v[[VLO:[0-9]+]], [[LO]]47; CHECK-DAG: v_mov_b32_e32 v[[VHI:[0-9]+]], [[HI]]48; CHECK: buffer_store_dwordx2 v[[[VLO]]:[[VHI]]],49 50define amdgpu_kernel void @fold_64bit_constant_add(ptr addrspace(1) %out, i32 %cmp, i64 %val) #1 {51entry:52 %tmp0 = add i64 %val, 153 store i64 %tmp0, ptr addrspace(1) %out54 ret void55}56 57; Inline constants should always be folded.58 59; CHECK-LABEL: {{^}}vector_inline:60; CHECK: v_xor_b32_e32 v{{[0-9]+}}, 5, v{{[0-9]+}}61; CHECK: v_xor_b32_e32 v{{[0-9]+}}, 5, v{{[0-9]+}}62; CHECK: v_xor_b32_e32 v{{[0-9]+}}, 5, v{{[0-9]+}}63; CHECK: v_xor_b32_e32 v{{[0-9]+}}, 5, v{{[0-9]+}}64 65define amdgpu_kernel void @vector_inline(ptr addrspace(1) %out) #1 {66entry:67 %tmp0 = call i32 @llvm.amdgcn.workitem.id.x()68 %tmp1 = add i32 %tmp0, 169 %tmp2 = add i32 %tmp0, 270 %tmp3 = add i32 %tmp0, 371 %vec0 = insertelement <4 x i32> poison, i32 %tmp0, i32 072 %vec1 = insertelement <4 x i32> %vec0, i32 %tmp1, i32 173 %vec2 = insertelement <4 x i32> %vec1, i32 %tmp2, i32 274 %vec3 = insertelement <4 x i32> %vec2, i32 %tmp3, i32 375 %tmp4 = xor <4 x i32> <i32 5, i32 5, i32 5, i32 5>, %vec376 store <4 x i32> %tmp4, ptr addrspace(1) %out77 ret void78}79 80; Immediates with one use should be folded81; CHECK-LABEL: {{^}}imm_one_use:82; CHECK: v_xor_b32_e32 v{{[0-9]+}}, 0x64, v{{[0-9]+}}83 84define amdgpu_kernel void @imm_one_use(ptr addrspace(1) %out) #1 {85entry:86 %tmp0 = call i32 @llvm.amdgcn.workitem.id.x()87 %tmp1 = xor i32 %tmp0, 10088 store i32 %tmp1, ptr addrspace(1) %out89 ret void90}91; CHECK-LABEL: {{^}}vector_imm:92; CHECK: v_xor_b32_e32 v{{[0-9]}}, 0x64, v{{[0-9]}}93; CHECK: v_xor_b32_e32 v{{[0-9]}}, 0x64, v{{[0-9]}}94; CHECK: v_xor_b32_e32 v{{[0-9]}}, 0x64, v{{[0-9]}}95; CHECK: v_xor_b32_e32 v{{[0-9]}}, 0x64, v{{[0-9]}}96 97define amdgpu_kernel void @vector_imm(ptr addrspace(1) %out) #1 {98entry:99 %tmp0 = call i32 @llvm.amdgcn.workitem.id.x()100 %tmp1 = add i32 %tmp0, 1101 %tmp2 = add i32 %tmp0, 2102 %tmp3 = add i32 %tmp0, 3103 %vec0 = insertelement <4 x i32> poison, i32 %tmp0, i32 0104 %vec1 = insertelement <4 x i32> %vec0, i32 %tmp1, i32 1105 %vec2 = insertelement <4 x i32> %vec1, i32 %tmp2, i32 2106 %vec3 = insertelement <4 x i32> %vec2, i32 %tmp3, i32 3107 %tmp4 = xor <4 x i32> <i32 100, i32 100, i32 100, i32 100>, %vec3108 store <4 x i32> %tmp4, ptr addrspace(1) %out109 ret void110}111 112; A subregister use operand should not be tied.113; CHECK-LABEL: {{^}}no_fold_tied_subregister:114; CHECK: buffer_load_dwordx2 v[[[LO:[0-9]+]]:[[HI:[0-9]+]]]115; CHECK: v_madmk_f32 v[[RES:[0-9]+]], v[[HI]], 0x41200000, v[[LO]]116; CHECK: buffer_store_dword v[[RES]]117define amdgpu_kernel void @no_fold_tied_subregister() #1 {118 %tmp1 = load volatile <2 x float>, ptr addrspace(1) poison119 %tmp2 = extractelement <2 x float> %tmp1, i32 0120 %tmp3 = extractelement <2 x float> %tmp1, i32 1121 %tmp4 = fmul float %tmp3, 10.0122 %tmp5 = fadd float %tmp4, %tmp2123 store volatile float %tmp5, ptr addrspace(1) poison124 ret void125}126 127; There should be exact one folding on the same operand.128; CHECK-LABEL: {{^}}no_extra_fold_on_same_opnd129; CHECK-NOT: %bb.1:130; CHECK: v_xor_b32_e32 v{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}131define void @no_extra_fold_on_same_opnd() #1 {132entry:133 %s0 = load i32, ptr addrspace(5) poison, align 4134 %s0.i64= zext i32 %s0 to i64135 br label %for.body.i.i136 137for.body.i.i:138 %s1 = load i32, ptr addrspace(1) poison, align 8139 %s1.i64 = sext i32 %s1 to i64140 %xor = xor i64 %s1.i64, %s0.i64141 %flag = icmp ult i64 %xor, 8142 br i1 %flag, label %if.then, label %if.else143 144if.then:145 unreachable146 147if.else:148 unreachable149}150 151; The compared constant is equal to {42, 42}. It cannot be reduced to152; a compare with 42.153 154define i32 @issue139908(i64 %in) {155; CHECK-LABEL: issue139908:156; CHECK: ; %bb.0:157; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)158; CHECK-NEXT: s_mov_b32 s4, 42159; CHECK-NEXT: s_mov_b32 s5, s4160; CHECK-NEXT: v_cmp_eq_u64_e32 vcc, s[4:5], v[0:1]161; CHECK-NEXT: v_cndmask_b32_e64 v0, 2, 1, vcc162; CHECK-NEXT: s_setpc_b64 s[30:31]163 %eq = icmp eq i64 %in, 180388626474164 %result = select i1 %eq, i32 1, i32 2165 ret i32 %result166}167 168declare i32 @llvm.amdgcn.workitem.id.x() #0169 170attributes #0 = { nounwind readnone }171attributes #1 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" }172