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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# REQUIRES: asserts3# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -verify-regalloc -misched-only-block=999 -start-before=machine-scheduler -stop-after=greedy,0 -o - %s | FileCheck %s4 5# This run line is a total hack to get the live intervals to make it6# to the verifier. This requires asserts to use7# -misched-only-block. We use the scheduler only because -start-before8# doesn't see si-optimize-exec-masking-pre-ra unless the scheduler is9# part of the pass pipeline.10 11---12name: subreg_value_undef13tracksRegLiveness: true14body: |15 ; CHECK-LABEL: name: subreg_value_undef16 ; CHECK: bb.0:17 ; CHECK-NEXT: successors: %bb.1(0x80000000)18 ; CHECK-NEXT: liveins: $sgpr0_sgpr119 ; CHECK-NEXT: {{ $}}20 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr0_sgpr121 ; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[COPY]], 0, 0 :: (load (s128), align 8, addrspace 1)22 ; CHECK-NEXT: undef [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_128 = S_MOV_B32 -123 ; CHECK-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, undef [[S_MOV_B32_]].sub0, implicit-def dead $scc24 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sgpr_128 = COPY [[S_LOAD_DWORDX4_IMM]].sub025 ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit $vcc26 ; CHECK-NEXT: {{ $}}27 ; CHECK-NEXT: bb.1:28 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]].sub129 bb.0:30 liveins: $sgpr0_sgpr131 %0:sgpr_64 = COPY $sgpr0_sgpr132 %1:sgpr_128 = S_LOAD_DWORDX4_IMM %0, 0, 0 :: (load (s128), align 8, addrspace 1)33 undef %2.sub1:sgpr_128 = S_MOV_B32 -134 %3:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, undef %2.sub0, implicit $exec35 %4:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 1, %3, implicit $exec36 $vcc_lo = S_AND_B32 $exec_lo, %4, implicit-def dead $scc37 %2.sub1:sgpr_128 = COPY %1.sub038 S_CBRANCH_VCCNZ %bb.1, implicit $vcc39 40 bb.1:41 S_NOP 0, implicit %2.sub142...43 44---45name: needs_distribute_046tracksRegLiveness: true47body: |48 ; CHECK-LABEL: name: needs_distribute_049 ; CHECK: bb.0:50 ; CHECK-NEXT: successors: %bb.1(0x80000000)51 ; CHECK-NEXT: liveins: $sgpr0_sgpr152 ; CHECK-NEXT: {{ $}}53 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr0_sgpr154 ; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[COPY]], 0, 0 :: (load (s128), align 8, addrspace 1)55 ; CHECK-NEXT: undef [[S_MOV_B32_:%[0-9]+]].sub0:sreg_64_xexec = S_MOV_B32 -156 ; CHECK-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, [[S_MOV_B32_]].sub0, implicit-def dead $scc57 ; CHECK-NEXT: dead [[S_MOV_B32_:%[0-9]+]].sub1:sreg_64_xexec = COPY [[S_LOAD_DWORDX4_IMM]].sub058 ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit $vcc59 ; CHECK-NEXT: {{ $}}60 ; CHECK-NEXT: bb.1:61 bb.0:62 liveins: $sgpr0_sgpr163 %0:sgpr_64 = COPY $sgpr0_sgpr164 %1:sgpr_128 = S_LOAD_DWORDX4_IMM %0, 0, 0 :: (load (s128), align 8, addrspace 1)65 undef %2.sub0:sreg_64_xexec = S_MOV_B32 -166 %3:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %2.sub0, implicit $exec67 %4:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 1, %3, implicit $exec68 $vcc_lo = S_AND_B32 $exec_lo, %4, implicit-def dead $scc69 %2.sub1:sreg_64_xexec = COPY %1.sub070 S_CBRANCH_VCCNZ %bb.1, implicit $vcc71 72 bb.1:73...74 75---76name: needs_distribute_177tracksRegLiveness: true78body: |79 ; CHECK-LABEL: name: needs_distribute_180 ; CHECK: bb.0:81 ; CHECK-NEXT: successors: %bb.1(0x80000000)82 ; CHECK-NEXT: liveins: $sgpr0_sgpr183 ; CHECK-NEXT: {{ $}}84 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr0_sgpr185 ; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[COPY]], 0, 0 :: (load (s128), align 8, addrspace 1)86 ; CHECK-NEXT: undef [[S_MOV_B32_:%[0-9]+]].sub0:sreg_64_xexec = S_MOV_B32 -187 ; CHECK-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, [[S_MOV_B32_]].sub0, implicit-def dead $scc88 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sreg_64_xexec = COPY [[S_LOAD_DWORDX4_IMM]].sub089 ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit $vcc90 ; CHECK-NEXT: {{ $}}91 ; CHECK-NEXT: bb.1:92 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]].sub193 bb.0:94 liveins: $sgpr0_sgpr195 %0:sgpr_64 = COPY $sgpr0_sgpr196 %1:sgpr_128 = S_LOAD_DWORDX4_IMM %0, 0, 0 :: (load (s128), align 8, addrspace 1)97 undef %2.sub0:sreg_64_xexec = S_MOV_B32 -198 %3:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %2.sub0, implicit $exec99 %4:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 1, %3, implicit $exec100 $vcc_lo = S_AND_B32 $exec_lo, %4, implicit-def dead $scc101 %2.sub1:sreg_64_xexec = COPY %1.sub0102 S_CBRANCH_VCCNZ %bb.1, implicit $vcc103 104 bb.1:105 S_NOP 0, implicit %2.sub1106...107 108---109name: needs_distribute_2110tracksRegLiveness: true111body: |112 ; CHECK-LABEL: name: needs_distribute_2113 ; CHECK: bb.0:114 ; CHECK-NEXT: successors: %bb.1(0x80000000)115 ; CHECK-NEXT: liveins: $sgpr0_sgpr1116 ; CHECK-NEXT: {{ $}}117 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr0_sgpr1118 ; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[COPY]], 0, 0 :: (load (s128), align 8, addrspace 1)119 ; CHECK-NEXT: undef [[S_MOV_B32_:%[0-9]+]].sub0:sreg_64_xexec = S_MOV_B32 -1120 ; CHECK-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, [[S_MOV_B32_]].sub0, implicit-def dead $scc121 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sreg_64_xexec = COPY [[S_LOAD_DWORDX4_IMM]].sub0122 ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit $vcc123 ; CHECK-NEXT: {{ $}}124 ; CHECK-NEXT: bb.1:125 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]]126 bb.0:127 liveins: $sgpr0_sgpr1128 %0:sgpr_64 = COPY $sgpr0_sgpr1129 %1:sgpr_128 = S_LOAD_DWORDX4_IMM %0, 0, 0 :: (load (s128), align 8, addrspace 1)130 undef %2.sub0:sreg_64_xexec = S_MOV_B32 -1131 %3:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %2.sub0, implicit $exec132 %4:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 1, %3, implicit $exec133 $vcc_lo = S_AND_B32 $exec_lo, %4, implicit-def dead $scc134 %2.sub1:sreg_64_xexec = COPY %1.sub0135 S_CBRANCH_VCCNZ %bb.1, implicit $vcc136 137 bb.1:138 S_NOP 0, implicit %2139...140 141---142name: needs_distribute_3143tracksRegLiveness: true144body: |145 ; CHECK-LABEL: name: needs_distribute_3146 ; CHECK: bb.0:147 ; CHECK-NEXT: successors: %bb.1(0x80000000)148 ; CHECK-NEXT: liveins: $sgpr0_sgpr1149 ; CHECK-NEXT: {{ $}}150 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr0_sgpr1151 ; CHECK-NEXT: [[S_LOAD_DWORDX4_IMM:%[0-9]+]]:sgpr_128 = S_LOAD_DWORDX4_IMM [[COPY]], 0, 0 :: (load (s128), align 8, addrspace 1)152 ; CHECK-NEXT: undef [[S_MOV_B32_:%[0-9]+]].sub0:sreg_64_xexec = S_MOV_B32 -1153 ; CHECK-NEXT: $vcc_lo = S_ANDN2_B32 $exec_lo, [[S_MOV_B32_]].sub0, implicit-def dead $scc154 ; CHECK-NEXT: [[S_MOV_B32_:%[0-9]+]].sub1:sreg_64_xexec = COPY [[S_LOAD_DWORDX4_IMM]].sub0155 ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit $vcc156 ; CHECK-NEXT: {{ $}}157 ; CHECK-NEXT: bb.1:158 ; CHECK-NEXT: S_NOP 0, implicit [[S_MOV_B32_]].sub0159 bb.0:160 liveins: $sgpr0_sgpr1161 %0:sgpr_64 = COPY $sgpr0_sgpr1162 %1:sgpr_128 = S_LOAD_DWORDX4_IMM %0, 0, 0 :: (load (s128), align 8, addrspace 1)163 undef %2.sub0:sreg_64_xexec = S_MOV_B32 -1164 %3:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %2.sub0, implicit $exec165 %4:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 1, %3, implicit $exec166 $vcc_lo = S_AND_B32 $exec_lo, %4, implicit-def dead $scc167 %2.sub1:sreg_64_xexec = COPY %1.sub0168 S_CBRANCH_VCCNZ %bb.1, implicit $vcc169 170 bb.1:171 S_NOP 0, implicit %2.sub0172...173