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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -verify-regalloc -start-before=machine-scheduler -stop-after=greedy,0 -o - %s | FileCheck %s3 4# Make sure liveness is correctly updated when folding the cndmask and5# compare.6 7---8name: cndmask_same_block9tracksRegLiveness: true10body: |11 ; CHECK-LABEL: name: cndmask_same_block12 ; CHECK: bb.0:13 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)14 ; CHECK-NEXT: {{ $}}15 ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF16 ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit undef $vcc17 ; CHECK-NEXT: {{ $}}18 ; CHECK-NEXT: bb.1:19 ; CHECK-NEXT: successors: %bb.4(0x80000000)20 ; CHECK-NEXT: {{ $}}21 ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.4, implicit undef $vcc22 ; CHECK-NEXT: S_BRANCH %bb.423 ; CHECK-NEXT: {{ $}}24 ; CHECK-NEXT: bb.2:25 ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.3(0x40000000)26 ; CHECK-NEXT: {{ $}}27 ; CHECK-NEXT: $vcc = S_ANDN2_B64 $exec, [[DEF]], implicit-def $scc28 ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.4, implicit $vcc29 ; CHECK-NEXT: S_BRANCH %bb.330 ; CHECK-NEXT: {{ $}}31 ; CHECK-NEXT: bb.3:32 ; CHECK-NEXT: successors: %bb.4(0x80000000)33 ; CHECK-NEXT: {{ $}}34 ; CHECK-NEXT: S_BRANCH %bb.435 ; CHECK-NEXT: {{ $}}36 ; CHECK-NEXT: bb.4:37 bb.0:38 %0:sreg_64_xexec = IMPLICIT_DEF39 S_CBRANCH_VCCNZ %bb.2, implicit undef $vcc40 41 bb.1:42 S_CBRANCH_VCCNZ %bb.4, implicit undef $vcc43 S_BRANCH %bb.444 45 bb.2:46 %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec47 %2:sreg_64_xexec = V_CMP_NE_U32_e64 1, %1, implicit $exec48 $vcc = S_AND_B64 $exec, %2, implicit-def $scc49 S_CBRANCH_VCCNZ %bb.4, implicit $vcc50 S_BRANCH %bb.351 52 bb.3:53 S_BRANCH %bb.454 55 bb.4:56...57 58---59name: cndmask_separate_block60tracksRegLiveness: true61body: |62 ; CHECK-LABEL: name: cndmask_separate_block63 ; CHECK: bb.0:64 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)65 ; CHECK-NEXT: {{ $}}66 ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF67 ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit undef $vcc68 ; CHECK-NEXT: {{ $}}69 ; CHECK-NEXT: bb.1:70 ; CHECK-NEXT: successors: %bb.4(0x80000000)71 ; CHECK-NEXT: {{ $}}72 ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.4, implicit undef $vcc73 ; CHECK-NEXT: S_BRANCH %bb.474 ; CHECK-NEXT: {{ $}}75 ; CHECK-NEXT: bb.2:76 ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.3(0x40000000)77 ; CHECK-NEXT: {{ $}}78 ; CHECK-NEXT: $vcc = S_ANDN2_B64 $exec, [[DEF]], implicit-def $scc79 ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.4, implicit $vcc80 ; CHECK-NEXT: S_BRANCH %bb.381 ; CHECK-NEXT: {{ $}}82 ; CHECK-NEXT: bb.3:83 ; CHECK-NEXT: successors: %bb.4(0x80000000)84 ; CHECK-NEXT: {{ $}}85 ; CHECK-NEXT: S_BRANCH %bb.486 ; CHECK-NEXT: {{ $}}87 ; CHECK-NEXT: bb.4:88 bb.0:89 %0:sreg_64_xexec = IMPLICIT_DEF90 %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec91 S_CBRANCH_VCCNZ %bb.2, implicit undef $vcc92 93 bb.1:94 S_CBRANCH_VCCNZ %bb.4, implicit undef $vcc95 S_BRANCH %bb.496 97 bb.2:98 %2:sreg_64_xexec = V_CMP_NE_U32_e64 1, %1, implicit $exec99 $vcc = S_AND_B64 $exec, %2, implicit-def $scc100 S_CBRANCH_VCCNZ %bb.4, implicit $vcc101 S_BRANCH %bb.3102 103 bb.3:104 S_BRANCH %bb.4105 106 bb.4:107...108 109---110name: cndmask_same_block_other_cmpreg_use111tracksRegLiveness: true112body: |113 ; CHECK-LABEL: name: cndmask_same_block_other_cmpreg_use114 ; CHECK: bb.0:115 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)116 ; CHECK-NEXT: {{ $}}117 ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF118 ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit undef $vcc119 ; CHECK-NEXT: {{ $}}120 ; CHECK-NEXT: bb.1:121 ; CHECK-NEXT: successors: %bb.4(0x80000000)122 ; CHECK-NEXT: {{ $}}123 ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.4, implicit undef $vcc124 ; CHECK-NEXT: S_BRANCH %bb.4125 ; CHECK-NEXT: {{ $}}126 ; CHECK-NEXT: bb.2:127 ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.3(0x40000000)128 ; CHECK-NEXT: {{ $}}129 ; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[DEF]], implicit $exec130 ; CHECK-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 1, [[V_CNDMASK_B32_e64_]], implicit $exec131 ; CHECK-NEXT: $vcc = S_ANDN2_B64 $exec, [[DEF]], implicit-def $scc132 ; CHECK-NEXT: S_NOP 0, implicit [[V_CMP_NE_U32_e64_]]133 ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.4, implicit $vcc134 ; CHECK-NEXT: S_BRANCH %bb.3135 ; CHECK-NEXT: {{ $}}136 ; CHECK-NEXT: bb.3:137 ; CHECK-NEXT: successors: %bb.4(0x80000000)138 ; CHECK-NEXT: {{ $}}139 ; CHECK-NEXT: S_BRANCH %bb.4140 ; CHECK-NEXT: {{ $}}141 ; CHECK-NEXT: bb.4:142 bb.0:143 %0:sreg_64_xexec = IMPLICIT_DEF144 S_CBRANCH_VCCNZ %bb.2, implicit undef $vcc145 146 bb.1:147 S_CBRANCH_VCCNZ %bb.4, implicit undef $vcc148 S_BRANCH %bb.4149 150 bb.2:151 %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec152 %2:sreg_64_xexec = V_CMP_NE_U32_e64 1, %1, implicit $exec153 S_NOP 0, implicit %2154 $vcc = S_AND_B64 $exec, %2, implicit-def $scc155 S_CBRANCH_VCCNZ %bb.4, implicit $vcc156 S_BRANCH %bb.3157 158 bb.3:159 S_BRANCH %bb.4160 161 bb.4:162...163 164---165name: cndmask_same_block_liveout_use166tracksRegLiveness: true167body: |168 ; CHECK-LABEL: name: cndmask_same_block_liveout_use169 ; CHECK: bb.0:170 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)171 ; CHECK-NEXT: {{ $}}172 ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF173 ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit undef $vcc174 ; CHECK-NEXT: {{ $}}175 ; CHECK-NEXT: bb.1:176 ; CHECK-NEXT: successors: %bb.4(0x80000000)177 ; CHECK-NEXT: {{ $}}178 ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.4, implicit undef $vcc179 ; CHECK-NEXT: S_BRANCH %bb.4180 ; CHECK-NEXT: {{ $}}181 ; CHECK-NEXT: bb.2:182 ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.3(0x40000000)183 ; CHECK-NEXT: {{ $}}184 ; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[DEF]], implicit $exec185 ; CHECK-NEXT: $vcc = S_ANDN2_B64 $exec, [[DEF]], implicit-def $scc186 ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.4, implicit $vcc187 ; CHECK-NEXT: S_BRANCH %bb.3188 ; CHECK-NEXT: {{ $}}189 ; CHECK-NEXT: bb.3:190 ; CHECK-NEXT: successors: %bb.4(0x80000000)191 ; CHECK-NEXT: {{ $}}192 ; CHECK-NEXT: S_NOP 0, implicit [[V_CNDMASK_B32_e64_]]193 ; CHECK-NEXT: S_BRANCH %bb.4194 ; CHECK-NEXT: {{ $}}195 ; CHECK-NEXT: bb.4:196 bb.0:197 %0:sreg_64_xexec = IMPLICIT_DEF198 S_CBRANCH_VCCNZ %bb.2, implicit undef $vcc199 200 bb.1:201 S_CBRANCH_VCCNZ %bb.4, implicit undef $vcc202 S_BRANCH %bb.4203 204 bb.2:205 %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec206 %2:sreg_64_xexec = V_CMP_NE_U32_e64 1, %1, implicit $exec207 $vcc = S_AND_B64 $exec, %2, implicit-def $scc208 S_CBRANCH_VCCNZ %bb.4, implicit $vcc209 S_BRANCH %bb.3210 211 bb.3:212 S_NOP 0, implicit %1213 S_BRANCH %bb.4214 215 bb.4:216...217 218# The legality check for removing the compare used to rely on219# use_nodbg_empty, which fails on the undef use of %2. We would then220# fail to update the interval correctly.221 222---223name: cmp_reg_extra_undef_use224tracksRegLiveness: true225body: |226 ; CHECK-LABEL: name: cmp_reg_extra_undef_use227 ; CHECK: bb.0:228 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)229 ; CHECK-NEXT: {{ $}}230 ; CHECK-NEXT: $vcc = S_ANDN2_B64 $exec, undef %1:sreg_64_xexec, implicit-def dead $scc231 ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc232 ; CHECK-NEXT: {{ $}}233 ; CHECK-NEXT: bb.1:234 ; CHECK-NEXT: successors: %bb.2(0x80000000)235 ; CHECK-NEXT: {{ $}}236 ; CHECK-NEXT: $vcc = S_AND_B64 $exec, undef %2:sreg_64_xexec, implicit-def dead $scc237 ; CHECK-NEXT: {{ $}}238 ; CHECK-NEXT: bb.2:239 bb.0:240 %0:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, undef %1:sreg_64_xexec, implicit $exec241 %2:sreg_64_xexec = V_CMP_NE_U32_e64 1, %0, implicit $exec242 $vcc = S_AND_B64 $exec, %2, implicit-def dead $scc243 S_CBRANCH_VCCNZ %bb.3, implicit killed $vcc244 245 bb.1:246 $vcc = S_AND_B64 $exec, undef %2, implicit-def dead $scc247 248 bb.3:249 250...251 252# use_nodbg_empty is insufficient for erasing %1's def when removing253# V_CNDMASK_B32.254 255---256name: cndmask_undef_extra_use257tracksRegLiveness: true258body: |259 ; CHECK-LABEL: name: cndmask_undef_extra_use260 ; CHECK: bb.0:261 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)262 ; CHECK-NEXT: {{ $}}263 ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF264 ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit undef $vcc265 ; CHECK-NEXT: {{ $}}266 ; CHECK-NEXT: bb.1:267 ; CHECK-NEXT: successors: %bb.4(0x80000000)268 ; CHECK-NEXT: {{ $}}269 ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.4, implicit undef $vcc270 ; CHECK-NEXT: S_BRANCH %bb.4271 ; CHECK-NEXT: {{ $}}272 ; CHECK-NEXT: bb.2:273 ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.3(0x40000000)274 ; CHECK-NEXT: {{ $}}275 ; CHECK-NEXT: dead [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[DEF]], implicit $exec276 ; CHECK-NEXT: $vcc = S_ANDN2_B64 $exec, [[DEF]], implicit-def $scc277 ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.4, implicit $vcc278 ; CHECK-NEXT: S_BRANCH %bb.3279 ; CHECK-NEXT: {{ $}}280 ; CHECK-NEXT: bb.3:281 ; CHECK-NEXT: successors: %bb.4(0x80000000)282 ; CHECK-NEXT: {{ $}}283 ; CHECK-NEXT: S_NOP 0, implicit undef [[V_CNDMASK_B32_e64_]]284 ; CHECK-NEXT: S_BRANCH %bb.4285 ; CHECK-NEXT: {{ $}}286 ; CHECK-NEXT: bb.4:287 bb.0:288 %0:sreg_64_xexec = IMPLICIT_DEF289 S_CBRANCH_VCCNZ %bb.2, implicit undef $vcc290 291 bb.1:292 S_CBRANCH_VCCNZ %bb.4, implicit undef $vcc293 S_BRANCH %bb.4294 295 bb.2:296 %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec297 %2:sreg_64_xexec = V_CMP_NE_U32_e64 1, %1, implicit $exec298 $vcc = S_AND_B64 $exec, %2, implicit-def $scc299 S_CBRANCH_VCCNZ %bb.4, implicit $vcc300 S_BRANCH %bb.3301 302 bb.3:303 S_NOP 0, implicit undef %1304 S_BRANCH %bb.4305 306 bb.4:307...308 309---310name: cndmask_is_undef311tracksRegLiveness: true312body: |313 ; CHECK-LABEL: name: cndmask_is_undef314 ; CHECK: bb.0:315 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)316 ; CHECK-NEXT: {{ $}}317 ; CHECK-NEXT: dead [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 0318 ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit undef $vcc319 ; CHECK-NEXT: {{ $}}320 ; CHECK-NEXT: bb.1:321 ; CHECK-NEXT: successors: %bb.4(0x80000000)322 ; CHECK-NEXT: {{ $}}323 ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.4, implicit undef $vcc324 ; CHECK-NEXT: S_BRANCH %bb.4325 ; CHECK-NEXT: {{ $}}326 ; CHECK-NEXT: bb.2:327 ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.3(0x40000000)328 ; CHECK-NEXT: {{ $}}329 ; CHECK-NEXT: $vcc = S_ANDN2_B64 $exec, undef [[S_MOV_B64_]], implicit-def $scc330 ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.4, implicit $vcc331 ; CHECK-NEXT: S_BRANCH %bb.3332 ; CHECK-NEXT: {{ $}}333 ; CHECK-NEXT: bb.3:334 ; CHECK-NEXT: successors: %bb.4(0x80000000)335 ; CHECK-NEXT: {{ $}}336 ; CHECK-NEXT: S_BRANCH %bb.4337 ; CHECK-NEXT: {{ $}}338 ; CHECK-NEXT: bb.4:339 bb.0:340 %0:sreg_64_xexec = S_MOV_B64 0341 S_CBRANCH_VCCNZ %bb.2, implicit undef $vcc342 343 bb.1:344 S_CBRANCH_VCCNZ %bb.4, implicit undef $vcc345 S_BRANCH %bb.4346 347 bb.2:348 %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, undef %0, implicit $exec349 %2:sreg_64_xexec = V_CMP_NE_U32_e64 1, %1, implicit $exec350 $vcc = S_AND_B64 $exec, %2, implicit-def $scc351 S_CBRANCH_VCCNZ %bb.4, implicit $vcc352 S_BRANCH %bb.3353 354 bb.3:355 S_BRANCH %bb.4356 357 bb.4:358...359 360# Liveness of V_CNDMASK_B32 source (%0) must be extended through loop.361 362---363name: cndmask_loop_cndmask364tracksRegLiveness: true365body: |366 ; CHECK-LABEL: name: cndmask_loop_cndmask367 ; CHECK: bb.0:368 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)369 ; CHECK-NEXT: {{ $}}370 ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF371 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF372 ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit undef $vcc373 ; CHECK-NEXT: {{ $}}374 ; CHECK-NEXT: bb.1:375 ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.2(0x40000000)376 ; CHECK-NEXT: {{ $}}377 ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_32 = S_ADD_I32 [[DEF]], -1, implicit-def $scc378 ; CHECK-NEXT: S_CBRANCH_SCC0 %bb.4, implicit $scc379 ; CHECK-NEXT: {{ $}}380 ; CHECK-NEXT: bb.2:381 ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.3(0x40000000)382 ; CHECK-NEXT: {{ $}}383 ; CHECK-NEXT: $vcc = S_ANDN2_B64 $exec, [[DEF1]], implicit-def $scc384 ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.4, implicit $vcc385 ; CHECK-NEXT: S_BRANCH %bb.3386 ; CHECK-NEXT: {{ $}}387 ; CHECK-NEXT: bb.3:388 ; CHECK-NEXT: successors: %bb.1(0x80000000)389 ; CHECK-NEXT: {{ $}}390 ; CHECK-NEXT: S_BRANCH %bb.1391 ; CHECK-NEXT: {{ $}}392 ; CHECK-NEXT: bb.4:393 bb.0:394 %0:sreg_64_xexec = IMPLICIT_DEF395 %1:sreg_32 = IMPLICIT_DEF396 %2:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec397 S_CBRANCH_VCCNZ %bb.2, implicit undef $vcc398 399 bb.1:400 %1:sreg_32 = S_ADD_I32 %1, -1, implicit-def $scc401 S_CBRANCH_SCC0 %bb.4, implicit $scc402 403 bb.2:404 %4:sreg_64_xexec = V_CMP_NE_U32_e64 1, %2, implicit $exec405 $vcc = S_AND_B64 $exec, %4, implicit-def $scc406 S_CBRANCH_VCCNZ %bb.4, implicit $vcc407 S_BRANCH %bb.3408 409 bb.3:410 S_BRANCH %bb.1411 412 bb.4:413...414 415---416name: cndmask_loop_cndmask_split417tracksRegLiveness: true418body: |419 ; CHECK-LABEL: name: cndmask_loop_cndmask_split420 ; CHECK: bb.0:421 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)422 ; CHECK-NEXT: {{ $}}423 ; CHECK-NEXT: $vcc = IMPLICIT_DEF424 ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF425 ; CHECK-NEXT: [[DEF1:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF426 ; CHECK-NEXT: S_CBRANCH_VCCZ %bb.1, implicit $vcc427 ; CHECK-NEXT: S_BRANCH %bb.2428 ; CHECK-NEXT: {{ $}}429 ; CHECK-NEXT: bb.1:430 ; CHECK-NEXT: successors: %bb.5(0x80000000)431 ; CHECK-NEXT: {{ $}}432 ; CHECK-NEXT: S_BRANCH %bb.5433 ; CHECK-NEXT: {{ $}}434 ; CHECK-NEXT: bb.2:435 ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.3(0x40000000)436 ; CHECK-NEXT: {{ $}}437 ; CHECK-NEXT: $vcc = S_ANDN2_B64 $exec, [[DEF1]], implicit-def $scc438 ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.4, implicit $vcc439 ; CHECK-NEXT: {{ $}}440 ; CHECK-NEXT: bb.3:441 ; CHECK-NEXT: successors: %bb.5(0x40000000), %bb.4(0x40000000)442 ; CHECK-NEXT: {{ $}}443 ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_32 = S_ADD_I32 [[DEF]], -1, implicit-def $scc444 ; CHECK-NEXT: S_CBRANCH_SCC0 %bb.5, implicit $scc445 ; CHECK-NEXT: {{ $}}446 ; CHECK-NEXT: bb.4:447 ; CHECK-NEXT: successors: %bb.2(0x80000000)448 ; CHECK-NEXT: {{ $}}449 ; CHECK-NEXT: S_BRANCH %bb.2450 ; CHECK-NEXT: {{ $}}451 ; CHECK-NEXT: bb.5:452 bb.0:453 $vcc = IMPLICIT_DEF454 %0:sreg_64_xexec = IMPLICIT_DEF455 %1:sreg_32 = IMPLICIT_DEF456 %2:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec457 S_CBRANCH_VCCZ %bb.5, implicit $vcc458 S_BRANCH %bb.1459 460 bb.5:461 S_BRANCH %bb.4462 463 bb.1:464 %4:sreg_64_xexec = V_CMP_NE_U32_e64 1, %2, implicit $exec465 $vcc = S_AND_B64 $exec, %4, implicit-def $scc466 S_CBRANCH_VCCNZ %bb.3, implicit $vcc467 468 bb.2:469 %1:sreg_32 = S_ADD_I32 %1, -1, implicit-def $scc470 S_CBRANCH_SCC0 %bb.4, implicit $scc471 472 bb.3:473 S_BRANCH %bb.1474 475 bb.4:476...477 478# We would need to extend the live range of %0 to be live out of %bb.2479 480---481name: register_not_marked_liveout482tracksRegLiveness: true483machineFunctionInfo:484 isEntryFunction: true485 scratchRSrcReg: '$sgpr0_sgpr1_sgpr2_sgpr3'486 stackPtrOffsetReg: '$sgpr32'487 returnsVoid: true488body: |489 ; CHECK-LABEL: name: register_not_marked_liveout490 ; CHECK: bb.0:491 ; CHECK-NEXT: successors: %bb.1(0x80000000)492 ; CHECK-NEXT: liveins: $vgpr0, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr14, $sgpr15, $sgpr16493 ; CHECK-NEXT: {{ $}}494 ; CHECK-NEXT: [[S_MOV_B64_:%[0-9]+]]:sreg_64_xexec = S_MOV_B64 0495 ; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[S_MOV_B64_]], implicit $exec496 ; CHECK-NEXT: [[V_CMP_GT_I32_e64_:%[0-9]+]]:sreg_64 = V_CMP_GT_I32_e64 0, [[V_CNDMASK_B32_e64_]], implicit $exec497 ; CHECK-NEXT: $exec = S_MOV_B64_term [[V_CMP_GT_I32_e64_]]498 ; CHECK-NEXT: {{ $}}499 ; CHECK-NEXT: bb.1:500 ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)501 ; CHECK-NEXT: {{ $}}502 ; CHECK-NEXT: $exec = S_MOV_B64_term [[V_CMP_GT_I32_e64_]]503 ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.3, implicit $exec504 ; CHECK-NEXT: {{ $}}505 ; CHECK-NEXT: bb.2:506 ; CHECK-NEXT: successors: %bb.1(0x40000000), %bb.3(0x40000000)507 ; CHECK-NEXT: {{ $}}508 ; CHECK-NEXT: $vcc = S_ANDN2_B64 $exec, [[S_MOV_B64_]], implicit-def dead $scc509 ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.1, implicit $vcc510 ; CHECK-NEXT: {{ $}}511 ; CHECK-NEXT: bb.3:512 bb.0:513 liveins: $vgpr0, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr14, $sgpr15, $sgpr16514 515 %0:sreg_64_xexec = S_MOV_B64 0516 %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec517 %2:sreg_64 = V_CMP_GT_I32_e64 0, %1, implicit $exec518 $exec = S_MOV_B64_term %2519 520 bb.1:521 $exec = S_MOV_B64_term %2522 S_CBRANCH_EXECZ %bb.3, implicit $exec523 524 bb.2:525 %3:sreg_64_xexec = V_CMP_NE_U32_e64 1, %1, implicit $exec526 $vcc = S_AND_B64 $exec, %3, implicit-def dead $scc527 S_CBRANCH_VCCNZ %bb.1, implicit killed $vcc528 529 bb.3:530 531...532 533# Can't delete V_CNDMASK_B32 when folding into the use in %bb.3 since534# it's also used in %bb.0535---536name: cndmask_multiple_uses537tracksRegLiveness: true538body: |539 ; CHECK-LABEL: name: cndmask_multiple_uses540 ; CHECK: bb.0:541 ; CHECK-NEXT: successors: %bb.1(0x80000000)542 ; CHECK-NEXT: liveins: $vgpr0, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr14, $sgpr15, $sgpr16543 ; CHECK-NEXT: {{ $}}544 ; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, undef %1:sreg_64_xexec, implicit $exec545 ; CHECK-NEXT: [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_64_xexec = V_CMP_NE_U32_e64 1, [[V_CNDMASK_B32_e64_]], implicit $exec546 ; CHECK-NEXT: {{ $}}547 ; CHECK-NEXT: bb.1:548 ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)549 ; CHECK-NEXT: {{ $}}550 ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.3, implicit undef $vcc551 ; CHECK-NEXT: {{ $}}552 ; CHECK-NEXT: bb.2:553 ; CHECK-NEXT: successors: %bb.5(0x40000000), %bb.3(0x40000000)554 ; CHECK-NEXT: {{ $}}555 ; CHECK-NEXT: $vcc = S_AND_B64 $exec, [[V_CMP_NE_U32_e64_]], implicit-def dead $scc556 ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.5, implicit $vcc557 ; CHECK-NEXT: {{ $}}558 ; CHECK-NEXT: bb.3:559 ; CHECK-NEXT: successors: %bb.5(0x40000000), %bb.4(0x40000000)560 ; CHECK-NEXT: {{ $}}561 ; CHECK-NEXT: $vcc = S_ANDN2_B64 $exec, undef %1:sreg_64_xexec, implicit-def dead $scc562 ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.5, implicit $vcc563 ; CHECK-NEXT: {{ $}}564 ; CHECK-NEXT: bb.4:565 ; CHECK-NEXT: successors: %bb.5(0x80000000)566 ; CHECK-NEXT: {{ $}}567 ; CHECK-NEXT: bb.5:568 bb.0:569 liveins: $vgpr0, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr14, $sgpr15, $sgpr16570 571 %0:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, undef %1:sreg_64_xexec, implicit $exec572 %2:sreg_64_xexec = V_CMP_NE_U32_e64 1, %0, implicit $exec573 574 bb.1:575 S_CBRANCH_VCCNZ %bb.3, implicit undef $vcc576 577 bb.2:578 $vcc = S_AND_B64 $exec, %2, implicit-def dead $scc579 S_CBRANCH_VCCNZ %bb.6, implicit killed $vcc580 581 bb.3:582 %3:sreg_64_xexec = V_CMP_NE_U32_e64 1, %0, implicit $exec583 $vcc = S_AND_B64 $exec, %3, implicit-def dead $scc584 S_CBRANCH_VCCNZ %bb.6, implicit killed $vcc585 586 bb.5:587 588 bb.6:589 590...591 592# The live segment of %1 from V_CMP_GT_I32 needs to be shrunk after the use in %bb.1 is deleted593---594name: leftover_use_of_selreg_extends_liverange595tracksRegLiveness: true596body: |597 ; CHECK-LABEL: name: leftover_use_of_selreg_extends_liverange598 ; CHECK: bb.0:599 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)600 ; CHECK-NEXT: liveins: $vgpr0, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr14, $sgpr15, $sgpr16601 ; CHECK-NEXT: {{ $}}602 ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF603 ; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[DEF]], implicit $exec604 ; CHECK-NEXT: [[V_CMP_GT_I32_e64_:%[0-9]+]]:sreg_64 = V_CMP_GT_I32_e64 0, [[V_CNDMASK_B32_e64_]], implicit $exec605 ; CHECK-NEXT: $exec = S_MOV_B64_term [[V_CMP_GT_I32_e64_]]606 ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec607 ; CHECK-NEXT: {{ $}}608 ; CHECK-NEXT: bb.1:609 ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)610 ; CHECK-NEXT: {{ $}}611 ; CHECK-NEXT: $vcc = S_ANDN2_B64 $exec, [[DEF]], implicit-def dead $scc612 ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.3, implicit $vcc613 ; CHECK-NEXT: {{ $}}614 ; CHECK-NEXT: bb.2:615 ; CHECK-NEXT: successors: %bb.3(0x80000000)616 ; CHECK-NEXT: {{ $}}617 ; CHECK-NEXT: bb.3:618 bb.0:619 liveins: $vgpr0, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr14, $sgpr15, $sgpr16620 621 %0:sreg_64_xexec = IMPLICIT_DEF622 %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec623 %2:sreg_64 = V_CMP_GT_I32_e64 0, %1, implicit $exec624 $exec = S_MOV_B64_term %2625 S_CBRANCH_EXECZ %bb.2, implicit $exec626 627 bb.1:628 %3:sreg_64_xexec = V_CMP_NE_U32_e64 1, %1, implicit $exec629 $vcc = S_AND_B64 $exec, %3, implicit-def dead $scc630 S_CBRANCH_VCCNZ %bb.3, implicit killed $vcc631 632 bb.2:633 634 bb.3:635 636...637 638---639name: leftover_use_of_selreg_extends_liverange_subrange640tracksRegLiveness: true641body: |642 ; CHECK-LABEL: name: leftover_use_of_selreg_extends_liverange_subrange643 ; CHECK: bb.0:644 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)645 ; CHECK-NEXT: liveins: $vgpr0, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr14, $sgpr15, $sgpr16646 ; CHECK-NEXT: {{ $}}647 ; CHECK-NEXT: [[DEF:%[0-9]+]]:sreg_64_xexec = IMPLICIT_DEF648 ; CHECK-NEXT: undef [[V_CNDMASK_B32_e64_:%[0-9]+]].sub1:vreg_64 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[DEF]], implicit $exec649 ; CHECK-NEXT: [[V_CMP_GT_I32_e64_:%[0-9]+]]:sreg_64 = V_CMP_GT_I32_e64 0, [[V_CNDMASK_B32_e64_]].sub1, implicit $exec650 ; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]].sub0:vreg_64 = V_MOV_B32_e32 123, implicit $exec651 ; CHECK-NEXT: $exec = S_MOV_B64_term [[V_CMP_GT_I32_e64_]]652 ; CHECK-NEXT: S_CBRANCH_EXECZ %bb.2, implicit $exec653 ; CHECK-NEXT: {{ $}}654 ; CHECK-NEXT: bb.1:655 ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)656 ; CHECK-NEXT: {{ $}}657 ; CHECK-NEXT: $vcc = S_ANDN2_B64 $exec, [[DEF]], implicit-def dead $scc658 ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.3, implicit $vcc659 ; CHECK-NEXT: {{ $}}660 ; CHECK-NEXT: bb.2:661 ; CHECK-NEXT: successors: %bb.3(0x80000000)662 ; CHECK-NEXT: {{ $}}663 ; CHECK-NEXT: S_NOP 0, implicit [[V_CNDMASK_B32_e64_]].sub0664 ; CHECK-NEXT: {{ $}}665 ; CHECK-NEXT: bb.3:666 bb.0:667 liveins: $vgpr0, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8_sgpr9, $sgpr10_sgpr11, $sgpr14, $sgpr15, $sgpr16668 669 %0:sreg_64_xexec = IMPLICIT_DEF670 undef %1.sub1:vreg_64 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec671 %1.sub0 = V_MOV_B32_e32 123, implicit $exec672 %2:sreg_64 = V_CMP_GT_I32_e64 0, %1.sub1, implicit $exec673 $exec = S_MOV_B64_term %2674 S_CBRANCH_EXECZ %bb.2, implicit $exec675 676 bb.1:677 %3:sreg_64_xexec = V_CMP_NE_U32_e64 1, %1.sub1, implicit $exec678 $vcc = S_AND_B64 $exec, %3, implicit-def dead $scc679 S_CBRANCH_VCCNZ %bb.3, implicit killed $vcc680 681 bb.2:682 S_NOP 0, implicit %1.sub0683 684 bb.3:685 686...687 688# This was trying to extend the liverange of %0 farther than needed,689# following %1's segment to %bb3690 691---692name: cannot_create_empty_or_backwards_segment693tracksRegLiveness: true694body: |695 ; CHECK-LABEL: name: cannot_create_empty_or_backwards_segment696 ; CHECK: bb.0:697 ; CHECK-NEXT: successors: %bb.2(0x40000000), %bb.1(0x40000000)698 ; CHECK-NEXT: liveins: $sgpr4_sgpr5699 ; CHECK-NEXT: {{ $}}700 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr4_sgpr5701 ; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[COPY]], implicit $exec702 ; CHECK-NEXT: $vcc = S_ANDN2_B64 $exec, [[COPY]], implicit-def dead $scc703 ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc704 ; CHECK-NEXT: {{ $}}705 ; CHECK-NEXT: bb.1:706 ; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)707 ; CHECK-NEXT: {{ $}}708 ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.3, implicit undef $vcc709 ; CHECK-NEXT: {{ $}}710 ; CHECK-NEXT: bb.2:711 ; CHECK-NEXT: S_ENDPGM 0712 ; CHECK-NEXT: {{ $}}713 ; CHECK-NEXT: bb.3:714 ; CHECK-NEXT: S_ENDPGM 0, implicit [[V_CNDMASK_B32_e64_]]715 bb.0:716 liveins: $sgpr4_sgpr5717 718 %0:sreg_64_xexec = COPY $sgpr4_sgpr5719 %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec720 %2:sreg_64_xexec = V_CMP_NE_U32_e64 1, %1, implicit $exec721 $vcc = S_AND_B64 $exec, %2, implicit-def dead $scc722 S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc723 724 bb.1:725 S_CBRANCH_VCCNZ %bb.3, implicit killed undef $vcc726 727 bb.2:728 S_ENDPGM 0729 730 bb.3:731 S_ENDPGM 0, implicit %1732...733 734---735name: cannot_create_empty_or_backwards_segment_2736tracksRegLiveness: true737body: |738 ; CHECK-LABEL: name: cannot_create_empty_or_backwards_segment_2739 ; CHECK: bb.0:740 ; CHECK-NEXT: successors: %bb.1(0x80000000)741 ; CHECK-NEXT: liveins: $sgpr4_sgpr5742 ; CHECK-NEXT: {{ $}}743 ; CHECK-NEXT: bb.1:744 ; CHECK-NEXT: successors: %bb.2(0x80000000)745 ; CHECK-NEXT: liveins: $sgpr4_sgpr5746 ; CHECK-NEXT: {{ $}}747 ; CHECK-NEXT: [[COPY:%[0-9]+]]:sreg_64_xexec = COPY $sgpr4_sgpr5748 ; CHECK-NEXT: [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[COPY]], implicit $exec749 ; CHECK-NEXT: $vcc = S_ANDN2_B64 $exec, [[COPY]], implicit-def dead $scc750 ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.2, implicit $vcc751 ; CHECK-NEXT: {{ $}}752 ; CHECK-NEXT: bb.2:753 ; CHECK-NEXT: successors: %bb.4(0x40000000), %bb.1(0x40000000)754 ; CHECK-NEXT: liveins: $sgpr4_sgpr5755 ; CHECK-NEXT: {{ $}}756 ; CHECK-NEXT: S_NOP 0, implicit-def dead [[V_CNDMASK_B32_e64_]], implicit [[V_CNDMASK_B32_e64_]]757 ; CHECK-NEXT: S_CBRANCH_VCCNZ %bb.4, implicit undef $vcc758 ; CHECK-NEXT: S_BRANCH %bb.1759 ; CHECK-NEXT: {{ $}}760 ; CHECK-NEXT: bb.3:761 ; CHECK-NEXT: S_ENDPGM 0762 ; CHECK-NEXT: {{ $}}763 ; CHECK-NEXT: bb.4:764 ; CHECK-NEXT: S_ENDPGM 0765 bb.0:766 liveins: $sgpr4_sgpr5767 768 bb.1:769 liveins: $sgpr4_sgpr5770 771 %0:sreg_64_xexec = COPY $sgpr4_sgpr5772 %1:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %0, implicit $exec773 %2:sreg_64_xexec = V_CMP_NE_U32_e64 1, %1, implicit $exec774 $vcc = S_AND_B64 $exec, %2, implicit-def dead $scc775 S_CBRANCH_VCCNZ %bb.2, implicit killed $vcc776 777 bb.2:778 liveins: $sgpr4_sgpr5779 S_NOP 0, implicit-def %1, implicit %1780 S_CBRANCH_VCCNZ %bb.4, implicit killed undef $vcc781 S_BRANCH %bb.1782 783 bb.3:784 S_ENDPGM 0785 786 bb.4:787 S_ENDPGM 0788...789