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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple=amdgcn -run-pass si-fix-sgpr-copies,si-fold-operands,dead-mi-elimination -verify-machineinstrs -o - %s | FileCheck -check-prefix=GCN %s3 4# Check that constant is in SGPR registers5 6--- |7 define amdgpu_kernel void @const_to_sgpr(ptr addrspace(1) nocapture %arg, i64 %id) {8 bb:9 br i1 poison, label %bb1, label %bb210 11 bb1: ; preds = %bb12 br label %bb213 14 bb2: ; preds = %bb1, %bb15 ret void16 }17 18 define amdgpu_kernel void @const_to_sgpr_multiple_use(ptr addrspace(1) nocapture %arg, i64 %id1, i64 %id2) {19 bb:20 br i1 poison, label %bb1, label %bb221 22 bb1: ; preds = %bb23 br label %bb224 25 bb2: ; preds = %bb1, %bb26 ret void27 }28 29 define amdgpu_kernel void @const_to_sgpr_subreg(ptr addrspace(1) nocapture %arg, i64 %id) {30 bb:31 br i1 poison, label %bb1, label %bb232 33 bb1: ; preds = %bb34 br label %bb235 36 bb2: ; preds = %bb1, %bb37 ret void38 }39 40...41---42name: const_to_sgpr43alignment: 144exposesReturnsTwice: false45legalized: false46regBankSelected: false47selected: false48tracksRegLiveness: true49registers:50 - { id: 0, class: sreg_64 }51 - { id: 1, class: sreg_64 }52 - { id: 2, class: vgpr_32 }53 - { id: 3, class: sgpr_64 }54 - { id: 4, class: sreg_32_xm0 }55 - { id: 5, class: sgpr_32 }56 - { id: 6, class: sreg_64 }57 - { id: 7, class: sreg_64_xexec }58 - { id: 8, class: sreg_64_xexec }59 - { id: 9, class: sreg_32 }60 - { id: 10, class: sreg_64 }61 - { id: 11, class: sreg_32_xm0 }62 - { id: 12, class: sreg_32_xm0 }63 - { id: 13, class: sreg_32_xm0 }64 - { id: 14, class: sreg_32_xm0 }65 - { id: 15, class: sreg_32_xm0 }66 - { id: 16, class: sreg_32_xm0 }67 - { id: 17, class: sreg_64 }68 - { id: 18, class: sreg_32_xm0 }69 - { id: 19, class: sreg_32_xm0 }70 - { id: 20, class: sreg_64 }71 - { id: 21, class: sreg_64 }72 - { id: 22, class: vreg_64 }73 - { id: 23, class: sreg_32_xm0 }74 - { id: 24, class: sreg_64 }75 - { id: 25, class: sreg_32_xm0 }76 - { id: 26, class: sreg_32_xm0 }77 - { id: 27, class: sgpr_64 }78 - { id: 28, class: sgpr_128 }79 - { id: 29, class: vgpr_32 }80 - { id: 30, class: vreg_64 }81liveins:82 - { reg: '$vgpr0', virtual-reg: '%2' }83 - { reg: '$sgpr0_sgpr1', virtual-reg: '%3' }84body: |85 ; GCN-LABEL: name: const_to_sgpr86 ; GCN: bb.0.bb:87 ; GCN-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)88 ; GCN-NEXT: liveins: $vgpr0, $sgpr0_sgpr189 ; GCN-NEXT: {{ $}}90 ; GCN-NEXT: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr0_sgpr191 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr092 ; GCN-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]], 9, 093 ; GCN-NEXT: [[S_LOAD_DWORDX2_IMM1:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]], 11, 094 ; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_64 = COPY [[S_LOAD_DWORDX2_IMM]]95 ; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec96 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, killed [[V_MOV_B32_e32_]], %subreg.sub197 ; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_LOAD_DWORDX2_IMM1]].sub0, [[REG_SEQUENCE]].sub0, implicit-def $vcc, implicit $exec98 ; GCN-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[S_LOAD_DWORDX2_IMM1]].sub199 ; GCN-NEXT: [[V_ADDC_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADDC_U32_e32 0, [[COPY3]], implicit-def $vcc, implicit $vcc, implicit $exec100 ; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE killed [[V_ADD_CO_U32_e32_]], %subreg.sub0, killed [[V_ADDC_U32_e32_]], %subreg.sub1101 ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 0102 ; GCN-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 1048576103 ; GCN-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sreg_64 = REG_SEQUENCE killed [[S_MOV_B32_1]], %subreg.sub0, killed [[S_MOV_B32_]], %subreg.sub1104 ; GCN-NEXT: [[V_CMP_LT_U64_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_U64_e64 killed [[REG_SEQUENCE1]], [[REG_SEQUENCE2]], implicit $exec105 ; GCN-NEXT: [[SI_IF:%[0-9]+]]:sreg_64 = SI_IF killed [[V_CMP_LT_U64_e64_]], %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec106 ; GCN-NEXT: S_BRANCH %bb.1107 ; GCN-NEXT: {{ $}}108 ; GCN-NEXT: bb.1.bb1:109 ; GCN-NEXT: successors: %bb.2(0x80000000)110 ; GCN-NEXT: {{ $}}111 ; GCN-NEXT: [[V_LSHL_B64_e64_:%[0-9]+]]:vreg_64 = V_LSHL_B64_e64 [[REG_SEQUENCE]], 2, implicit $exec112 ; GCN-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 61440113 ; GCN-NEXT: [[S_MOV_B32_3:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 0114 ; GCN-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_64 = REG_SEQUENCE killed [[S_MOV_B32_3]], %subreg.sub0, killed [[S_MOV_B32_2]], %subreg.sub1115 ; GCN-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub1_sub2_sub3_sub4_sub5, killed [[REG_SEQUENCE3]], %subreg.sub1_sub2_sub3_sub4_sub5_sub6116 ; GCN-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec117 ; GCN-NEXT: BUFFER_STORE_DWORD_ADDR64 killed [[V_MOV_B32_e32_1]], [[V_LSHL_B64_e64_]], killed [[REG_SEQUENCE4]], 0, 0, 0, 0, implicit $exec118 ; GCN-NEXT: {{ $}}119 ; GCN-NEXT: bb.2.bb2:120 ; GCN-NEXT: SI_END_CF [[SI_IF]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec121 ; GCN-NEXT: S_ENDPGM 0122 bb.0.bb:123 successors: %bb.1.bb1(0x40000000), %bb.2.bb2(0x40000000)124 liveins: $vgpr0, $sgpr0_sgpr1125 126 %3 = COPY $sgpr0_sgpr1127 %2 = COPY $vgpr0128 %7 = S_LOAD_DWORDX2_IMM %3, 9, 0129 %8 = S_LOAD_DWORDX2_IMM %3, 11, 0130 %6 = COPY %7131 %9 = S_MOV_B32 0132 %10 = REG_SEQUENCE %2, %subreg.sub0, killed %9, %subreg.sub1133 %0 = COPY %10134 %11 = COPY %10.sub0135 %12 = COPY %10.sub1136 %13 = COPY %8.sub0137 %14 = COPY %8.sub1138 %15 = S_ADD_U32 killed %11, killed %13, implicit-def $scc139 %16 = S_ADDC_U32 killed %12, killed %14, implicit-def dead $scc, implicit $scc140 %17 = REG_SEQUENCE killed %15, %subreg.sub0, killed %16, %subreg.sub1141 %18 = S_MOV_B32 0142 %19 = S_MOV_B32 1048576143 %20 = REG_SEQUENCE killed %19, %subreg.sub0, killed %18, %subreg.sub1144 %22 = COPY killed %20145 %21 = V_CMP_LT_U64_e64 killed %17, %22, implicit $exec146 %1 = SI_IF killed %21, %bb.2.bb2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec147 S_BRANCH %bb.1.bb1148 149 bb.1.bb1:150 successors: %bb.2.bb2(0x80000000)151 152 %23 = S_MOV_B32 2153 %24 = S_LSHL_B64 %0, killed %23, implicit-def dead $scc154 %25 = S_MOV_B32 61440155 %26 = S_MOV_B32 0156 %27 = REG_SEQUENCE killed %26, %subreg.sub0, killed %25, %subreg.sub1157 %28 = REG_SEQUENCE %6, 17, killed %27, 18158 %29 = V_MOV_B32_e32 0, implicit $exec159 %30 = COPY %24160 BUFFER_STORE_DWORD_ADDR64 killed %29, killed %30, killed %28, 0, 0, 0, 0, implicit $exec161 162 bb.2.bb2:163 SI_END_CF %1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec164 S_ENDPGM 0165 166...167---168name: const_to_sgpr_multiple_use169alignment: 1170exposesReturnsTwice: false171legalized: false172regBankSelected: false173selected: false174tracksRegLiveness: true175registers:176 - { id: 0, class: sreg_64 }177 - { id: 1, class: sreg_64 }178 - { id: 2, class: vgpr_32 }179 - { id: 3, class: sgpr_64 }180 - { id: 4, class: sreg_32_xm0 }181 - { id: 5, class: sgpr_32 }182 - { id: 6, class: sreg_64 }183 - { id: 7, class: sreg_64_xexec }184 - { id: 8, class: sreg_64_xexec }185 - { id: 9, class: sreg_64_xexec }186 - { id: 10, class: sreg_32 }187 - { id: 11, class: sreg_64 }188 - { id: 12, class: sreg_32_xm0 }189 - { id: 13, class: sreg_32_xm0 }190 - { id: 14, class: sreg_32_xm0 }191 - { id: 15, class: sreg_32_xm0 }192 - { id: 16, class: sreg_32_xm0 }193 - { id: 17, class: sreg_32_xm0 }194 - { id: 18, class: sreg_64 }195 - { id: 19, class: sreg_32_xm0 }196 - { id: 20, class: sreg_32_xm0 }197 - { id: 21, class: sreg_32_xm0 }198 - { id: 22, class: sreg_32_xm0 }199 - { id: 23, class: sreg_64 }200 - { id: 24, class: sreg_32_xm0 }201 - { id: 25, class: sreg_32_xm0 }202 - { id: 26, class: sreg_64 }203 - { id: 27, class: sreg_64 }204 - { id: 28, class: vreg_64 }205 - { id: 29, class: sreg_64 }206 - { id: 30, class: vreg_64 }207 - { id: 31, class: sreg_64 }208 - { id: 32, class: sreg_32_xm0 }209 - { id: 33, class: sreg_64 }210 - { id: 34, class: sreg_32_xm0 }211 - { id: 35, class: sreg_32_xm0 }212 - { id: 36, class: sgpr_64 }213 - { id: 37, class: sgpr_128 }214 - { id: 38, class: vgpr_32 }215 - { id: 39, class: vreg_64 }216liveins:217 - { reg: '$vgpr0', virtual-reg: '%2' }218 - { reg: '$sgpr0_sgpr1', virtual-reg: '%3' }219body: |220 ; GCN-LABEL: name: const_to_sgpr_multiple_use221 ; GCN: bb.0.bb:222 ; GCN-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)223 ; GCN-NEXT: liveins: $vgpr0, $sgpr0_sgpr1224 ; GCN-NEXT: {{ $}}225 ; GCN-NEXT: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr0_sgpr1226 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0227 ; GCN-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]], 9, 0228 ; GCN-NEXT: [[S_LOAD_DWORDX2_IMM1:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]], 11, 0229 ; GCN-NEXT: [[S_LOAD_DWORDX2_IMM2:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]], 13, 0230 ; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_64 = COPY [[S_LOAD_DWORDX2_IMM]]231 ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0232 ; GCN-NEXT: [[V_READFIRSTLANE_B32_:%[0-9]+]]:sgpr_32 = V_READFIRSTLANE_B32 [[COPY1]], implicit $exec233 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[V_READFIRSTLANE_B32_]], %subreg.sub0, killed [[S_MOV_B32_]], %subreg.sub1234 ; GCN-NEXT: [[S_ADD_U32_:%[0-9]+]]:sreg_32_xm0 = S_ADD_U32 [[REG_SEQUENCE]].sub0, [[S_LOAD_DWORDX2_IMM1]].sub0, implicit-def $scc235 ; GCN-NEXT: [[S_ADDC_U32_:%[0-9]+]]:sreg_32_xm0 = S_ADDC_U32 0, [[S_LOAD_DWORDX2_IMM1]].sub1, implicit-def dead $scc, implicit $scc236 ; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:sreg_64 = REG_SEQUENCE killed [[S_ADD_U32_]], %subreg.sub0, killed [[S_ADDC_U32_]], %subreg.sub1237 ; GCN-NEXT: [[S_ADD_U32_1:%[0-9]+]]:sreg_32_xm0 = S_ADD_U32 [[REG_SEQUENCE]].sub0, [[S_LOAD_DWORDX2_IMM2]].sub0, implicit-def $scc238 ; GCN-NEXT: [[S_ADDC_U32_1:%[0-9]+]]:sreg_32_xm0 = S_ADDC_U32 0, [[S_LOAD_DWORDX2_IMM2]].sub1, implicit-def dead $scc, implicit $scc239 ; GCN-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sreg_64 = REG_SEQUENCE killed [[S_ADD_U32_1]], %subreg.sub0, killed [[S_ADDC_U32_1]], %subreg.sub1240 ; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1048576, implicit $exec241 ; GCN-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec242 ; GCN-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:vreg_64 = REG_SEQUENCE killed [[V_MOV_B32_e32_]], %subreg.sub0, killed [[V_MOV_B32_e32_1]], %subreg.sub1243 ; GCN-NEXT: [[V_CMP_LT_U64_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_U64_e64 killed [[REG_SEQUENCE1]], [[REG_SEQUENCE3]], implicit $exec244 ; GCN-NEXT: [[V_CMP_LT_U64_e64_1:%[0-9]+]]:sreg_64 = V_CMP_LT_U64_e64 killed [[REG_SEQUENCE2]], [[REG_SEQUENCE3]], implicit $exec245 ; GCN-NEXT: [[S_AND_B64_:%[0-9]+]]:sreg_64 = S_AND_B64 killed [[V_CMP_LT_U64_e64_]], killed [[V_CMP_LT_U64_e64_1]], implicit-def dead $scc246 ; GCN-NEXT: [[SI_IF:%[0-9]+]]:sreg_64 = SI_IF killed [[S_AND_B64_]], %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec247 ; GCN-NEXT: S_BRANCH %bb.1248 ; GCN-NEXT: {{ $}}249 ; GCN-NEXT: bb.1.bb1:250 ; GCN-NEXT: successors: %bb.2(0x80000000)251 ; GCN-NEXT: {{ $}}252 ; GCN-NEXT: [[S_LSHL_B64_:%[0-9]+]]:sreg_64 = S_LSHL_B64 [[REG_SEQUENCE]], 2, implicit-def dead $scc253 ; GCN-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 61440254 ; GCN-NEXT: [[S_MOV_B32_2:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 0255 ; GCN-NEXT: [[REG_SEQUENCE4:%[0-9]+]]:sgpr_64 = REG_SEQUENCE killed [[S_MOV_B32_2]], %subreg.sub0, killed [[S_MOV_B32_1]], %subreg.sub1256 ; GCN-NEXT: [[REG_SEQUENCE5:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub1_sub2_sub3_sub4_sub5, killed [[REG_SEQUENCE4]], %subreg.sub1_sub2_sub3_sub4_sub5_sub6257 ; GCN-NEXT: [[V_MOV_B32_e32_2:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec258 ; GCN-NEXT: [[COPY3:%[0-9]+]]:vreg_64 = COPY [[S_LSHL_B64_]]259 ; GCN-NEXT: BUFFER_STORE_DWORD_ADDR64 killed [[V_MOV_B32_e32_2]], killed [[COPY3]], killed [[REG_SEQUENCE5]], 0, 0, 0, 0, implicit $exec260 ; GCN-NEXT: {{ $}}261 ; GCN-NEXT: bb.2.bb2:262 ; GCN-NEXT: SI_END_CF [[SI_IF]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec263 ; GCN-NEXT: S_ENDPGM 0264 bb.0.bb:265 successors: %bb.1.bb1(0x40000000), %bb.2.bb2(0x40000000)266 liveins: $vgpr0, $sgpr0_sgpr1267 268 %3 = COPY $sgpr0_sgpr1269 %2 = COPY $vgpr0270 %7 = S_LOAD_DWORDX2_IMM %3, 9, 0271 %8 = S_LOAD_DWORDX2_IMM %3, 11, 0272 %9 = S_LOAD_DWORDX2_IMM %3, 13, 0273 %6 = COPY %7274 %10 = S_MOV_B32 0275 %11 = REG_SEQUENCE %2, %subreg.sub0, killed %10, %subreg.sub1276 %0 = COPY %11277 %12 = COPY %11.sub0278 %13 = COPY %11.sub1279 %14 = COPY %8.sub0280 %15 = COPY %8.sub1281 %16 = S_ADD_U32 %12, killed %14, implicit-def $scc282 %17 = S_ADDC_U32 %13, killed %15, implicit-def dead $scc, implicit $scc283 %18 = REG_SEQUENCE killed %16, %subreg.sub0, killed %17, %subreg.sub1284 %19 = COPY %9.sub0285 %20 = COPY %9.sub1286 %21 = S_ADD_U32 %12, killed %19, implicit-def $scc287 %22 = S_ADDC_U32 %13, killed %20, implicit-def dead $scc, implicit $scc288 %23 = REG_SEQUENCE killed %21, %subreg.sub0, killed %22, %subreg.sub1289 %24 = S_MOV_B32 0290 %25 = S_MOV_B32 1048576291 %26 = REG_SEQUENCE killed %25, %subreg.sub0, killed %24, %subreg.sub1292 %28 = COPY %26293 %27 = V_CMP_LT_U64_e64 killed %18, %28, implicit $exec294 %29 = V_CMP_LT_U64_e64 killed %23, %28, implicit $exec295 %31 = S_AND_B64 killed %27, killed %29, implicit-def dead $scc296 %1 = SI_IF killed %31, %bb.2.bb2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec297 S_BRANCH %bb.1.bb1298 299 bb.1.bb1:300 successors: %bb.2.bb2(0x80000000)301 302 %32 = S_MOV_B32 2303 %33 = S_LSHL_B64 %0, killed %32, implicit-def dead $scc304 %34 = S_MOV_B32 61440305 %35 = S_MOV_B32 0306 %36 = REG_SEQUENCE killed %35, %subreg.sub0, killed %34, %subreg.sub1307 %37 = REG_SEQUENCE %6, 17, killed %36, 18308 %38 = V_MOV_B32_e32 0, implicit $exec309 %39 = COPY %33310 BUFFER_STORE_DWORD_ADDR64 killed %38, killed %39, killed %37, 0, 0, 0, 0, implicit $exec311 312 bb.2.bb2:313 SI_END_CF %1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec314 S_ENDPGM 0315 316...317---318name: const_to_sgpr_subreg319alignment: 1320exposesReturnsTwice: false321legalized: false322regBankSelected: false323selected: false324tracksRegLiveness: true325registers:326 - { id: 0, class: sreg_64 }327 - { id: 1, class: sreg_64 }328 - { id: 2, class: vgpr_32 }329 - { id: 3, class: sgpr_64 }330 - { id: 4, class: sreg_32_xm0 }331 - { id: 5, class: sgpr_32 }332 - { id: 6, class: sreg_64 }333 - { id: 7, class: sreg_64_xexec }334 - { id: 8, class: sreg_64_xexec }335 - { id: 9, class: sreg_32 }336 - { id: 10, class: sreg_64 }337 - { id: 11, class: sreg_32_xm0 }338 - { id: 12, class: sreg_32_xm0 }339 - { id: 13, class: sreg_32_xm0 }340 - { id: 14, class: sreg_32_xm0 }341 - { id: 15, class: sreg_32_xm0 }342 - { id: 16, class: sreg_32_xm0 }343 - { id: 17, class: sreg_64 }344 - { id: 18, class: sreg_32_xm0 }345 - { id: 19, class: sreg_32_xm0 }346 - { id: 20, class: sreg_64 }347 - { id: 21, class: sreg_64 }348 - { id: 22, class: vgpr_32 }349 - { id: 23, class: sreg_32_xm0 }350 - { id: 24, class: sreg_64 }351 - { id: 25, class: sreg_32_xm0 }352 - { id: 26, class: sreg_32_xm0 }353 - { id: 27, class: sgpr_64 }354 - { id: 28, class: sgpr_128 }355 - { id: 29, class: vgpr_32 }356 - { id: 30, class: vreg_64 }357liveins:358 - { reg: '$vgpr0', virtual-reg: '%2' }359 - { reg: '$sgpr0_sgpr1', virtual-reg: '%3' }360body: |361 ; GCN-LABEL: name: const_to_sgpr_subreg362 ; GCN: bb.0.bb:363 ; GCN-NEXT: successors: %bb.1(0x40000000), %bb.2(0x40000000)364 ; GCN-NEXT: liveins: $vgpr0, $sgpr0_sgpr1365 ; GCN-NEXT: {{ $}}366 ; GCN-NEXT: [[COPY:%[0-9]+]]:sgpr_64 = COPY $sgpr0_sgpr1367 ; GCN-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0368 ; GCN-NEXT: [[S_LOAD_DWORDX2_IMM:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]], 9, 0369 ; GCN-NEXT: [[S_LOAD_DWORDX2_IMM1:%[0-9]+]]:sreg_64_xexec = S_LOAD_DWORDX2_IMM [[COPY]], 11, 0370 ; GCN-NEXT: [[COPY2:%[0-9]+]]:sreg_64 = COPY [[S_LOAD_DWORDX2_IMM]]371 ; GCN-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec372 ; GCN-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY1]], %subreg.sub0, killed [[V_MOV_B32_e32_]], %subreg.sub1373 ; GCN-NEXT: [[V_ADD_CO_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADD_CO_U32_e32 [[S_LOAD_DWORDX2_IMM1]].sub0, [[REG_SEQUENCE]].sub0, implicit-def $vcc, implicit $exec374 ; GCN-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[S_LOAD_DWORDX2_IMM1]].sub1375 ; GCN-NEXT: [[V_ADDC_U32_e32_:%[0-9]+]]:vgpr_32 = V_ADDC_U32_e32 0, [[COPY3]], implicit-def $vcc, implicit $vcc, implicit $exec376 ; GCN-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE killed [[V_ADD_CO_U32_e32_]], %subreg.sub0, killed [[V_ADDC_U32_e32_]], %subreg.sub1377 ; GCN-NEXT: [[V_CMP_LT_U32_e64_:%[0-9]+]]:sreg_64 = V_CMP_LT_U32_e64 killed [[REG_SEQUENCE1]].sub0, 12, implicit $exec378 ; GCN-NEXT: [[SI_IF:%[0-9]+]]:sreg_64 = SI_IF killed [[V_CMP_LT_U32_e64_]], %bb.2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec379 ; GCN-NEXT: S_BRANCH %bb.1380 ; GCN-NEXT: {{ $}}381 ; GCN-NEXT: bb.1.bb1:382 ; GCN-NEXT: successors: %bb.2(0x80000000)383 ; GCN-NEXT: {{ $}}384 ; GCN-NEXT: [[V_LSHL_B64_e64_:%[0-9]+]]:vreg_64 = V_LSHL_B64_e64 [[REG_SEQUENCE]], 2, implicit $exec385 ; GCN-NEXT: [[S_MOV_B32_:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 61440386 ; GCN-NEXT: [[S_MOV_B32_1:%[0-9]+]]:sreg_32_xm0 = S_MOV_B32 0387 ; GCN-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:sgpr_64 = REG_SEQUENCE killed [[S_MOV_B32_1]], %subreg.sub0, killed [[S_MOV_B32_]], %subreg.sub1388 ; GCN-NEXT: [[REG_SEQUENCE3:%[0-9]+]]:sgpr_128 = REG_SEQUENCE [[COPY2]], %subreg.sub1_sub2_sub3_sub4_sub5, killed [[REG_SEQUENCE2]], %subreg.sub1_sub2_sub3_sub4_sub5_sub6389 ; GCN-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec390 ; GCN-NEXT: BUFFER_STORE_DWORD_ADDR64 killed [[V_MOV_B32_e32_1]], [[V_LSHL_B64_e64_]], killed [[REG_SEQUENCE3]], 0, 0, 0, 0, implicit $exec391 ; GCN-NEXT: {{ $}}392 ; GCN-NEXT: bb.2.bb2:393 ; GCN-NEXT: SI_END_CF [[SI_IF]], implicit-def dead $exec, implicit-def dead $scc, implicit $exec394 ; GCN-NEXT: S_ENDPGM 0395 bb.0.bb:396 successors: %bb.1.bb1(0x40000000), %bb.2.bb2(0x40000000)397 liveins: $vgpr0, $sgpr0_sgpr1398 399 %3 = COPY $sgpr0_sgpr1400 %2 = COPY $vgpr0401 %7 = S_LOAD_DWORDX2_IMM %3, 9, 0402 %8 = S_LOAD_DWORDX2_IMM %3, 11, 0403 %6 = COPY %7404 %9 = S_MOV_B32 0405 %10 = REG_SEQUENCE %2, %subreg.sub0, killed %9, %subreg.sub1406 %0 = COPY %10407 %11 = COPY %10.sub0408 %12 = COPY %10.sub1409 %13 = COPY %8.sub0410 %14 = COPY %8.sub1411 %15 = S_ADD_U32 killed %11, killed %13, implicit-def $scc412 %16 = S_ADDC_U32 killed %12, killed %14, implicit-def dead $scc, implicit $scc413 %17 = REG_SEQUENCE killed %15, %subreg.sub0, killed %16, %subreg.sub1414 %18 = S_MOV_B32 12415 %19 = S_MOV_B32 1048576416 %20 = REG_SEQUENCE killed %19, %subreg.sub0, killed %18, %subreg.sub1417 %22 = COPY killed %20.sub1418 %21 = V_CMP_LT_U32_e64 killed %17.sub0, %22, implicit $exec419 %1 = SI_IF killed %21, %bb.2.bb2, implicit-def dead $exec, implicit-def dead $scc, implicit $exec420 S_BRANCH %bb.1.bb1421 422 bb.1.bb1:423 successors: %bb.2.bb2(0x80000000)424 425 %23 = S_MOV_B32 2426 %24 = S_LSHL_B64 %0, killed %23, implicit-def dead $scc427 %25 = S_MOV_B32 61440428 %26 = S_MOV_B32 0429 %27 = REG_SEQUENCE killed %26, %subreg.sub0, killed %25, %subreg.sub1430 %28 = REG_SEQUENCE %6, 17, killed %27, 18431 %29 = V_MOV_B32_e32 0, implicit $exec432 %30 = COPY %24433 BUFFER_STORE_DWORD_ADDR64 killed %29, killed %30, killed %28, 0, 0, 0, 0, implicit $exec434 435 bb.2.bb2:436 SI_END_CF %1, implicit-def dead $exec, implicit-def dead $scc, implicit $exec437 S_ENDPGM 0438 439...440