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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py2# RUN: llc -mtriple amdgcn-amd-amdhsa -mcpu=gfx1030 -verify-machineinstrs -run-pass=si-optimize-exec-masking-pre-ra %s -o - | FileCheck --check-prefix=GCN %s3 4# %8 is defined at the end, but it will be used in bb.2.5# Make sure we properly extend its liverange to the beginning of the bb.2.6# and to the end of the bb.67 8---9name: def_later_than_use10tracksRegLiveness: true11body:             |12  ; GCN-LABEL: name: def_later_than_use13  ; GCN: bb.0:14  ; GCN-NEXT:   successors: %bb.1(0x80000000)15  ; GCN-NEXT: {{  $}}16  ; GCN-NEXT:   [[GLOBAL_LOAD_USHORT:%[0-9]+]]:vgpr_32 = GLOBAL_LOAD_USHORT undef %1:vreg_64, 0, 0, implicit $exec17  ; GCN-NEXT:   [[DEF:%[0-9]+]]:sreg_32_xm0_xexec = IMPLICIT_DEF18  ; GCN-NEXT: {{  $}}19  ; GCN-NEXT: bb.1:20  ; GCN-NEXT:   successors: %bb.6(0x04000000), %bb.1(0x7c000000)21  ; GCN-NEXT: {{  $}}22  ; GCN-NEXT:   [[S_AND_B32_:%[0-9]+]]:sreg_32 = S_AND_B32 $exec_lo, [[DEF]], implicit-def dead $scc23  ; GCN-NEXT:   $vcc_lo = COPY [[S_AND_B32_]]24  ; GCN-NEXT:   S_CBRANCH_VCCNZ %bb.6, implicit $vcc25  ; GCN-NEXT:   S_BRANCH %bb.126  ; GCN-NEXT: {{  $}}27  ; GCN-NEXT: bb.2:28  ; GCN-NEXT:   successors: %bb.3(0x80000000)29  ; GCN-NEXT: {{  $}}30  ; GCN-NEXT:   $vcc_lo = S_ANDN2_B32 $exec_lo, %8, implicit-def dead $scc31  ; GCN-NEXT:   S_CBRANCH_VCCNZ %bb.3, implicit $vcc32  ; GCN-NEXT:   S_BRANCH %bb.333  ; GCN-NEXT: {{  $}}34  ; GCN-NEXT: bb.3:35  ; GCN-NEXT:   successors: %bb.4(0x50000000), %bb.5(0x30000000)36  ; GCN-NEXT: {{  $}}37  ; GCN-NEXT:   $exec_lo = S_OR_B32 $exec_lo, %6, implicit-def $scc38  ; GCN-NEXT:   [[V_CMP_NE_U32_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 1, %5, implicit $exec39  ; GCN-NEXT:   $vcc_lo = S_AND_B32 $exec_lo, [[V_CMP_NE_U32_e64_]], implicit-def dead $scc40  ; GCN-NEXT:   S_CBRANCH_VCCNZ %bb.5, implicit $vcc41  ; GCN-NEXT:   S_BRANCH %bb.442  ; GCN-NEXT: {{  $}}43  ; GCN-NEXT: bb.4:44  ; GCN-NEXT:   successors: %bb.5(0x80000000)45  ; GCN-NEXT: {{  $}}46  ; GCN-NEXT: bb.5:47  ; GCN-NEXT:   S_ENDPGM 048  ; GCN-NEXT: {{  $}}49  ; GCN-NEXT: bb.6:50  ; GCN-NEXT:   successors: %bb.2(0x40000000), %bb.3(0x40000000)51  ; GCN-NEXT: {{  $}}52  ; GCN-NEXT:   [[V_CMP_NEQ_F16_e64_:%[0-9]+]]:sreg_32_xm0_xexec = V_CMP_NEQ_F16_e64 0, 0, 0, [[GLOBAL_LOAD_USHORT]], 0, implicit $mode, implicit $exec53  ; GCN-NEXT:   [[V_CNDMASK_B32_e64_:%[0-9]+]]:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, [[V_CMP_NEQ_F16_e64_]], implicit $exec54  ; GCN-NEXT:   [[S_CSELECT_B32_:%[0-9]+]]:sreg_32_xm0_xexec = S_CSELECT_B32 -1, 0, implicit undef $scc55  ; GCN-NEXT:   [[S_AND_B32_1:%[0-9]+]]:sreg_32 = S_AND_B32 $exec_lo, [[S_CSELECT_B32_]], implicit-def dead $scc56  ; GCN-NEXT:   $exec_lo = S_MOV_B32_term [[S_AND_B32_1]]57  ; GCN-NEXT:   S_CBRANCH_EXECZ %bb.3, implicit $exec58  ; GCN-NEXT:   S_BRANCH %bb.259  bb.0:60    successors: %bb.1(0x80000000)61 62    %0:vgpr_32 = GLOBAL_LOAD_USHORT undef %1:vreg_64, 0, 0, implicit $exec63    %2:sreg_32_xm0_xexec = IMPLICIT_DEF64 65  bb.1:66    successors: %bb.6(0x04000000), %bb.1(0x7c000000)67 68    %3:sreg_32 = S_AND_B32 $exec_lo, %2, implicit-def dead $scc69    $vcc_lo = COPY %370    S_CBRANCH_VCCNZ %bb.6, implicit killed $vcc71    S_BRANCH %bb.172 73  bb.2:74    successors: %bb.3(0x80000000)75 76    %4:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 1, %5, implicit $exec77    $vcc_lo = S_AND_B32 $exec_lo, %4, implicit-def dead $scc78    S_CBRANCH_VCCNZ %bb.3, implicit killed $vcc79    S_BRANCH %bb.380 81  bb.3:82    successors: %bb.4(0x50000000), %bb.5(0x30000000)83 84    $exec_lo = S_OR_B32 $exec_lo, %6, implicit-def $scc85    %7:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 1, %5, implicit $exec86    $vcc_lo = S_AND_B32 $exec_lo, %7, implicit-def dead $scc87    S_CBRANCH_VCCNZ %bb.5, implicit killed $vcc88    S_BRANCH %bb.489 90  bb.4:91    successors: %bb.5(0x80000000)92 93  bb.5:94    S_ENDPGM 095 96  bb.6:97    successors: %bb.2(0x40000000), %bb.3(0x40000000)98 99    %8:sreg_32_xm0_xexec = V_CMP_NEQ_F16_e64 0, 0, 0, %0, 0, implicit $mode, implicit $exec100    %5:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %8, implicit $exec101    %9:sreg_32_xm0_xexec = S_CSELECT_B32 -1, 0, implicit undef $scc102    %10:sreg_32 = COPY $exec_lo, implicit-def $exec_lo103    %6:sreg_32 = S_AND_B32 %10, %9, implicit-def dead $scc104    $exec_lo = S_MOV_B32_term %6105    S_CBRANCH_EXECZ %bb.3, implicit $exec106    S_BRANCH %bb.2107 108...109