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1# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=si-optimize-exec-masking-pre-ra,greedy -verify-machineinstrs -o - %s2 3# This sample can trigger a "Non-empty but used interval" assert in regalloc if4# SIOptimizeExecMaskingPreRA does not update live intervals correctly.5 6---7name: foo8tracksRegLiveness: true9body: |10 bb.0:11 %0:sreg_32 = IMPLICIT_DEF12 %1:sreg_32_xm0_xexec = IMPLICIT_DEF13 %2:sreg_64_xexec_xnull = IMPLICIT_DEF14 %3:sgpr_32 = IMPLICIT_DEF15 %4:sreg_32_xexec_hi = IMPLICIT_DEF16 %5:sreg_32 = IMPLICIT_DEF17 %6:sreg_32 = IMPLICIT_DEF18 %7:sreg_32 = IMPLICIT_DEF19 %8:sreg_32 = IMPLICIT_DEF20 %9:sreg_32 = IMPLICIT_DEF21 %10:sreg_32 = IMPLICIT_DEF22 %11:sreg_32 = IMPLICIT_DEF23 %12:sreg_64_xexec = IMPLICIT_DEF24 %13:sreg_64_xexec_xnull = IMPLICIT_DEF25 %14:sreg_32 = IMPLICIT_DEF26 %15:sreg_32 = IMPLICIT_DEF27 %16:sreg_32 = IMPLICIT_DEF28 %17:sreg_32 = IMPLICIT_DEF29 %18:sgpr_32 = IMPLICIT_DEF30 $exec_lo = S_MOV_B32_term undef %931 S_BRANCH %bb.232 33 bb.1:34 $exec_lo = S_XOR_B32_term $exec_lo, undef %10, implicit-def $scc35 S_CBRANCH_EXECZ %bb.39, implicit $exec36 S_BRANCH %bb.3237 38 bb.2:39 S_CMP_EQ_U32 %15, undef %15, implicit-def $scc40 %19:sreg_32_xm0_xexec = S_CSELECT_B32 -1, 0, implicit killed undef $scc41 %20:sreg_32 = IMPLICIT_DEF42 $vcc_lo = COPY undef %2043 S_CBRANCH_VCCNZ %bb.3, implicit $vcc44 S_BRANCH %bb.345 46 bb.3:47 $vcc_lo = S_AND_B32 $exec_lo, undef %19, implicit-def dead $scc48 S_CBRANCH_VCCNZ %bb.6, implicit $vcc49 S_BRANCH %bb.450 51 bb.4:52 %21:vgpr_32 = V_CNDMASK_B32_e64 0, 0, 0, 1, %19, implicit $exec53 %22:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 1, undef %21, implicit $exec54 $vcc_lo = S_AND_B32 $exec_lo, undef %22, implicit-def dead $scc55 S_CBRANCH_VCCNZ %bb.7, implicit $vcc56 S_BRANCH %bb.557 58 bb.5:59 S_BRANCH %bb.760 61 bb.6:62 $vcc_lo = COPY %2063 %18:sgpr_32 = COPY %1864 S_CBRANCH_VCCNZ %bb.1, implicit killed $vcc65 S_BRANCH %bb.266 67 bb.7:68 %23:sreg_32 = S_AND_B32 undef %20, %9, implicit-def dead $scc69 $exec_lo = S_MOV_B32_term undef %2370 S_CBRANCH_EXECZ %bb.10, implicit $exec71 S_BRANCH %bb.972 73 bb.8:74 %24:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %13, undef %21, 0, 0, implicit $exec75 S_BRANCH %bb.2876 77 bb.9:78 S_BRANCH %bb.1179 80 bb.10:81 $exec_lo = S_XOR_B32_term $exec_lo, %23, implicit-def $scc82 S_CBRANCH_EXECZ %bb.31, implicit $exec83 S_BRANCH %bb.884 85 bb.11:86 %25:vgpr_32 = GLOBAL_LOAD_DWORD_SADDR %2, undef %21, 0, 0, implicit $exec87 $exec_lo = S_MOV_B32_term undef %2388 S_CBRANCH_EXECZ %bb.12, implicit $exec89 S_BRANCH %bb.1490 91 bb.12:92 $exec_lo = S_XOR_B32_term $exec_lo, undef %23, implicit-def $scc93 S_CBRANCH_EXECZ %bb.15, implicit $exec94 S_BRANCH %bb.1395 96 bb.13:97 $exec_lo = S_MOV_B32_term undef %2398 S_CBRANCH_EXECZ %bb.15, implicit $exec99 S_BRANCH %bb.15100 101 bb.14:102 %26:vgpr_32 = V_BFI_B32_e64 2147483647, %3, undef %25, implicit $exec103 %27:vgpr_32 = V_CNDMASK_B32_e64 0, undef %26, 0, 2143289344, %1, implicit $exec104 dead %28:vgpr_32, %29:sreg_32_xm0_xexec = V_ADD_CO_U32_e64 %12.sub0, undef %27, 0, implicit $exec105 %30:vgpr_32, dead %31:sreg_32_xm0_xexec = V_ADDC_U32_e64 %12.sub1, undef %27, undef %22, 0, implicit $exec106 SCRATCH_STORE_DWORD_SADDR undef %27, %4, 0, 0, implicit $exec, implicit $flat_scr107 S_BRANCH %bb.12108 109 bb.15:110 %32:sreg_32 = IMPLICIT_DEF111 $exec_lo = S_MOV_B32_term undef %32112 S_CBRANCH_EXECZ %bb.17, implicit $exec113 S_BRANCH %bb.16114 115 bb.16:116 %33:sreg_32 = S_AND_B32 undef %32, %16, implicit-def dead $scc117 $exec_lo = S_MOV_B32_term undef %33118 S_CBRANCH_EXECZ %bb.17, implicit $exec119 S_BRANCH %bb.17120 121 bb.17:122 $exec_lo = S_XOR_B32_term $exec_lo, undef %32, implicit-def $scc123 S_CBRANCH_EXECZ %bb.30, implicit $exec124 S_BRANCH %bb.18125 126 bb.18:127 %34:sreg_32 = IMPLICIT_DEF128 %35:sreg_32 = S_AND_B32 undef %34, %17, implicit-def dead $scc129 $exec_lo = S_MOV_B32_term undef %35130 S_CBRANCH_EXECZ %bb.20, implicit $exec131 S_BRANCH %bb.19132 133 bb.19:134 dead %36:vgpr_32, $sgpr_null = V_ADD_CO_U32_e64 %14, undef %25, 0, implicit $exec135 %37:sreg_32 = IMPLICIT_DEF136 S_BRANCH %bb.21137 138 bb.20:139 $exec_lo = S_OR_B32 $exec_lo, %34, implicit-def $scc140 S_BRANCH %bb.30141 142 bb.21:143 %38:sreg_32 = IMPLICIT_DEF144 $exec_lo = S_MOV_B32_term undef %38145 S_CBRANCH_EXECZ %bb.23, implicit $exec146 S_BRANCH %bb.22147 148 bb.22:149 S_BRANCH %bb.24150 151 bb.23:152 S_BRANCH %bb.26153 154 bb.24:155 %39:sreg_32 = S_AND_B32 undef %38, %11, implicit-def dead $scc156 $exec_lo = S_MOV_B32_term undef %39157 S_CBRANCH_EXECZ %bb.38, implicit $exec158 S_BRANCH %bb.25159 160 bb.25:161 %40:sreg_32 = S_AND_B32 %5, $exec_lo, implicit-def dead $scc162 S_BRANCH %bb.38163 164 bb.26:165 %37:sreg_32 = S_OR_B32 %38, %37, implicit-def $scc166 $exec_lo = S_ANDN2_B32_term $exec_lo, undef %37, implicit-def $scc167 S_CBRANCH_EXECNZ %bb.21, implicit $exec168 S_BRANCH %bb.27169 170 bb.27:171 %41:sreg_32 = S_OR_B32 undef %37, %35, implicit-def $scc172 $exec_lo = S_ANDN2_B32_term $exec_lo, undef %35, implicit-def $scc173 S_CBRANCH_EXECNZ %bb.21, implicit $exec174 S_BRANCH %bb.20175 176 bb.28:177 $vcc_lo = S_AND_B32 $exec_lo, %22, implicit-def dead $scc178 S_CBRANCH_VCCNZ %bb.29, implicit $vcc179 S_BRANCH %bb.29180 181 bb.29:182 $exec_lo = S_ANDN2_B32_term $exec_lo, undef %23, implicit-def $scc183 S_CBRANCH_EXECNZ %bb.28, implicit $exec184 S_BRANCH %bb.31185 186 bb.30:187 $exec_lo = S_OR_B32 $exec_lo, %32, implicit-def $scc188 S_BRANCH %bb.10189 190 bb.31:191 %42:sreg_32_xm0_xexec = V_CMP_NE_U32_e64 undef %23, %21, implicit $exec192 $vcc_lo = S_AND_B32 $exec_lo, undef %42, implicit-def dead $scc193 S_CBRANCH_VCCZ %bb.6, implicit killed $vcc194 195 bb.32:196 %43:sreg_32 = S_AND_B32 %10, %8, implicit-def dead $scc197 $exec_lo = S_MOV_B32_term undef %43198 S_CBRANCH_EXECZ %bb.37, implicit $exec199 S_BRANCH %bb.33200 201 bb.33:202 %44:sreg_32 = S_AND_B32 undef %43, %0, implicit-def dead $scc203 $exec_lo = S_MOV_B32_term undef %44204 S_CBRANCH_EXECZ %bb.37, implicit $exec205 S_BRANCH %bb.34206 207 bb.34:208 %45:sreg_32 = S_AND_B32 undef %44, %6, implicit-def dead $scc209 $exec_lo = S_MOV_B32_term undef %45210 S_CBRANCH_EXECZ %bb.37, implicit $exec211 S_BRANCH %bb.35212 213 bb.35:214 %46:sreg_32 = S_AND_B32 undef %45, %7, implicit-def dead $scc215 $exec_lo = S_MOV_B32_term undef %46216 S_CBRANCH_EXECZ %bb.36, implicit $exec217 S_BRANCH %bb.37218 219 bb.36:220 S_BRANCH %bb.37221 222 bb.37:223 dead $vcc_lo = COPY undef %47:sreg_32224 S_BRANCH %bb.39225 226 bb.38:227 S_BRANCH %bb.26228 229 bb.39:230 SI_RETURN231 232...233