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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 32; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG %s3 4 5define amdgpu_kernel void @or_v2i32(ptr addrspace(1) %out, ptr addrspace(1) %in) {6; EG-LABEL: or_v2i32:7; EG: ; %bb.0:8; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]9; EG-NEXT: TEX 0 @610; EG-NEXT: ALU 3, @9, KC0[CB0:0-32], KC1[]11; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 112; EG-NEXT: CF_END13; EG-NEXT: PAD14; EG-NEXT: Fetch clause starting at 6:15; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #116; EG-NEXT: ALU clause starting at 8:17; EG-NEXT: MOV * T0.X, KC0[2].Z,18; EG-NEXT: ALU clause starting at 9:19; EG-NEXT: OR_INT * T0.Y, T0.Y, T0.W,20; EG-NEXT: OR_INT T0.X, T0.X, T0.Z,21; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,22; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)23 %b_ptr = getelementptr <2 x i32>, ptr addrspace(1) %in, i32 124 %a = load <2 x i32>, ptr addrspace(1) %in25 %b = load <2 x i32>, ptr addrspace(1) %b_ptr26 %result = or <2 x i32> %a, %b27 store <2 x i32> %result, ptr addrspace(1) %out28 ret void29}30 31define amdgpu_kernel void @or_v4i32(ptr addrspace(1) %out, ptr addrspace(1) %in) {32; EG-LABEL: or_v4i32:33; EG: ; %bb.0:34; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[]35; EG-NEXT: TEX 1 @636; EG-NEXT: ALU 5, @11, KC0[CB0:0-32], KC1[]37; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 138; EG-NEXT: CF_END39; EG-NEXT: PAD40; EG-NEXT: Fetch clause starting at 6:41; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 16, #142; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #143; EG-NEXT: ALU clause starting at 10:44; EG-NEXT: MOV * T0.X, KC0[2].Z,45; EG-NEXT: ALU clause starting at 11:46; EG-NEXT: OR_INT * T0.W, T0.W, T1.W,47; EG-NEXT: OR_INT * T0.Z, T0.Z, T1.Z,48; EG-NEXT: OR_INT * T0.Y, T0.Y, T1.Y,49; EG-NEXT: OR_INT T0.X, T0.X, T1.X,50; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,51; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)52 %b_ptr = getelementptr <4 x i32>, ptr addrspace(1) %in, i32 153 %a = load <4 x i32>, ptr addrspace(1) %in54 %b = load <4 x i32>, ptr addrspace(1) %b_ptr55 %result = or <4 x i32> %a, %b56 store <4 x i32> %result, ptr addrspace(1) %out57 ret void58}59 60define amdgpu_kernel void @scalar_or_i32(ptr addrspace(1) %out, i32 %a, i32 %b) {61; EG-LABEL: scalar_or_i32:62; EG: ; %bb.0:63; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]64; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 165; EG-NEXT: CF_END66; EG-NEXT: PAD67; EG-NEXT: ALU clause starting at 4:68; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x,69; EG-NEXT: OR_INT * T1.X, KC0[2].Z, KC0[2].W,70; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)71 %or = or i32 %a, %b72 store i32 %or, ptr addrspace(1) %out73 ret void74}75 76define amdgpu_kernel void @vector_or_i32(ptr addrspace(1) %out, ptr addrspace(1) %a, i32 %b) {77; EG-LABEL: vector_or_i32:78; EG: ; %bb.0:79; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]80; EG-NEXT: TEX 0 @681; EG-NEXT: ALU 2, @9, KC0[CB0:0-32], KC1[]82; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 183; EG-NEXT: CF_END84; EG-NEXT: PAD85; EG-NEXT: Fetch clause starting at 6:86; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #187; EG-NEXT: ALU clause starting at 8:88; EG-NEXT: MOV * T0.X, KC0[2].Z,89; EG-NEXT: ALU clause starting at 9:90; EG-NEXT: OR_INT T0.X, T0.X, KC0[2].W,91; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,92; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)93 %loada = load i32, ptr addrspace(1) %a94 %or = or i32 %loada, %b95 store i32 %or, ptr addrspace(1) %out96 ret void97}98 99define amdgpu_kernel void @scalar_or_literal_i32(ptr addrspace(1) %out, i32 %a) {100; EG-LABEL: scalar_or_literal_i32:101; EG: ; %bb.0:102; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]103; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1104; EG-NEXT: CF_END105; EG-NEXT: PAD106; EG-NEXT: ALU clause starting at 4:107; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x,108; EG-NEXT: OR_INT * T1.X, KC0[2].Z, literal.y,109; EG-NEXT: 2(2.802597e-45), 99999(1.401284e-40)110 %or = or i32 %a, 99999111 store i32 %or, ptr addrspace(1) %out, align 4112 ret void113}114 115define amdgpu_kernel void @scalar_or_literal_i64(ptr addrspace(1) %out, [8 x i32], i64 %a) {116; EG-LABEL: scalar_or_literal_i64:117; EG: ; %bb.0:118; EG-NEXT: ALU 4, @4, KC0[CB0:0-32], KC1[]119; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1120; EG-NEXT: CF_END121; EG-NEXT: PAD122; EG-NEXT: ALU clause starting at 4:123; EG-NEXT: OR_INT * T0.Y, KC0[5].X, literal.x,124; EG-NEXT: 992123(1.390260e-39), 0(0.000000e+00)125; EG-NEXT: OR_INT T0.X, KC0[4].W, literal.x,126; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,127; EG-NEXT: 12345(1.729903e-41), 2(2.802597e-45)128 %or = or i64 %a, 4261135838621753129 store i64 %or, ptr addrspace(1) %out130 ret void131}132 133define amdgpu_kernel void @scalar_or_literal_multi_use_i64(ptr addrspace(1) %out, [8 x i32], i64 %a, [8 x i32], i64 %b) {134; EG-LABEL: scalar_or_literal_multi_use_i64:135; EG: ; %bb.0:136; EG-NEXT: ALU 12, @6, KC0[CB0:0-32], KC1[]137; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T3.XY, T4.X, 0138; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T2.X, 0139; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T2.X, 1140; EG-NEXT: CF_END141; EG-NEXT: PAD142; EG-NEXT: ALU clause starting at 6:143; EG-NEXT: ADDC_UINT * T0.W, KC0[7].Y, literal.x,144; EG-NEXT: 12345(1.729903e-41), 0(0.000000e+00)145; EG-NEXT: ADD_INT T0.X, KC0[7].Y, literal.x,146; EG-NEXT: ADD_INT * T0.W, KC0[7].Z, PV.W,147; EG-NEXT: 12345(1.729903e-41), 0(0.000000e+00)148; EG-NEXT: ADD_INT T1.X, PV.W, literal.x,149; EG-NEXT: MOV * T2.X, literal.y,150; EG-NEXT: 992123(1.390260e-39), 0(0.000000e+00)151; EG-NEXT: OR_INT * T3.Y, KC0[5].X, literal.x,152; EG-NEXT: 992123(1.390260e-39), 0(0.000000e+00)153; EG-NEXT: OR_INT T3.X, KC0[4].W, literal.x,154; EG-NEXT: LSHR * T4.X, KC0[2].Y, literal.y,155; EG-NEXT: 12345(1.729903e-41), 2(2.802597e-45)156 %or = or i64 %a, 4261135838621753157 store i64 %or, ptr addrspace(1) %out158 159 %foo = add i64 %b, 4261135838621753160 store volatile i64 %foo, ptr addrspace(1) poison161 ret void162}163 164define amdgpu_kernel void @scalar_or_inline_imm_i64(ptr addrspace(1) %out, [8 x i32], i64 %a) {165; EG-LABEL: scalar_or_inline_imm_i64:166; EG: ; %bb.0:167; EG-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]168; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1169; EG-NEXT: CF_END170; EG-NEXT: PAD171; EG-NEXT: ALU clause starting at 4:172; EG-NEXT: MOV * T0.Y, KC0[5].X,173; EG-NEXT: OR_INT T0.X, KC0[4].W, literal.x,174; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,175; EG-NEXT: 63(8.828180e-44), 2(2.802597e-45)176 %or = or i64 %a, 63177 store i64 %or, ptr addrspace(1) %out178 ret void179}180 181define amdgpu_kernel void @scalar_or_inline_imm_multi_use_i64(ptr addrspace(1) %out, i64 %a, i64 %b) {182; EG-LABEL: scalar_or_inline_imm_multi_use_i64:183; EG: ; %bb.0:184; EG-NEXT: ALU 9, @6, KC0[CB0:0-32], KC1[]185; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T3.XY, T4.X, 0186; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T2.X, 0187; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T2.X, 1188; EG-NEXT: CF_END189; EG-NEXT: PAD190; EG-NEXT: ALU clause starting at 6:191; EG-NEXT: ADD_INT T0.X, KC0[3].Y, literal.x,192; EG-NEXT: ADDC_UINT * T0.W, KC0[3].Y, literal.x,193; EG-NEXT: 63(8.828180e-44), 0(0.000000e+00)194; EG-NEXT: ADD_INT T1.X, KC0[3].Z, PV.W,195; EG-NEXT: MOV * T2.X, literal.x,196; EG-NEXT: 0(0.000000e+00), 0(0.000000e+00)197; EG-NEXT: MOV * T3.Y, KC0[3].X,198; EG-NEXT: OR_INT T3.X, KC0[2].W, literal.x,199; EG-NEXT: LSHR * T4.X, KC0[2].Y, literal.y,200; EG-NEXT: 63(8.828180e-44), 2(2.802597e-45)201 %or = or i64 %a, 63202 store i64 %or, ptr addrspace(1) %out203 %foo = add i64 %b, 63204 store volatile i64 %foo, ptr addrspace(1) poison205 ret void206}207 208define amdgpu_kernel void @scalar_or_neg_inline_imm_i64(ptr addrspace(1) %out, [8 x i32], i64 %a) {209; EG-LABEL: scalar_or_neg_inline_imm_i64:210; EG: ; %bb.0:211; EG-NEXT: ALU 4, @4, KC0[CB0:0-32], KC1[]212; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1213; EG-NEXT: CF_END214; EG-NEXT: PAD215; EG-NEXT: ALU clause starting at 4:216; EG-NEXT: OR_INT T0.X, KC0[4].W, literal.x,217; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,218; EG-NEXT: -8(nan), 2(2.802597e-45)219; EG-NEXT: MOV * T0.Y, literal.x,220; EG-NEXT: -1(nan), 0(0.000000e+00)221 %or = or i64 %a, -8222 store i64 %or, ptr addrspace(1) %out223 ret void224}225 226define amdgpu_kernel void @vector_or_literal_i32(ptr addrspace(1) %out, ptr addrspace(1) %a, ptr addrspace(1) %b) {227; EG-LABEL: vector_or_literal_i32:228; EG: ; %bb.0:229; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]230; EG-NEXT: TEX 0 @6231; EG-NEXT: ALU 2, @9, KC0[CB0:0-32], KC1[]232; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1233; EG-NEXT: CF_END234; EG-NEXT: PAD235; EG-NEXT: Fetch clause starting at 6:236; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1237; EG-NEXT: ALU clause starting at 8:238; EG-NEXT: MOV * T0.X, KC0[2].Z,239; EG-NEXT: ALU clause starting at 9:240; EG-NEXT: OR_INT T0.X, T0.X, literal.x,241; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,242; EG-NEXT: 65535(9.183409e-41), 2(2.802597e-45)243 %loada = load i32, ptr addrspace(1) %a, align 4244 %or = or i32 %loada, 65535245 store i32 %or, ptr addrspace(1) %out, align 4246 ret void247}248 249define amdgpu_kernel void @vector_or_inline_immediate_i32(ptr addrspace(1) %out, ptr addrspace(1) %a, ptr addrspace(1) %b) {250; EG-LABEL: vector_or_inline_immediate_i32:251; EG: ; %bb.0:252; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]253; EG-NEXT: TEX 0 @6254; EG-NEXT: ALU 2, @9, KC0[CB0:0-32], KC1[]255; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1256; EG-NEXT: CF_END257; EG-NEXT: PAD258; EG-NEXT: Fetch clause starting at 6:259; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1260; EG-NEXT: ALU clause starting at 8:261; EG-NEXT: MOV * T0.X, KC0[2].Z,262; EG-NEXT: ALU clause starting at 9:263; EG-NEXT: OR_INT T0.X, T0.X, literal.x,264; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,265; EG-NEXT: 4(5.605194e-45), 2(2.802597e-45)266 %loada = load i32, ptr addrspace(1) %a, align 4267 %or = or i32 %loada, 4268 store i32 %or, ptr addrspace(1) %out, align 4269 ret void270}271 272define amdgpu_kernel void @scalar_or_i64(ptr addrspace(1) %out, i64 %a, i64 %b) {273; EG-LABEL: scalar_or_i64:274; EG: ; %bb.0:275; EG-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]276; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1277; EG-NEXT: CF_END278; EG-NEXT: PAD279; EG-NEXT: ALU clause starting at 4:280; EG-NEXT: OR_INT * T0.Y, KC0[3].X, KC0[3].Z,281; EG-NEXT: OR_INT * T0.X, KC0[2].W, KC0[3].Y,282; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,283; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)284 %or = or i64 %a, %b285 store i64 %or, ptr addrspace(1) %out286 ret void287}288 289define amdgpu_kernel void @vector_or_i64(ptr addrspace(1) %out, ptr addrspace(1) %a, ptr addrspace(1) %b) {290; EG-LABEL: vector_or_i64:291; EG: ; %bb.0:292; EG-NEXT: ALU 1, @10, KC0[CB0:0-32], KC1[]293; EG-NEXT: TEX 1 @6294; EG-NEXT: ALU 3, @12, KC0[CB0:0-32], KC1[]295; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1296; EG-NEXT: CF_END297; EG-NEXT: PAD298; EG-NEXT: Fetch clause starting at 6:299; EG-NEXT: VTX_READ_64 T1.XY, T1.X, 0, #1300; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #1301; EG-NEXT: ALU clause starting at 10:302; EG-NEXT: MOV T0.X, KC0[2].Z,303; EG-NEXT: MOV * T1.X, KC0[2].W,304; EG-NEXT: ALU clause starting at 12:305; EG-NEXT: OR_INT * T0.Y, T0.Y, T1.Y,306; EG-NEXT: OR_INT T0.X, T0.X, T1.X,307; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,308; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)309 %loada = load i64, ptr addrspace(1) %a, align 8310 %loadb = load i64, ptr addrspace(1) %b, align 8311 %or = or i64 %loada, %loadb312 store i64 %or, ptr addrspace(1) %out313 ret void314}315 316define amdgpu_kernel void @scalar_vector_or_i64(ptr addrspace(1) %out, ptr addrspace(1) %a, i64 %b) {317; EG-LABEL: scalar_vector_or_i64:318; EG: ; %bb.0:319; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]320; EG-NEXT: TEX 0 @6321; EG-NEXT: ALU 3, @9, KC0[CB0:0-32], KC1[]322; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1323; EG-NEXT: CF_END324; EG-NEXT: PAD325; EG-NEXT: Fetch clause starting at 6:326; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #1327; EG-NEXT: ALU clause starting at 8:328; EG-NEXT: MOV * T0.X, KC0[2].Z,329; EG-NEXT: ALU clause starting at 9:330; EG-NEXT: OR_INT * T0.Y, T0.Y, KC0[3].X,331; EG-NEXT: OR_INT T0.X, T0.X, KC0[2].W,332; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,333; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)334 %loada = load i64, ptr addrspace(1) %a335 %or = or i64 %loada, %b336 store i64 %or, ptr addrspace(1) %out337 ret void338}339 340define amdgpu_kernel void @vector_or_i64_loadimm(ptr addrspace(1) %out, ptr addrspace(1) %a, ptr addrspace(1) %b) {341; EG-LABEL: vector_or_i64_loadimm:342; EG: ; %bb.0:343; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]344; EG-NEXT: TEX 0 @6345; EG-NEXT: ALU 4, @9, KC0[CB0:0-32], KC1[]346; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1347; EG-NEXT: CF_END348; EG-NEXT: PAD349; EG-NEXT: Fetch clause starting at 6:350; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #1351; EG-NEXT: ALU clause starting at 8:352; EG-NEXT: MOV * T0.X, KC0[2].Z,353; EG-NEXT: ALU clause starting at 9:354; EG-NEXT: OR_INT * T0.Y, T0.Y, literal.x,355; EG-NEXT: 5231(7.330192e-42), 0(0.000000e+00)356; EG-NEXT: OR_INT T0.X, T0.X, literal.x,357; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,358; EG-NEXT: -545810305(-1.784115e+19), 2(2.802597e-45)359 %loada = load i64, ptr addrspace(1) %a, align 8360 %or = or i64 %loada, 22470723082367361 store i64 %or, ptr addrspace(1) %out362 ret void363}364 365; FIXME: The or 0 should really be removed.366define amdgpu_kernel void @vector_or_i64_imm(ptr addrspace(1) %out, ptr addrspace(1) %a, ptr addrspace(1) %b) {367; EG-LABEL: vector_or_i64_imm:368; EG: ; %bb.0:369; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]370; EG-NEXT: TEX 0 @6371; EG-NEXT: ALU 2, @9, KC0[CB0:0-32], KC1[]372; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1373; EG-NEXT: CF_END374; EG-NEXT: PAD375; EG-NEXT: Fetch clause starting at 6:376; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #1377; EG-NEXT: ALU clause starting at 8:378; EG-NEXT: MOV * T0.X, KC0[2].Z,379; EG-NEXT: ALU clause starting at 9:380; EG-NEXT: OR_INT T0.X, T0.X, literal.x,381; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,382; EG-NEXT: 8(1.121039e-44), 2(2.802597e-45)383 %loada = load i64, ptr addrspace(1) %a, align 8384 %or = or i64 %loada, 8385 store i64 %or, ptr addrspace(1) %out386 ret void387}388 389define amdgpu_kernel void @vector_or_i64_neg_inline_imm(ptr addrspace(1) %out, ptr addrspace(1) %a, ptr addrspace(1) %b) {390; EG-LABEL: vector_or_i64_neg_inline_imm:391; EG: ; %bb.0:392; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]393; EG-NEXT: TEX 0 @6394; EG-NEXT: ALU 4, @9, KC0[CB0:0-32], KC1[]395; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1396; EG-NEXT: CF_END397; EG-NEXT: PAD398; EG-NEXT: Fetch clause starting at 6:399; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1400; EG-NEXT: ALU clause starting at 8:401; EG-NEXT: MOV * T0.X, KC0[2].Z,402; EG-NEXT: ALU clause starting at 9:403; EG-NEXT: OR_INT T0.X, T0.X, literal.x,404; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,405; EG-NEXT: -8(nan), 2(2.802597e-45)406; EG-NEXT: MOV * T0.Y, literal.x,407; EG-NEXT: -1(nan), 0(0.000000e+00)408 %loada = load i64, ptr addrspace(1) %a, align 8409 %or = or i64 %loada, -8410 store i64 %or, ptr addrspace(1) %out411 ret void412}413 414define amdgpu_kernel void @vector_or_i64_neg_literal(ptr addrspace(1) %out, ptr addrspace(1) %a, ptr addrspace(1) %b) {415; EG-LABEL: vector_or_i64_neg_literal:416; EG: ; %bb.0:417; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]418; EG-NEXT: TEX 0 @6419; EG-NEXT: ALU 4, @9, KC0[CB0:0-32], KC1[]420; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1421; EG-NEXT: CF_END422; EG-NEXT: PAD423; EG-NEXT: Fetch clause starting at 6:424; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1425; EG-NEXT: ALU clause starting at 8:426; EG-NEXT: MOV * T0.X, KC0[2].Z,427; EG-NEXT: ALU clause starting at 9:428; EG-NEXT: OR_INT T0.X, T0.X, literal.x,429; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,430; EG-NEXT: -200(nan), 2(2.802597e-45)431; EG-NEXT: MOV * T0.Y, literal.x,432; EG-NEXT: -1(nan), 0(0.000000e+00)433 %loada = load i64, ptr addrspace(1) %a, align 8434 %or = or i64 %loada, -200435 store i64 %or, ptr addrspace(1) %out436 ret void437}438 439define amdgpu_kernel void @trunc_i64_or_to_i32(ptr addrspace(1) %out, [8 x i32], i64 %a, [8 x i32], i64 %b) {440; EG-LABEL: trunc_i64_or_to_i32:441; EG: ; %bb.0:442; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]443; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1444; EG-NEXT: CF_END445; EG-NEXT: PAD446; EG-NEXT: ALU clause starting at 4:447; EG-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,448; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)449; EG-NEXT: OR_INT * T1.X, KC0[7].Y, KC0[4].W,450 %add = or i64 %b, %a451 %trunc = trunc i64 %add to i32452 store i32 %trunc, ptr addrspace(1) %out, align 8453 ret void454}455 456define amdgpu_kernel void @or_i1(ptr addrspace(1) %out, ptr addrspace(1) %in0, ptr addrspace(1) %in1) {457; EG-LABEL: or_i1:458; EG: ; %bb.0:459; EG-NEXT: ALU 1, @10, KC0[CB0:0-32], KC1[]460; EG-NEXT: TEX 1 @6461; EG-NEXT: ALU 4, @12, KC0[CB0:0-32], KC1[]462; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1463; EG-NEXT: CF_END464; EG-NEXT: PAD465; EG-NEXT: Fetch clause starting at 6:466; EG-NEXT: VTX_READ_32 T1.X, T1.X, 0, #1467; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1468; EG-NEXT: ALU clause starting at 10:469; EG-NEXT: MOV T0.X, KC0[2].Z,470; EG-NEXT: MOV * T1.X, KC0[2].W,471; EG-NEXT: ALU clause starting at 12:472; EG-NEXT: MAX_DX10 * T0.W, T0.X, T1.X,473; EG-NEXT: SETGE_DX10 * T0.W, PV.W, 0.0,474; EG-NEXT: AND_INT T0.X, PV.W, 1,475; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,476; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)477 %a = load float, ptr addrspace(1) %in0478 %b = load float, ptr addrspace(1) %in1479 %acmp = fcmp oge float %a, 0.000000e+00480 %bcmp = fcmp oge float %b, 0.000000e+00481 %or = or i1 %acmp, %bcmp482 %result = zext i1 %or to i32483 store i32 %result, ptr addrspace(1) %out484 ret void485}486 487define amdgpu_kernel void @s_or_i1(ptr addrspace(1) %out, i32 %a, i32 %b, i32 %c, i32 %d) {488; EG-LABEL: s_or_i1:489; EG: ; %bb.0:490; EG-NEXT: ALU 14, @4, KC0[CB0:0-32], KC1[]491; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X492; EG-NEXT: CF_END493; EG-NEXT: PAD494; EG-NEXT: ALU clause starting at 4:495; EG-NEXT: SETE_INT T0.W, KC0[3].X, KC0[3].Y,496; EG-NEXT: SETE_INT * T1.W, KC0[2].Z, KC0[2].W,497; EG-NEXT: AND_INT T2.W, KC0[2].Y, literal.x,498; EG-NEXT: OR_INT * T0.W, PS, PV.W,499; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)500; EG-NEXT: AND_INT T0.W, PS, 1,501; EG-NEXT: LSHL * T1.W, PV.W, literal.x,502; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)503; EG-NEXT: LSHL T0.X, PV.W, PS,504; EG-NEXT: LSHL * T0.W, literal.x, PS,505; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)506; EG-NEXT: MOV T0.Y, 0.0,507; EG-NEXT: MOV * T0.Z, 0.0,508; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,509; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)510 %cmp0 = icmp eq i32 %a, %b511 %cmp1 = icmp eq i32 %c, %d512 %or = or i1 %cmp0, %cmp1513 store i1 %or, ptr addrspace(1) %out514 ret void515}516