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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=fiji | FileCheck -check-prefix=VI %s3; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx900 | FileCheck -check-prefix=GFX9 %s4; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 | FileCheck -check-prefix=GFX10 %s5; RUN: llc < %s -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 | FileCheck -check-prefix=GFX10 %s6 7; ===================================================================================8; V_OR3_B329; ===================================================================================10 11define amdgpu_ps float @or3(i32 %a, i32 %b, i32 %c) {12; VI-LABEL: or3:13; VI: ; %bb.0:14; VI-NEXT: v_or_b32_e32 v0, v0, v115; VI-NEXT: v_or_b32_e32 v0, v0, v216; VI-NEXT: ; return to shader part epilog17;18; GFX9-LABEL: or3:19; GFX9: ; %bb.0:20; GFX9-NEXT: v_or3_b32 v0, v0, v1, v221; GFX9-NEXT: ; return to shader part epilog22;23; GFX10-LABEL: or3:24; GFX10: ; %bb.0:25; GFX10-NEXT: v_or3_b32 v0, v0, v1, v226; GFX10-NEXT: ; return to shader part epilog27 %x = or i32 %a, %b28 %result = or i32 %x, %c29 %bc = bitcast i32 %result to float30 ret float %bc31}32 33; ThreeOp instruction variant not used due to Constant Bus Limitations34; TODO: with reassociation it is possible to replace a v_or_b32_e32 with an s_or_b3235define amdgpu_ps float @or3_vgpr_a(i32 %a, i32 inreg %b, i32 inreg %c) {36; VI-LABEL: or3_vgpr_a:37; VI: ; %bb.0:38; VI-NEXT: v_or_b32_e32 v0, s2, v039; VI-NEXT: v_or_b32_e32 v0, s3, v040; VI-NEXT: ; return to shader part epilog41;42; GFX9-LABEL: or3_vgpr_a:43; GFX9: ; %bb.0:44; GFX9-NEXT: v_or_b32_e32 v0, s2, v045; GFX9-NEXT: v_or_b32_e32 v0, s3, v046; GFX9-NEXT: ; return to shader part epilog47;48; GFX10-LABEL: or3_vgpr_a:49; GFX10: ; %bb.0:50; GFX10-NEXT: v_or3_b32 v0, v0, s2, s351; GFX10-NEXT: ; return to shader part epilog52 %x = or i32 %a, %b53 %result = or i32 %x, %c54 %bc = bitcast i32 %result to float55 ret float %bc56}57 58define amdgpu_ps float @or3_vgpr_all2(i32 %a, i32 %b, i32 %c) {59; VI-LABEL: or3_vgpr_all2:60; VI: ; %bb.0:61; VI-NEXT: v_or_b32_e32 v1, v1, v262; VI-NEXT: v_or_b32_e32 v0, v0, v163; VI-NEXT: ; return to shader part epilog64;65; GFX9-LABEL: or3_vgpr_all2:66; GFX9: ; %bb.0:67; GFX9-NEXT: v_or3_b32 v0, v1, v2, v068; GFX9-NEXT: ; return to shader part epilog69;70; GFX10-LABEL: or3_vgpr_all2:71; GFX10: ; %bb.0:72; GFX10-NEXT: v_or3_b32 v0, v1, v2, v073; GFX10-NEXT: ; return to shader part epilog74 %x = or i32 %b, %c75 %result = or i32 %a, %x76 %bc = bitcast i32 %result to float77 ret float %bc78}79 80define amdgpu_ps float @or3_vgpr_bc(i32 inreg %a, i32 %b, i32 %c) {81; VI-LABEL: or3_vgpr_bc:82; VI: ; %bb.0:83; VI-NEXT: v_or_b32_e32 v0, s2, v084; VI-NEXT: v_or_b32_e32 v0, v0, v185; VI-NEXT: ; return to shader part epilog86;87; GFX9-LABEL: or3_vgpr_bc:88; GFX9: ; %bb.0:89; GFX9-NEXT: v_or3_b32 v0, s2, v0, v190; GFX9-NEXT: ; return to shader part epilog91;92; GFX10-LABEL: or3_vgpr_bc:93; GFX10: ; %bb.0:94; GFX10-NEXT: v_or3_b32 v0, s2, v0, v195; GFX10-NEXT: ; return to shader part epilog96 %x = or i32 %a, %b97 %result = or i32 %x, %c98 %bc = bitcast i32 %result to float99 ret float %bc100}101 102define amdgpu_ps float @or3_vgpr_const(i32 %a, i32 %b) {103; VI-LABEL: or3_vgpr_const:104; VI: ; %bb.0:105; VI-NEXT: v_or_b32_e32 v0, v1, v0106; VI-NEXT: v_or_b32_e32 v0, 64, v0107; VI-NEXT: ; return to shader part epilog108;109; GFX9-LABEL: or3_vgpr_const:110; GFX9: ; %bb.0:111; GFX9-NEXT: v_or3_b32 v0, v1, v0, 64112; GFX9-NEXT: ; return to shader part epilog113;114; GFX10-LABEL: or3_vgpr_const:115; GFX10: ; %bb.0:116; GFX10-NEXT: v_or3_b32 v0, v1, v0, 64117; GFX10-NEXT: ; return to shader part epilog118 %x = or i32 64, %b119 %result = or i32 %x, %a120 %bc = bitcast i32 %result to float121 ret float %bc122}123