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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefix=GCN %s3 4define amdgpu_kernel void @fma_vector_vector_scalar_lo(ptr addrspace(1) %out, ptr addrspace(3) %lds, ptr addrspace(3) %arg2) #0 {5; GCN-LABEL: fma_vector_vector_scalar_lo:6; GCN: ; %bb.0: ; %bb7; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x248; GCN-NEXT: v_mov_b32_e32 v3, 09; GCN-NEXT: s_waitcnt lgkmcnt(0)10; GCN-NEXT: v_mov_b32_e32 v0, s611; GCN-NEXT: v_mov_b32_e32 v1, s712; GCN-NEXT: ds_read_b32 v2, v013; GCN-NEXT: ds_read_b32 v0, v0 offset:414; GCN-NEXT: ds_read_u16 v1, v115; GCN-NEXT: s_waitcnt lgkmcnt(0)16; GCN-NEXT: v_pk_fma_f16 v0, v2, v0, v1 op_sel_hi:[1,1,0]17; GCN-NEXT: global_store_dword v3, v0, s[4:5]18; GCN-NEXT: s_endpgm19bb:20 %lds.gep1 = getelementptr inbounds <2 x half>, ptr addrspace(3) %lds, i32 121 22 %vec0 = load volatile <2 x half>, ptr addrspace(3) %lds, align 423 %vec1 = load volatile <2 x half>, ptr addrspace(3) %lds.gep1, align 424 %scalar0 = load volatile half, ptr addrspace(3) %arg2, align 225 26 %scalar0.vec = insertelement <2 x half> poison, half %scalar0, i32 027 %scalar0.broadcast = shufflevector <2 x half> %scalar0.vec, <2 x half> poison, <2 x i32> zeroinitializer28 29 %result = tail call <2 x half> @llvm.fma.v2f16(<2 x half> %vec0, <2 x half> %vec1, <2 x half> %scalar0.broadcast)30 store <2 x half> %result, ptr addrspace(1) %out, align 431 ret void32}33 34; Apply fneg to broadcasted vector35define amdgpu_kernel void @fma_vector_vector_neg_broadcast_scalar_lo(ptr addrspace(1) %out, ptr addrspace(3) %lds, ptr addrspace(3) %arg2) #0 {36; GCN-LABEL: fma_vector_vector_neg_broadcast_scalar_lo:37; GCN: ; %bb.0: ; %bb38; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2439; GCN-NEXT: v_mov_b32_e32 v3, 040; GCN-NEXT: s_waitcnt lgkmcnt(0)41; GCN-NEXT: v_mov_b32_e32 v0, s642; GCN-NEXT: v_mov_b32_e32 v1, s743; GCN-NEXT: ds_read_b32 v2, v044; GCN-NEXT: ds_read_b32 v0, v0 offset:445; GCN-NEXT: ds_read_u16 v1, v146; GCN-NEXT: s_waitcnt lgkmcnt(0)47; GCN-NEXT: v_pk_fma_f16 v0, v2, v0, v1 op_sel_hi:[1,1,0] neg_lo:[0,0,1] neg_hi:[0,0,1]48; GCN-NEXT: global_store_dword v3, v0, s[4:5]49; GCN-NEXT: s_endpgm50bb:51 %lds.gep1 = getelementptr inbounds <2 x half>, ptr addrspace(3) %lds, i32 152 53 %vec0 = load volatile <2 x half>, ptr addrspace(3) %lds, align 454 %vec1 = load volatile <2 x half>, ptr addrspace(3) %lds.gep1, align 455 %scalar0 = load volatile half, ptr addrspace(3) %arg2, align 256 57 %scalar0.vec = insertelement <2 x half> poison, half %scalar0, i32 058 %scalar0.broadcast = shufflevector <2 x half> %scalar0.vec, <2 x half> poison, <2 x i32> zeroinitializer59 %neg.scalar0.broadcast = fsub <2 x half> <half -0.0, half -0.0>, %scalar0.broadcast60 61 %result = tail call <2 x half> @llvm.fma.v2f16(<2 x half> %vec0, <2 x half> %vec1, <2 x half> %neg.scalar0.broadcast)62 store <2 x half> %result, ptr addrspace(1) %out, align 463 ret void64}65 66; Apply fneg before broadcast67define amdgpu_kernel void @fma_vector_vector_neg_scalar_lo(ptr addrspace(1) %out, ptr addrspace(3) %lds, ptr addrspace(3) %arg2) #0 {68; GCN-LABEL: fma_vector_vector_neg_scalar_lo:69; GCN: ; %bb.0: ; %bb70; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2471; GCN-NEXT: v_mov_b32_e32 v3, 072; GCN-NEXT: s_waitcnt lgkmcnt(0)73; GCN-NEXT: v_mov_b32_e32 v0, s674; GCN-NEXT: v_mov_b32_e32 v1, s775; GCN-NEXT: ds_read_b32 v2, v076; GCN-NEXT: ds_read_b32 v0, v0 offset:477; GCN-NEXT: ds_read_u16 v1, v178; GCN-NEXT: s_waitcnt lgkmcnt(0)79; GCN-NEXT: v_pk_fma_f16 v0, v2, v0, v1 op_sel_hi:[1,1,0] neg_lo:[0,0,1] neg_hi:[0,0,1]80; GCN-NEXT: global_store_dword v3, v0, s[4:5]81; GCN-NEXT: s_endpgm82bb:83 %lds.gep1 = getelementptr inbounds <2 x half>, ptr addrspace(3) %lds, i32 184 85 %vec0 = load volatile <2 x half>, ptr addrspace(3) %lds, align 486 %vec1 = load volatile <2 x half>, ptr addrspace(3) %lds.gep1, align 487 %scalar0 = load volatile half, ptr addrspace(3) %arg2, align 288 89 %neg.scalar0 = fsub half -0.0, %scalar090 %neg.scalar0.vec = insertelement <2 x half> poison, half %neg.scalar0, i32 091 %neg.scalar0.broadcast = shufflevector <2 x half> %neg.scalar0.vec, <2 x half> poison, <2 x i32> zeroinitializer92 93 %result = tail call <2 x half> @llvm.fma.v2f16(<2 x half> %vec0, <2 x half> %vec1, <2 x half> %neg.scalar0.broadcast)94 store <2 x half> %result, ptr addrspace(1) %out, align 495 ret void96}97 98; Apply fneg before and after broadcast, and should cancel out.99define amdgpu_kernel void @fma_vector_vector_neg_broadcast_neg_scalar_lo(ptr addrspace(1) %out, ptr addrspace(3) %lds, ptr addrspace(3) %arg2) #0 {100; GCN-LABEL: fma_vector_vector_neg_broadcast_neg_scalar_lo:101; GCN: ; %bb.0: ; %bb102; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24103; GCN-NEXT: v_mov_b32_e32 v3, 0104; GCN-NEXT: s_waitcnt lgkmcnt(0)105; GCN-NEXT: v_mov_b32_e32 v0, s6106; GCN-NEXT: v_mov_b32_e32 v1, s7107; GCN-NEXT: ds_read_b32 v2, v0108; GCN-NEXT: ds_read_b32 v0, v0 offset:4109; GCN-NEXT: ds_read_u16 v1, v1110; GCN-NEXT: s_waitcnt lgkmcnt(0)111; GCN-NEXT: v_pk_fma_f16 v0, v2, v0, v1 op_sel_hi:[1,1,0]112; GCN-NEXT: global_store_dword v3, v0, s[4:5]113; GCN-NEXT: s_endpgm114bb:115 %lds.gep1 = getelementptr inbounds <2 x half>, ptr addrspace(3) %lds, i32 1116 117 %vec0 = load volatile <2 x half>, ptr addrspace(3) %lds, align 4118 %vec1 = load volatile <2 x half>, ptr addrspace(3) %lds.gep1, align 4119 %scalar0 = load volatile half, ptr addrspace(3) %arg2, align 2120 121 %neg.scalar0 = fsub half -0.0, %scalar0122 %neg.scalar0.vec = insertelement <2 x half> poison, half %neg.scalar0, i32 0123 %neg.scalar0.broadcast = shufflevector <2 x half> %neg.scalar0.vec, <2 x half> poison, <2 x i32> zeroinitializer124 %neg.neg.scalar0.broadcast = fsub <2 x half> <half -0.0, half -0.0>, %neg.scalar0.broadcast125 126 %result = tail call <2 x half> @llvm.fma.v2f16(<2 x half> %vec0, <2 x half> %vec1, <2 x half> %neg.neg.scalar0.broadcast)127 store <2 x half> %result, ptr addrspace(1) %out, align 4128 ret void129}130 131; Add scalar, but negate low component132define amdgpu_kernel void @fma_vector_vector_scalar_neg_lo(ptr addrspace(1) %out, ptr addrspace(3) %lds, ptr addrspace(3) %arg2) #0 {133; GCN-LABEL: fma_vector_vector_scalar_neg_lo:134; GCN: ; %bb.0: ; %bb135; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24136; GCN-NEXT: v_mov_b32_e32 v3, 0137; GCN-NEXT: s_waitcnt lgkmcnt(0)138; GCN-NEXT: v_mov_b32_e32 v0, s6139; GCN-NEXT: v_mov_b32_e32 v1, s7140; GCN-NEXT: ds_read_b32 v2, v0141; GCN-NEXT: ds_read_b32 v0, v0 offset:4142; GCN-NEXT: ds_read_u16 v1, v1143; GCN-NEXT: s_waitcnt lgkmcnt(0)144; GCN-NEXT: v_pk_fma_f16 v0, v2, v0, v1 op_sel_hi:[1,1,0] neg_lo:[0,0,1]145; GCN-NEXT: global_store_dword v3, v0, s[4:5]146; GCN-NEXT: s_endpgm147bb:148 %lds.gep1 = getelementptr inbounds <2 x half>, ptr addrspace(3) %lds, i32 1149 150 %vec0 = load volatile <2 x half>, ptr addrspace(3) %lds, align 4151 %vec1 = load volatile <2 x half>, ptr addrspace(3) %lds.gep1, align 4152 %scalar0 = load volatile half, ptr addrspace(3) %arg2, align 2153 154 %neg.scalar0 = fsub half -0.0, %scalar0155 %neg.scalar0.vec = insertelement <2 x half> poison, half %neg.scalar0, i32 0156 %neg.scalar0.scalar0 = insertelement <2 x half> %neg.scalar0.vec, half %scalar0, i32 1157 %result = tail call <2 x half> @llvm.fma.v2f16(<2 x half> %vec0, <2 x half> %vec1, <2 x half> %neg.scalar0.scalar0)158 store <2 x half> %result, ptr addrspace(1) %out, align 4159 ret void160}161 162; Add scalar, but negate high component163define amdgpu_kernel void @fma_vector_vector_scalar_neg_hi(ptr addrspace(1) %out, ptr addrspace(3) %lds, ptr addrspace(3) %arg2) #0 {164; GCN-LABEL: fma_vector_vector_scalar_neg_hi:165; GCN: ; %bb.0: ; %bb166; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24167; GCN-NEXT: v_mov_b32_e32 v3, 0168; GCN-NEXT: s_waitcnt lgkmcnt(0)169; GCN-NEXT: v_mov_b32_e32 v0, s6170; GCN-NEXT: v_mov_b32_e32 v1, s7171; GCN-NEXT: ds_read_b32 v2, v0172; GCN-NEXT: ds_read_b32 v0, v0 offset:4173; GCN-NEXT: ds_read_u16 v1, v1174; GCN-NEXT: s_waitcnt lgkmcnt(0)175; GCN-NEXT: v_pk_fma_f16 v0, v2, v0, v1 op_sel_hi:[1,1,0] neg_hi:[0,0,1]176; GCN-NEXT: global_store_dword v3, v0, s[4:5]177; GCN-NEXT: s_endpgm178bb:179 %lds.gep1 = getelementptr inbounds <2 x half>, ptr addrspace(3) %lds, i32 1180 181 %vec0 = load volatile <2 x half>, ptr addrspace(3) %lds, align 4182 %vec1 = load volatile <2 x half>, ptr addrspace(3) %lds.gep1, align 4183 %scalar0 = load volatile half, ptr addrspace(3) %arg2, align 2184 185 %neg.scalar0 = fsub half -0.0, %scalar0186 %neg.scalar0.vec = insertelement <2 x half> poison, half %scalar0, i32 0187 %scalar0.neg.scalar0 = insertelement <2 x half> %neg.scalar0.vec, half %neg.scalar0, i32 1188 %result = tail call <2 x half> @llvm.fma.v2f16(<2 x half> %vec0, <2 x half> %vec1, <2 x half> %scalar0.neg.scalar0)189 store <2 x half> %result, ptr addrspace(1) %out, align 4190 ret void191}192 193; Apply fneg before broadcast with bitcast194define amdgpu_kernel void @add_vector_neg_bitcast_scalar_lo(ptr addrspace(1) %out, ptr addrspace(3) %lds, ptr addrspace(3) %arg2) #0 {195; GCN-LABEL: add_vector_neg_bitcast_scalar_lo:196; GCN: ; %bb.0: ; %bb197; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24198; GCN-NEXT: v_mov_b32_e32 v2, 0199; GCN-NEXT: s_waitcnt lgkmcnt(0)200; GCN-NEXT: v_mov_b32_e32 v0, s6201; GCN-NEXT: v_mov_b32_e32 v1, s7202; GCN-NEXT: ds_read_b32 v0, v0203; GCN-NEXT: ds_read_u16 v1, v1204; GCN-NEXT: s_waitcnt lgkmcnt(0)205; GCN-NEXT: v_pk_add_u16 v0, v0, v1 op_sel_hi:[1,0] neg_lo:[0,1] neg_hi:[0,1]206; GCN-NEXT: global_store_dword v2, v0, s[4:5]207; GCN-NEXT: s_endpgm208bb:209 %vec0 = load volatile <2 x i16>, ptr addrspace(3) %lds, align 4210 %scalar0 = load volatile half, ptr addrspace(3) %arg2, align 2211 %neg.scalar0 = fsub half -0.0, %scalar0212 %neg.scalar0.bc = bitcast half %neg.scalar0 to i16213 214 %neg.scalar0.vec = insertelement <2 x i16> poison, i16 %neg.scalar0.bc, i32 0215 %neg.scalar0.broadcast = shufflevector <2 x i16> %neg.scalar0.vec, <2 x i16> poison, <2 x i32> zeroinitializer216 217 %result = add <2 x i16> %vec0, %neg.scalar0.broadcast218 store <2 x i16> %result, ptr addrspace(1) %out, align 4219 ret void220}221 222define amdgpu_kernel void @fma_vector_vector_scalar_lo_neg_scalar_hi(ptr addrspace(1) %out, ptr addrspace(3) %lds, ptr addrspace(3) %arg2) #0 {223; GCN-LABEL: fma_vector_vector_scalar_lo_neg_scalar_hi:224; GCN: ; %bb.0: ; %bb225; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24226; GCN-NEXT: v_mov_b32_e32 v4, 0227; GCN-NEXT: s_waitcnt lgkmcnt(0)228; GCN-NEXT: v_mov_b32_e32 v0, s6229; GCN-NEXT: v_mov_b32_e32 v1, s7230; GCN-NEXT: ds_read_b32 v2, v0231; GCN-NEXT: ds_read_b32 v0, v0 offset:4232; GCN-NEXT: ds_read_u16 v3, v1233; GCN-NEXT: ds_read_u16 v1, v1 offset:4234; GCN-NEXT: s_waitcnt lgkmcnt(1)235; GCN-NEXT: v_and_b32_e32 v3, 0xffff, v3236; GCN-NEXT: s_waitcnt lgkmcnt(0)237; GCN-NEXT: v_xor_b32_e32 v1, 0x8000, v1238; GCN-NEXT: v_lshl_or_b32 v1, v1, 16, v3239; GCN-NEXT: v_pk_fma_f16 v0, v2, v0, v1240; GCN-NEXT: global_store_dword v4, v0, s[4:5]241; GCN-NEXT: s_endpgm242bb:243 %lds.gep1 = getelementptr inbounds <2 x half>, ptr addrspace(3) %lds, i32 1244 %arg2.gep = getelementptr inbounds half, ptr addrspace(3) %arg2, i32 2245 246 %vec0 = load volatile <2 x half>, ptr addrspace(3) %lds, align 4247 %vec1 = load volatile <2 x half>, ptr addrspace(3) %lds.gep1, align 4248 249 %scalar0 = load volatile half, ptr addrspace(3) %arg2, align 2250 %scalar1 = load volatile half, ptr addrspace(3) %arg2.gep, align 2251 252 %neg.scalar1 = fsub half -0.0, %scalar1253 %vec.ins0 = insertelement <2 x half> poison, half %scalar0, i32 0254 %vec2 = insertelement <2 x half> %vec.ins0, half %neg.scalar1, i32 1255 %result = tail call <2 x half> @llvm.fma.v2f16(<2 x half> %vec0, <2 x half> %vec1, <2 x half> %vec2)256 store <2 x half> %result, ptr addrspace(1) %out, align 4257 ret void258}259 260; FIXME: Can we avoid waitcnt between the two halves?261define amdgpu_kernel void @fma_vector_vector_neg_scalar_lo_scalar_hi(ptr addrspace(1) %out, ptr addrspace(3) %lds, ptr addrspace(3) %arg2) #0 {262; GCN-LABEL: fma_vector_vector_neg_scalar_lo_scalar_hi:263; GCN: ; %bb.0: ; %bb264; GCN-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24265; GCN-NEXT: s_waitcnt lgkmcnt(0)266; GCN-NEXT: v_mov_b32_e32 v0, s6267; GCN-NEXT: v_mov_b32_e32 v1, s7268; GCN-NEXT: ds_read_b32 v2, v0269; GCN-NEXT: ds_read_b32 v0, v0 offset:4270; GCN-NEXT: ds_read_u16 v3, v1271; GCN-NEXT: s_waitcnt lgkmcnt(0)272; GCN-NEXT: ds_read_u16_d16_hi v3, v1 offset:4273; GCN-NEXT: v_mov_b32_e32 v1, 0274; GCN-NEXT: s_waitcnt lgkmcnt(0)275; GCN-NEXT: v_pk_fma_f16 v0, v2, v0, v3 neg_lo:[0,0,1] neg_hi:[0,0,1]276; GCN-NEXT: global_store_dword v1, v0, s[4:5]277; GCN-NEXT: s_endpgm278bb:279 %lds.gep1 = getelementptr inbounds <2 x half>, ptr addrspace(3) %lds, i32 1280 %arg2.gep = getelementptr inbounds half, ptr addrspace(3) %arg2, i32 2281 282 %vec0 = load volatile <2 x half>, ptr addrspace(3) %lds, align 4283 %vec1 = load volatile <2 x half>, ptr addrspace(3) %lds.gep1, align 4284 285 %scalar0 = load volatile half, ptr addrspace(3) %arg2, align 2286 %scalar1 = load volatile half, ptr addrspace(3) %arg2.gep, align 2287 288 %vec.ins0 = insertelement <2 x half> poison, half %scalar0, i32 0289 %vec2 = insertelement <2 x half> %vec.ins0, half %scalar1, i32 1290 %neg.vec2 = fsub <2 x half> <half -0.0, half -0.0>, %vec2291 292 %result = tail call <2 x half> @llvm.fma.v2f16(<2 x half> %vec0, <2 x half> %vec1, <2 x half> %neg.vec2)293 store <2 x half> %result, ptr addrspace(1) %out, align 4294 ret void295}296 297define amdgpu_kernel void @fma_vector_vector_neg_vector_hi(ptr addrspace(1) %out, ptr addrspace(3) %lds) #0 {298; GCN-LABEL: fma_vector_vector_neg_vector_hi:299; GCN: ; %bb.0: ; %bb300; GCN-NEXT: s_load_dword s2, s[0:1], 0x2c301; GCN-NEXT: v_mov_b32_e32 v3, 0302; GCN-NEXT: s_waitcnt lgkmcnt(0)303; GCN-NEXT: v_mov_b32_e32 v0, s2304; GCN-NEXT: ds_read_b32 v1, v0305; GCN-NEXT: ds_read_b32 v2, v0 offset:4306; GCN-NEXT: ds_read_b32 v0, v0 offset:8307; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24308; GCN-NEXT: s_waitcnt lgkmcnt(0)309; GCN-NEXT: v_pk_fma_f16 v0, v1, v2, v0 op_sel:[0,0,1] neg_lo:[0,0,1] neg_hi:[0,0,1]310; GCN-NEXT: global_store_dword v3, v0, s[2:3]311; GCN-NEXT: s_endpgm312bb:313 %lds.gep1 = getelementptr inbounds <2 x half>, ptr addrspace(3) %lds, i32 1314 %lds.gep2 = getelementptr inbounds <2 x half>, ptr addrspace(3) %lds, i32 2315 316 %vec0 = load volatile <2 x half>, ptr addrspace(3) %lds, align 4317 %vec1 = load volatile <2 x half>, ptr addrspace(3) %lds.gep1, align 4318 %vec2 = load volatile <2 x half>, ptr addrspace(3) %lds.gep2, align 4319 320 %vec2.fneg = fsub <2 x half> <half -0.0, half -0.0>, %vec2321 %vec2.fneg.elt1.broadcast = shufflevector <2 x half> %vec2.fneg, <2 x half> poison, <2 x i32> <i32 1, i32 1>322 323 %result = tail call <2 x half> @llvm.fma.v2f16(<2 x half> %vec0, <2 x half> %vec1, <2 x half> %vec2.fneg.elt1.broadcast)324 store <2 x half> %result, ptr addrspace(1) %out, align 4325 ret void326}327 328define amdgpu_kernel void @fma_vector_vector_vector_neg_hi(ptr addrspace(1) %out, ptr addrspace(3) %lds) #0 {329; GCN-LABEL: fma_vector_vector_vector_neg_hi:330; GCN: ; %bb.0: ; %bb331; GCN-NEXT: s_load_dword s2, s[0:1], 0x2c332; GCN-NEXT: v_mov_b32_e32 v3, 0333; GCN-NEXT: s_waitcnt lgkmcnt(0)334; GCN-NEXT: v_mov_b32_e32 v0, s2335; GCN-NEXT: ds_read_b32 v1, v0336; GCN-NEXT: ds_read_b32 v2, v0 offset:4337; GCN-NEXT: ds_read_b32 v0, v0 offset:8338; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24339; GCN-NEXT: s_waitcnt lgkmcnt(0)340; GCN-NEXT: v_pk_fma_f16 v0, v1, v2, v0 neg_hi:[0,0,1]341; GCN-NEXT: global_store_dword v3, v0, s[2:3]342; GCN-NEXT: s_endpgm343bb:344 %lds.gep1 = getelementptr inbounds <2 x half>, ptr addrspace(3) %lds, i32 1345 %lds.gep2 = getelementptr inbounds <2 x half>, ptr addrspace(3) %lds, i32 2346 347 %vec0 = load volatile <2 x half>, ptr addrspace(3) %lds, align 4348 %vec1 = load volatile <2 x half>, ptr addrspace(3) %lds.gep1, align 4349 %vec2 = load volatile <2 x half>, ptr addrspace(3) %lds.gep2, align 4350 351 %vec2.elt1 = extractelement <2 x half> %vec2, i32 1352 %neg.vec2.elt1 = fsub half -0.0, %vec2.elt1353 354 %neg.vec2.elt1.insert = insertelement <2 x half> %vec2, half %neg.vec2.elt1, i32 1355 %result = tail call <2 x half> @llvm.fma.v2f16(<2 x half> %vec0, <2 x half> %vec1, <2 x half> %neg.vec2.elt1.insert)356 store <2 x half> %result, ptr addrspace(1) %out, align 4357 ret void358}359 360define amdgpu_kernel void @add_vector_scalar_hi(ptr addrspace(1) %out, ptr addrspace(3) %lds) #0 {361; GCN-LABEL: add_vector_scalar_hi:362; GCN: ; %bb.0: ; %bb363; GCN-NEXT: s_load_dword s2, s[0:1], 0x2c364; GCN-NEXT: v_mov_b32_e32 v2, 0365; GCN-NEXT: s_waitcnt lgkmcnt(0)366; GCN-NEXT: v_mov_b32_e32 v0, s2367; GCN-NEXT: ds_read_b32 v1, v0368; GCN-NEXT: ds_read_b32 v0, v0 offset:4369; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24370; GCN-NEXT: s_waitcnt lgkmcnt(0)371; GCN-NEXT: v_pk_add_u16 v0, v1, v0 op_sel:[0,1]372; GCN-NEXT: global_store_dword v2, v0, s[2:3]373; GCN-NEXT: s_endpgm374bb:375 %lds.gep1 = getelementptr inbounds <2 x i16>, ptr addrspace(3) %lds, i32 1376 377 %vec0 = load volatile <2 x i16>, ptr addrspace(3) %lds, align 4378 %vec1 = load volatile <2 x i16>, ptr addrspace(3) %lds.gep1, align 4379 380 %vec1.elt1.broadcast = shufflevector <2 x i16> %vec1, <2 x i16> poison, <2 x i32> <i32 1, i32 1>381 %result = add <2 x i16> %vec0, %vec1.elt1.broadcast382 383 store <2 x i16> %result, ptr addrspace(1) %out, align 4384 ret void385}386 387define amdgpu_kernel void @fma_vector_vector_scalar_hi(ptr addrspace(1) %out, ptr addrspace(3) %lds) #0 {388; GCN-LABEL: fma_vector_vector_scalar_hi:389; GCN: ; %bb.0: ; %bb390; GCN-NEXT: s_load_dword s2, s[0:1], 0x2c391; GCN-NEXT: v_mov_b32_e32 v3, 0392; GCN-NEXT: s_waitcnt lgkmcnt(0)393; GCN-NEXT: v_mov_b32_e32 v0, s2394; GCN-NEXT: ds_read_b32 v1, v0395; GCN-NEXT: ds_read_b32 v2, v0 offset:4396; GCN-NEXT: ds_read_b32 v0, v0 offset:8397; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24398; GCN-NEXT: s_waitcnt lgkmcnt(0)399; GCN-NEXT: v_pk_fma_f16 v0, v1, v2, v0 op_sel:[0,0,1]400; GCN-NEXT: global_store_dword v3, v0, s[2:3]401; GCN-NEXT: s_endpgm402bb:403 %lds.gep1 = getelementptr inbounds <2 x half>, ptr addrspace(3) %lds, i32 1404 %lds.gep2 = getelementptr inbounds <2 x half>, ptr addrspace(3) %lds, i32 2405 406 %vec0 = load volatile <2 x half>, ptr addrspace(3) %lds, align 4407 %vec1 = load volatile <2 x half>, ptr addrspace(3) %lds.gep1, align 4408 %vec2 = load volatile <2 x half>, ptr addrspace(3) %lds.gep2, align 4409 410 %vec2.elt1.broadcast = shufflevector <2 x half> %vec2, <2 x half> poison, <2 x i32> <i32 1, i32 1>411 412 %result = tail call <2 x half> @llvm.fma.v2f16(<2 x half> %vec0, <2 x half> %vec1, <2 x half> %vec2.elt1.broadcast)413 414 store <2 x half> %result, ptr addrspace(1) %out, align 4415 ret void416}417 418define amdgpu_kernel void @fma_vector_vector_neg_vector_lo_neg_hi(ptr addrspace(1) %out, ptr addrspace(3) %lds) #0 {419; GCN-LABEL: fma_vector_vector_neg_vector_lo_neg_hi:420; GCN: ; %bb.0: ; %bb421; GCN-NEXT: s_load_dword s2, s[0:1], 0x2c422; GCN-NEXT: v_mov_b32_e32 v3, 0423; GCN-NEXT: s_waitcnt lgkmcnt(0)424; GCN-NEXT: v_mov_b32_e32 v0, s2425; GCN-NEXT: ds_read_b32 v1, v0426; GCN-NEXT: ds_read_b32 v2, v0 offset:4427; GCN-NEXT: ds_read_b32 v0, v0 offset:8428; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24429; GCN-NEXT: s_waitcnt lgkmcnt(0)430; GCN-NEXT: v_pk_fma_f16 v0, v1, v2, v0431; GCN-NEXT: global_store_dword v3, v0, s[2:3]432; GCN-NEXT: s_endpgm433bb:434 %lds.gep1 = getelementptr inbounds <2 x half>, ptr addrspace(3) %lds, i32 1435 %lds.gep2 = getelementptr inbounds <2 x half>, ptr addrspace(3) %lds, i32 2436 437 %vec0 = load volatile <2 x half>, ptr addrspace(3) %lds, align 4438 %vec1 = load volatile <2 x half>, ptr addrspace(3) %lds.gep1, align 4439 %vec2 = load volatile <2 x half>, ptr addrspace(3) %lds.gep2, align 4440 441 %neg.vec2 = fsub <2 x half> <half -0.0, half -0.0>, %vec2442 %neg.vec2.elt1 = extractelement <2 x half> %neg.vec2, i32 1443 %neg.neg.vec2.elt1 = fsub half -0.0, %neg.vec2.elt1444 %neg.neg.vec2.elt1.insert = insertelement <2 x half> %vec2, half %neg.neg.vec2.elt1, i32 1445 446 %result = tail call <2 x half> @llvm.fma.v2f16(<2 x half> %vec0, <2 x half> %vec1, <2 x half> %neg.neg.vec2.elt1.insert)447 store <2 x half> %result, ptr addrspace(1) %out, align 4448 ret void449}450 451define amdgpu_kernel void @fma_vector_vector_swap_vector(ptr addrspace(1) %out, ptr addrspace(3) %lds) #0 {452; GCN-LABEL: fma_vector_vector_swap_vector:453; GCN: ; %bb.0: ; %bb454; GCN-NEXT: s_load_dword s2, s[0:1], 0x2c455; GCN-NEXT: v_mov_b32_e32 v3, 0456; GCN-NEXT: s_waitcnt lgkmcnt(0)457; GCN-NEXT: v_mov_b32_e32 v0, s2458; GCN-NEXT: ds_read_b32 v1, v0459; GCN-NEXT: ds_read_b32 v2, v0 offset:4460; GCN-NEXT: ds_read_b32 v0, v0 offset:8461; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24462; GCN-NEXT: s_waitcnt lgkmcnt(0)463; GCN-NEXT: v_pk_fma_f16 v0, v1, v2, v0 op_sel:[0,0,1] op_sel_hi:[1,1,0]464; GCN-NEXT: global_store_dword v3, v0, s[2:3]465; GCN-NEXT: s_endpgm466bb:467 %lds.gep1 = getelementptr inbounds <2 x half>, ptr addrspace(3) %lds, i32 1468 %lds.gep2 = getelementptr inbounds <2 x half>, ptr addrspace(3) %lds, i32 2469 470 %vec0 = load volatile <2 x half>, ptr addrspace(3) %lds, align 4471 %vec1 = load volatile <2 x half>, ptr addrspace(3) %lds.gep1, align 4472 %vec2 = load volatile <2 x half>, ptr addrspace(3) %lds.gep2, align 4473 474 %vec2.swap = shufflevector <2 x half> %vec2, <2 x half> poison, <2 x i32> <i32 1, i32 0>475 %result = tail call <2 x half> @llvm.fma.v2f16(<2 x half> %vec0, <2 x half> %vec1, <2 x half> %vec2.swap)476 477 store <2 x half> %result, ptr addrspace(1) %out, align 4478 ret void479}480 481define amdgpu_kernel void @fma_vector_vector_swap_neg_vector(ptr addrspace(1) %out, ptr addrspace(3) %lds) #0 {482; GCN-LABEL: fma_vector_vector_swap_neg_vector:483; GCN: ; %bb.0: ; %bb484; GCN-NEXT: s_load_dword s2, s[0:1], 0x2c485; GCN-NEXT: v_mov_b32_e32 v3, 0486; GCN-NEXT: s_waitcnt lgkmcnt(0)487; GCN-NEXT: v_mov_b32_e32 v0, s2488; GCN-NEXT: ds_read_b32 v1, v0489; GCN-NEXT: ds_read_b32 v2, v0 offset:4490; GCN-NEXT: ds_read_b32 v0, v0 offset:8491; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24492; GCN-NEXT: s_waitcnt lgkmcnt(0)493; GCN-NEXT: v_pk_fma_f16 v0, v1, v2, v0 op_sel:[0,0,1] op_sel_hi:[1,1,0] neg_lo:[0,0,1] neg_hi:[0,0,1]494; GCN-NEXT: global_store_dword v3, v0, s[2:3]495; GCN-NEXT: s_endpgm496bb:497 %lds.gep1 = getelementptr inbounds <2 x half>, ptr addrspace(3) %lds, i32 1498 %lds.gep2 = getelementptr inbounds <2 x half>, ptr addrspace(3) %lds, i32 2499 500 %vec0 = load volatile <2 x half>, ptr addrspace(3) %lds, align 4501 %vec1 = load volatile <2 x half>, ptr addrspace(3) %lds.gep1, align 4502 %vec2 = load volatile <2 x half>, ptr addrspace(3) %lds.gep2, align 4503 %neg.vec2 = fsub <2 x half> <half -0.0, half -0.0>, %vec2504 505 %neg.vec2.swap = shufflevector <2 x half> %neg.vec2, <2 x half> poison, <2 x i32> <i32 1, i32 0>506 %result = tail call <2 x half> @llvm.fma.v2f16(<2 x half> %vec0, <2 x half> %vec1, <2 x half> %neg.vec2.swap)507 508 store <2 x half> %result, ptr addrspace(1) %out, align 4509 ret void510}511 512define amdgpu_kernel void @fma_vector_vector_blend_vector_neg_vector_0(ptr addrspace(1) %out, ptr addrspace(3) %lds) #0 {513; GCN-LABEL: fma_vector_vector_blend_vector_neg_vector_0:514; GCN: ; %bb.0: ; %bb515; GCN-NEXT: s_load_dword s2, s[0:1], 0x2c516; GCN-NEXT: v_mov_b32_e32 v3, 0517; GCN-NEXT: s_waitcnt lgkmcnt(0)518; GCN-NEXT: v_mov_b32_e32 v0, s2519; GCN-NEXT: ds_read_b32 v1, v0520; GCN-NEXT: ds_read_b32 v2, v0 offset:4521; GCN-NEXT: ds_read_b32 v0, v0 offset:8522; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24523; GCN-NEXT: s_waitcnt lgkmcnt(0)524; GCN-NEXT: v_pk_fma_f16 v0, v1, v2, v0 op_sel:[0,0,1] op_sel_hi:[1,1,0] neg_lo:[0,0,1]525; GCN-NEXT: global_store_dword v3, v0, s[2:3]526; GCN-NEXT: s_endpgm527bb:528 %lds.gep1 = getelementptr inbounds <2 x half>, ptr addrspace(3) %lds, i32 1529 %lds.gep2 = getelementptr inbounds <2 x half>, ptr addrspace(3) %lds, i32 2530 531 %vec0 = load volatile <2 x half>, ptr addrspace(3) %lds, align 4532 %vec1 = load volatile <2 x half>, ptr addrspace(3) %lds.gep1, align 4533 %vec2 = load volatile <2 x half>, ptr addrspace(3) %lds.gep2, align 4534 %neg.vec2 = fsub <2 x half> <half -0.0, half -0.0>, %vec2535 %combined = shufflevector <2 x half> %vec2, <2 x half> %neg.vec2, <2 x i32> <i32 3, i32 0>536 %result = tail call <2 x half> @llvm.fma.v2f16(<2 x half> %vec0, <2 x half> %vec1, <2 x half> %combined)537 538 store <2 x half> %result, ptr addrspace(1) %out, align 4539 ret void540}541 542define amdgpu_kernel void @fma_vector_vector_blend_vector_neg_vector_1(ptr addrspace(1) %out, ptr addrspace(3) %lds) #0 {543; GCN-LABEL: fma_vector_vector_blend_vector_neg_vector_1:544; GCN: ; %bb.0: ; %bb545; GCN-NEXT: s_load_dword s2, s[0:1], 0x2c546; GCN-NEXT: v_mov_b32_e32 v3, 0547; GCN-NEXT: s_waitcnt lgkmcnt(0)548; GCN-NEXT: v_mov_b32_e32 v0, s2549; GCN-NEXT: ds_read_b32 v1, v0550; GCN-NEXT: ds_read_b32 v2, v0 offset:4551; GCN-NEXT: ds_read_b32 v0, v0 offset:8552; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24553; GCN-NEXT: s_waitcnt lgkmcnt(0)554; GCN-NEXT: v_pk_fma_f16 v0, v1, v2, v0 neg_lo:[0,0,1]555; GCN-NEXT: global_store_dword v3, v0, s[2:3]556; GCN-NEXT: s_endpgm557bb:558 %lds.gep1 = getelementptr inbounds <2 x half>, ptr addrspace(3) %lds, i32 1559 %lds.gep2 = getelementptr inbounds <2 x half>, ptr addrspace(3) %lds, i32 2560 561 %vec0 = load volatile <2 x half>, ptr addrspace(3) %lds, align 4562 %vec1 = load volatile <2 x half>, ptr addrspace(3) %lds.gep1, align 4563 %vec2 = load volatile <2 x half>, ptr addrspace(3) %lds.gep2, align 4564 %neg.vec2 = fsub <2 x half> <half -0.0, half -0.0>, %vec2565 %combined = shufflevector <2 x half> %vec2, <2 x half> %neg.vec2, <2 x i32> <i32 2, i32 1>566 %result = tail call <2 x half> @llvm.fma.v2f16(<2 x half> %vec0, <2 x half> %vec1, <2 x half> %combined)567 568 store <2 x half> %result, ptr addrspace(1) %out, align 4569 ret void570}571 572define amdgpu_kernel void @fma_vector_vector_blend_vector_neg_vector_2(ptr addrspace(1) %out, ptr addrspace(3) %lds) #0 {573; GCN-LABEL: fma_vector_vector_blend_vector_neg_vector_2:574; GCN: ; %bb.0: ; %bb575; GCN-NEXT: s_load_dword s2, s[0:1], 0x2c576; GCN-NEXT: v_mov_b32_e32 v3, 0577; GCN-NEXT: s_waitcnt lgkmcnt(0)578; GCN-NEXT: v_mov_b32_e32 v0, s2579; GCN-NEXT: ds_read_b32 v1, v0580; GCN-NEXT: ds_read_b32 v2, v0 offset:4581; GCN-NEXT: ds_read_b32 v0, v0 offset:8582; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24583; GCN-NEXT: s_waitcnt lgkmcnt(0)584; GCN-NEXT: v_pk_fma_f16 v0, v1, v2, v0 neg_hi:[0,0,1]585; GCN-NEXT: global_store_dword v3, v0, s[2:3]586; GCN-NEXT: s_endpgm587bb:588 %lds.gep1 = getelementptr inbounds <2 x half>, ptr addrspace(3) %lds, i32 1589 %lds.gep2 = getelementptr inbounds <2 x half>, ptr addrspace(3) %lds, i32 2590 591 %vec0 = load volatile <2 x half>, ptr addrspace(3) %lds, align 4592 %vec1 = load volatile <2 x half>, ptr addrspace(3) %lds.gep1, align 4593 %vec2 = load volatile <2 x half>, ptr addrspace(3) %lds.gep2, align 4594 %neg.vec2 = fsub <2 x half> <half -0.0, half -0.0>, %vec2595 %combined = shufflevector <2 x half> %vec2, <2 x half> %neg.vec2, <2 x i32> <i32 0, i32 3>596 %result = tail call <2 x half> @llvm.fma.v2f16(<2 x half> %vec0, <2 x half> %vec1, <2 x half> %combined)597 598 store <2 x half> %result, ptr addrspace(1) %out, align 4599 ret void600}601 602define amdgpu_kernel void @fma_vector_vector_blend_vector_neg_vector_3(ptr addrspace(1) %out, ptr addrspace(3) %lds) #0 {603; GCN-LABEL: fma_vector_vector_blend_vector_neg_vector_3:604; GCN: ; %bb.0: ; %bb605; GCN-NEXT: s_load_dword s2, s[0:1], 0x2c606; GCN-NEXT: v_mov_b32_e32 v3, 0607; GCN-NEXT: s_waitcnt lgkmcnt(0)608; GCN-NEXT: v_mov_b32_e32 v0, s2609; GCN-NEXT: ds_read_b32 v1, v0610; GCN-NEXT: ds_read_b32 v2, v0 offset:4611; GCN-NEXT: ds_read_b32 v0, v0 offset:8612; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24613; GCN-NEXT: s_waitcnt lgkmcnt(0)614; GCN-NEXT: v_pk_fma_f16 v0, v1, v2, v0 op_sel:[0,0,1] neg_lo:[0,0,1]615; GCN-NEXT: global_store_dword v3, v0, s[2:3]616; GCN-NEXT: s_endpgm617bb:618 %lds.gep1 = getelementptr inbounds <2 x half>, ptr addrspace(3) %lds, i32 1619 %lds.gep2 = getelementptr inbounds <2 x half>, ptr addrspace(3) %lds, i32 2620 621 %vec0 = load volatile <2 x half>, ptr addrspace(3) %lds, align 4622 %vec1 = load volatile <2 x half>, ptr addrspace(3) %lds.gep1, align 4623 %vec2 = load volatile <2 x half>, ptr addrspace(3) %lds.gep2, align 4624 %neg.vec2 = fsub <2 x half> <half -0.0, half -0.0>, %vec2625 %combined = shufflevector <2 x half> %vec2, <2 x half> %neg.vec2, <2 x i32> <i32 3, i32 1>626 %result = tail call <2 x half> @llvm.fma.v2f16(<2 x half> %vec0, <2 x half> %vec1, <2 x half> %combined)627 628 store <2 x half> %result, ptr addrspace(1) %out, align 4629 ret void630}631 632define amdgpu_kernel void @bitcast_fneg_f32(ptr addrspace(1) %out, ptr addrspace(3) %lds) #0 {633; GCN-LABEL: bitcast_fneg_f32:634; GCN: ; %bb.0: ; %bb635; GCN-NEXT: s_load_dword s2, s[0:1], 0x2c636; GCN-NEXT: v_mov_b32_e32 v2, 0637; GCN-NEXT: s_waitcnt lgkmcnt(0)638; GCN-NEXT: v_mov_b32_e32 v0, s2639; GCN-NEXT: ds_read_b32 v0, v0640; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24641; GCN-NEXT: s_waitcnt lgkmcnt(0)642; GCN-NEXT: ds_read_b32 v1, v0643; GCN-NEXT: s_waitcnt lgkmcnt(0)644; GCN-NEXT: v_xor_b32_e32 v1, 0x80000000, v1645; GCN-NEXT: v_pk_add_f16 v0, v0, v1646; GCN-NEXT: global_store_dword v2, v0, s[2:3]647; GCN-NEXT: s_endpgm648bb:649 %vec0 = load volatile <2 x half>, ptr addrspace(3) %lds, align 4650 %f32 = load volatile float, ptr addrspace(3) poison, align 4651 %neg.f32 = fsub float -0.0, %f32652 %bc = bitcast float %neg.f32 to <2 x half>653 %result = fadd <2 x half> %vec0, %bc654 655 store <2 x half> %result, ptr addrspace(1) %out, align 4656 ret void657}658 659define amdgpu_kernel void @shuffle_bitcast_fneg_f32(ptr addrspace(1) %out, ptr addrspace(3) %lds) #0 {660; GCN-LABEL: shuffle_bitcast_fneg_f32:661; GCN: ; %bb.0: ; %bb662; GCN-NEXT: s_load_dword s2, s[0:1], 0x2c663; GCN-NEXT: v_mov_b32_e32 v2, 0664; GCN-NEXT: s_waitcnt lgkmcnt(0)665; GCN-NEXT: v_mov_b32_e32 v0, s2666; GCN-NEXT: ds_read_b32 v0, v0667; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24668; GCN-NEXT: s_waitcnt lgkmcnt(0)669; GCN-NEXT: ds_read_b32 v1, v0670; GCN-NEXT: s_waitcnt lgkmcnt(0)671; GCN-NEXT: v_xor_b32_e32 v1, 0x80000000, v1672; GCN-NEXT: v_pk_add_f16 v0, v0, v1 op_sel:[0,1] op_sel_hi:[1,0]673; GCN-NEXT: global_store_dword v2, v0, s[2:3]674; GCN-NEXT: s_endpgm675bb:676 %vec0 = load volatile <2 x half>, ptr addrspace(3) %lds, align 4677 678 %f32 = load volatile float, ptr addrspace(3) poison, align 4679 %neg.f32 = fsub float -0.0, %f32680 %bc = bitcast float %neg.f32 to <2 x half>681 %shuf = shufflevector <2 x half> %bc, <2 x half> poison, <2 x i32> <i32 1, i32 0>682 %result = fadd <2 x half> %vec0, %shuf683 store <2 x half> %result, ptr addrspace(1) %out, align 4684 ret void685}686 687define amdgpu_kernel void @extract_from_i64(ptr addrspace(1) %out, ptr addrspace(3) %lds) #0 {688; GCN-LABEL: extract_from_i64:689; GCN: ; %bb.0: ; %bb690; GCN-NEXT: s_load_dword s2, s[0:1], 0x2c691; GCN-NEXT: v_mov_b32_e32 v3, 0xffff692; GCN-NEXT: s_waitcnt lgkmcnt(0)693; GCN-NEXT: v_mov_b32_e32 v0, s2694; GCN-NEXT: ds_read_b32 v2, v0695; GCN-NEXT: global_load_dwordx2 v[0:1], v[0:1], off glc696; GCN-NEXT: s_waitcnt vmcnt(0)697; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24698; GCN-NEXT: v_mov_b32_e32 v1, 0699; GCN-NEXT: v_and_b32_sdwa v3, v3, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1700; GCN-NEXT: v_lshl_or_b32 v0, v0, 16, v3701; GCN-NEXT: s_waitcnt lgkmcnt(0)702; GCN-NEXT: v_pk_add_u16 v0, v2, v0703; GCN-NEXT: global_store_dword v1, v0, s[2:3]704; GCN-NEXT: s_endpgm705bb:706 %vec0 = load volatile <2 x i16>, ptr addrspace(3) %lds, align 4707 %i64 = load volatile i64, ptr addrspace(1) poison708 709 %elt0 = trunc i64 %i64 to i16710 %hi = lshr i64 %i64, 16711 %elt1 = trunc i64 %hi to i16712 713 %ins0 = insertelement <2 x i16> poison, i16 %elt1, i32 0714 %ins1 = insertelement <2 x i16> %ins0, i16 %elt0, i32 1715 %result = add <2 x i16> %vec0, %ins1716 store <2 x i16> %result, ptr addrspace(1) %out, align 4717 ret void718}719 720define amdgpu_kernel void @bitcast_lo_elt_op_sel(ptr addrspace(1) %out, ptr addrspace(3) %lds) #0 {721; GCN-LABEL: bitcast_lo_elt_op_sel:722; GCN: ; %bb.0: ; %bb723; GCN-NEXT: s_load_dword s2, s[0:1], 0x2c724; GCN-NEXT: s_waitcnt lgkmcnt(0)725; GCN-NEXT: v_mov_b32_e32 v0, s2726; GCN-NEXT: ds_read_b32 v1, v0727; GCN-NEXT: ds_read_b32 v2, v0 offset:4728; GCN-NEXT: ds_read_b32 v0, v0 offset:8729; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24730; GCN-NEXT: s_waitcnt lgkmcnt(0)731; GCN-NEXT: global_load_ushort v3, v[0:1], off glc732; GCN-NEXT: s_waitcnt vmcnt(0)733; GCN-NEXT: v_pk_add_f16 v0, v0, 2.0 op_sel_hi:[1,0]734; GCN-NEXT: v_mov_b32_e32 v3, 0735; GCN-NEXT: v_pk_fma_f16 v0, v1, v2, v0 op_sel:[0,0,1] op_sel_hi:[1,1,0]736; GCN-NEXT: global_store_dword v3, v0, s[2:3]737; GCN-NEXT: s_endpgm738bb:739 %lds.gep1 = getelementptr inbounds <2 x half>, ptr addrspace(3) %lds, i32 1740 %lds.gep2 = getelementptr inbounds <2 x half>, ptr addrspace(3) %lds, i32 2741 742 %vec0 = load volatile <2 x half>, ptr addrspace(3) %lds, align 4743 %vec1 = load volatile <2 x half>, ptr addrspace(3) %lds.gep1, align 4744 %vec2 = load volatile <2 x half>, ptr addrspace(3) %lds.gep2, align 4745 746 %scalar0 = load volatile i16, ptr addrspace(1) poison747 %shl = shl i16 %scalar0, 1748 %shl.bc = bitcast i16 %shl to half749 750 %fadd = fadd <2 x half> %vec2, <half 2.0, half 2.0>751 %shuffle = shufflevector <2 x half> %fadd, <2 x half> %vec2, <2 x i32> <i32 1, i32 0>752 753 %result = tail call <2 x half> @llvm.fma.v2f16(<2 x half> %vec0, <2 x half> %vec1, <2 x half> %shuffle)754 store <2 x half> %result, ptr addrspace(1) %out, align 4755 ret void756}757 758define amdgpu_kernel void @mix_elt_types_op_sel(ptr addrspace(1) %out, ptr addrspace(3) %lds) #0 {759; GCN-LABEL: mix_elt_types_op_sel:760; GCN: ; %bb.0: ; %bb761; GCN-NEXT: s_load_dword s2, s[0:1], 0x2c762; GCN-NEXT: s_waitcnt lgkmcnt(0)763; GCN-NEXT: v_mov_b32_e32 v0, s2764; GCN-NEXT: ds_read_b32 v1, v0765; GCN-NEXT: ds_read_b32 v2, v0 offset:4766; GCN-NEXT: ds_read_b32 v0, v0 offset:8767; GCN-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24768; GCN-NEXT: ; kill: killed $vgpr0_vgpr1769; GCN-NEXT: s_waitcnt lgkmcnt(0)770; GCN-NEXT: global_load_ushort v3, v[0:1], off glc771; GCN-NEXT: s_waitcnt vmcnt(0)772; GCN-NEXT: global_load_ushort v3, v[0:1], off glc773; GCN-NEXT: s_waitcnt vmcnt(0)774; GCN-NEXT: ; kill: killed $vgpr0_vgpr1775; GCN-NEXT: v_pk_add_f16 v0, v0, 2.0 op_sel_hi:[1,0]776; GCN-NEXT: v_mov_b32_e32 v3, 0777; GCN-NEXT: v_pk_fma_f16 v0, v1, v2, v0 op_sel:[0,0,1] op_sel_hi:[1,1,0]778; GCN-NEXT: global_store_dword v3, v0, s[2:3]779; GCN-NEXT: s_endpgm780bb:781 %lds.gep1 = getelementptr inbounds <2 x half>, ptr addrspace(3) %lds, i32 1782 %lds.gep2 = getelementptr inbounds <2 x half>, ptr addrspace(3) %lds, i32 2783 784 %vec0 = load volatile <2 x half>, ptr addrspace(3) %lds, align 4785 %vec1 = load volatile <2 x half>, ptr addrspace(3) %lds.gep1, align 4786 %vec2 = load volatile <2 x half>, ptr addrspace(3) %lds.gep2, align 4787 788 %scalar0 = load volatile i16, ptr addrspace(1) poison789 %scalar1 = load volatile half, ptr addrspace(1) poison790 %shl = shl i16 %scalar0, 1791 %shl.bc = bitcast i16 %shl to half792 793 %insert0 = insertelement <2 x half> poison, half %shl.bc, i32 0794 795 %fadd = fadd <2 x half> %vec2, <half 2.0, half 2.0>796 %insert1 = shufflevector <2 x half> %fadd, <2 x half> %insert0, <2 x i32> <i32 1, i32 0>797 798 %result = tail call <2 x half> @llvm.fma.v2f16(<2 x half> %vec0, <2 x half> %vec1, <2 x half> %insert1)799 store <2 x half> %result, ptr addrspace(1) %out, align 4800 ret void801}802 803declare <2 x half> @llvm.fma.v2f16(<2 x half>, <2 x half>, <2 x half>) #1804 805attributes #0 = { nounwind "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" }806attributes #1 = { nounwind readnone }807