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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 62; RUN: llc < %s -mtriple=r600 -mcpu=redwood | FileCheck %s -check-prefix=R6003; RUN: llc < %s -mtriple=r600 -mcpu=cayman | FileCheck %s -check-prefix=CM4 5define amdgpu_kernel void @test(ptr addrspace(1) %out, i32 %x_arg, i32 %y_arg, i32 %z_arg, i32 %w_arg, i32 %e) {6; R600-LABEL: test:7; R600: ; %bb.0: ; %entry8; R600-NEXT: ALU 12, @4, KC0[CB0:0-32], KC1[]9; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 110; R600-NEXT: CF_END11; R600-NEXT: PAD12; R600-NEXT: ALU clause starting at 4:13; R600-NEXT: ADD_INT T0.Y, KC0[3].X, 1,14; R600-NEXT: ADD_INT T0.Z, KC0[3].Y, 1,15; R600-NEXT: ADD_INT T0.W, KC0[2].Z, 1,16; R600-NEXT: ADD_INT * T1.W, KC0[2].W, 1,17; R600-NEXT: BIT_ALIGN_INT T0.X, PS, PS, KC0[3].Z,18; R600-NEXT: BIT_ALIGN_INT T1.Y, PV.W, PV.W, KC0[3].Z,19; R600-NEXT: BIT_ALIGN_INT T0.Z, PV.Z, PV.Z, KC0[3].Z,20; R600-NEXT: BIT_ALIGN_INT * T0.W, PV.Y, PV.Y, KC0[3].Z,21; R600-NEXT: OR_INT T0.W, PV.W, PV.Z,22; R600-NEXT: OR_INT * T1.W, PV.Y, PV.X,23; R600-NEXT: OR_INT T0.X, PS, PV.W,24; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,25; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)26;27; CM-LABEL: test:28; CM: ; %bb.0: ; %entry29; CM-NEXT: ALU 12, @4, KC0[CB0:0-32], KC1[]30; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X31; CM-NEXT: CF_END32; CM-NEXT: PAD33; CM-NEXT: ALU clause starting at 4:34; CM-NEXT: ADD_INT T0.X, KC0[3].X, 1,35; CM-NEXT: ADD_INT T0.Y, KC0[3].Y, 1,36; CM-NEXT: ADD_INT T0.Z, KC0[2].Z, 1,37; CM-NEXT: ADD_INT * T0.W, KC0[2].W, 1,38; CM-NEXT: BIT_ALIGN_INT T1.X, PV.W, PV.W, KC0[3].Z,39; CM-NEXT: BIT_ALIGN_INT T1.Y, PV.Z, PV.Z, KC0[3].Z,40; CM-NEXT: BIT_ALIGN_INT T0.Z, PV.Y, PV.Y, KC0[3].Z,41; CM-NEXT: BIT_ALIGN_INT * T0.W, PV.X, PV.X, KC0[3].Z,42; CM-NEXT: OR_INT T0.Z, PV.W, PV.Z,43; CM-NEXT: OR_INT * T0.W, PV.Y, PV.X,44; CM-NEXT: OR_INT * T0.X, PV.W, PV.Z,45; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,46; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)47entry:48 %shl = sub i32 32, %e49 %x = add i32 %x_arg, 150 %x.0 = shl i32 %x, %shl51 %x.1 = lshr i32 %x, %e52 %x.2 = or i32 %x.0, %x.153 %y = add i32 %y_arg, 154 %y.0 = shl i32 %y, %shl55 %y.1 = lshr i32 %y, %e56 %y.2 = or i32 %y.0, %y.157 %z = add i32 %z_arg, 158 %z.0 = shl i32 %z, %shl59 %z.1 = lshr i32 %z, %e60 %z.2 = or i32 %z.0, %z.161 %w = add i32 %w_arg, 162 %w.0 = shl i32 %w, %shl63 %w.1 = lshr i32 %w, %e64 %w.2 = or i32 %w.0, %w.165 %xy = or i32 %x.2, %y.266 %zw = or i32 %z.2, %w.267 %xyzw = or i32 %xy, %zw68 store i32 %xyzw, ptr addrspace(1) %out69 ret void70}71