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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -enable-var-scope --check-prefix=GCN %s3 4; Test combine to reduce the width of a 64-bit shift to 32-bit if5; truncated to 16-bit.6define i16 @trunc_srl_i64_16_to_i16(i64 %x) {7; GCN-LABEL: trunc_srl_i64_16_to_i16:8; GCN: ; %bb.0:9; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)10; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v011; GCN-NEXT: s_setpc_b64 s[30:31]12 %shift = lshr i64 %x, 1613 %trunc = trunc i64 %shift to i1614 ret i16 %trunc15}16 17define i16 @trunc_srl_i64_17_to_i16(i64 %x) {18; GCN-LABEL: trunc_srl_i64_17_to_i16:19; GCN: ; %bb.0:20; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)21; GCN-NEXT: v_lshrrev_b64 v[0:1], 17, v[0:1]22; GCN-NEXT: s_setpc_b64 s[30:31]23 %shift = lshr i64 %x, 1724 %trunc = trunc i64 %shift to i1625 ret i16 %trunc26}27 28define i15 @trunc_srl_i55_16_to_i15(i55 %x) {29; GCN-LABEL: trunc_srl_i55_16_to_i15:30; GCN: ; %bb.0:31; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)32; GCN-NEXT: v_lshrrev_b32_e32 v0, 15, v033; GCN-NEXT: v_add_u16_e32 v0, 4, v034; GCN-NEXT: s_setpc_b64 s[30:31]35 %shift = lshr i55 %x, 1536 %trunc = trunc i55 %shift to i1537 %add = add i15 %trunc, 438 ret i15 %add39}40 41define i16 @trunc_sra_i64_16_to_i16(i64 %x) {42; GCN-LABEL: trunc_sra_i64_16_to_i16:43; GCN: ; %bb.0:44; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)45; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v046; GCN-NEXT: s_setpc_b64 s[30:31]47 %shift = ashr i64 %x, 1648 %trunc = trunc i64 %shift to i1649 ret i16 %trunc50}51 52define i16 @trunc_sra_i64_17_to_i16(i64 %x) {53; GCN-LABEL: trunc_sra_i64_17_to_i16:54; GCN: ; %bb.0:55; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)56; GCN-NEXT: v_lshrrev_b64 v[0:1], 17, v[0:1]57; GCN-NEXT: s_setpc_b64 s[30:31]58 %shift = ashr i64 %x, 1759 %trunc = trunc i64 %shift to i1660 ret i16 %trunc61}62 63define i16 @trunc_shl_i64_16_to_i16(i64 %x) {64; GCN-LABEL: trunc_shl_i64_16_to_i16:65; GCN: ; %bb.0:66; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)67; GCN-NEXT: v_mov_b32_e32 v0, 068; GCN-NEXT: s_setpc_b64 s[30:31]69 %shift = shl i64 %x, 1670 %trunc = trunc i64 %shift to i1671 ret i16 %trunc72}73 74define i16 @trunc_shl_i64_17_to_i16(i64 %x) {75; GCN-LABEL: trunc_shl_i64_17_to_i16:76; GCN: ; %bb.0:77; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)78; GCN-NEXT: v_mov_b32_e32 v0, 079; GCN-NEXT: s_setpc_b64 s[30:31]80 %shift = shl i64 %x, 1781 %trunc = trunc i64 %shift to i1682 ret i16 %trunc83}84 85define <2 x i16> @trunc_srl_v2i64_16_to_v2i16(<2 x i64> %x) {86; GCN-LABEL: trunc_srl_v2i64_16_to_v2i16:87; GCN: ; %bb.0:88; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)89; GCN-NEXT: s_mov_b32 s4, 0x706030290; GCN-NEXT: v_perm_b32 v0, v2, v0, s491; GCN-NEXT: s_setpc_b64 s[30:31]92 %shift = lshr <2 x i64> %x, <i64 16, i64 16>93 %trunc = trunc <2 x i64> %shift to <2 x i16>94 ret <2 x i16> %trunc95}96 97define amdgpu_kernel void @s_trunc_srl_i64_16_to_i16(i64 %x) {98; GCN-LABEL: s_trunc_srl_i64_16_to_i16:99; GCN: ; %bb.0:100; GCN-NEXT: s_load_dword s0, s[4:5], 0x24101; GCN-NEXT: s_waitcnt lgkmcnt(0)102; GCN-NEXT: s_lshr_b32 s0, s0, 16103; GCN-NEXT: s_or_b32 s0, s0, 4104; GCN-NEXT: v_mov_b32_e32 v0, s0105; GCN-NEXT: global_store_short v[0:1], v0, off106; GCN-NEXT: s_endpgm107 %shift = lshr i64 %x, 16108 %trunc = trunc i64 %shift to i16109 %add = or i16 %trunc, 4110 store i16 %add, ptr addrspace(1) poison111 ret void112}113 114define i16 @trunc_srl_i64_var_mask15_to_i16(i64 %x, i64 %amt) {115; GCN-LABEL: trunc_srl_i64_var_mask15_to_i16:116; GCN: ; %bb.0:117; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)118; GCN-NEXT: v_and_b32_e32 v1, 15, v2119; GCN-NEXT: v_lshrrev_b32_e32 v0, v1, v0120; GCN-NEXT: s_setpc_b64 s[30:31]121 %amt.masked = and i64 %amt, 15122 %shift = lshr i64 %x, %amt.masked123 %trunc = trunc i64 %shift to i16124 ret i16 %trunc125}126 127define i16 @trunc_srl_i64_var_mask16_to_i16(i64 %x, i64 %amt) {128; GCN-LABEL: trunc_srl_i64_var_mask16_to_i16:129; GCN: ; %bb.0:130; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)131; GCN-NEXT: v_and_b32_e32 v1, 16, v2132; GCN-NEXT: v_lshrrev_b32_e32 v0, v1, v0133; GCN-NEXT: s_setpc_b64 s[30:31]134 %amt.masked = and i64 %amt, 16135 %shift = lshr i64 %x, %amt.masked136 %trunc = trunc i64 %shift to i16137 ret i16 %trunc138}139 140define i16 @trunc_srl_i64_var_mask31_to_i16(i64 %x, i64 %amt) {141; GCN-LABEL: trunc_srl_i64_var_mask31_to_i16:142; GCN: ; %bb.0:143; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)144; GCN-NEXT: v_and_b32_e32 v2, 31, v2145; GCN-NEXT: v_lshrrev_b64 v[0:1], v2, v[0:1]146; GCN-NEXT: s_setpc_b64 s[30:31]147 %amt.masked = and i64 %amt, 31148 %shift = lshr i64 %x, %amt.masked149 %trunc = trunc i64 %shift to i16150 ret i16 %trunc151}152 153define i32 @trunc_srl_i64_25_to_i26(i64 %x) {154; GCN-LABEL: trunc_srl_i64_25_to_i26:155; GCN: ; %bb.0:156; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)157; GCN-NEXT: v_and_b32_e32 v0, 0xa000000, v0158; GCN-NEXT: v_lshrrev_b32_e32 v0, 25, v0159; GCN-NEXT: v_add_u32_e32 v0, 55, v0160; GCN-NEXT: s_setpc_b64 s[30:31]161 %value.knownbits2 = and i64 %x, 167772160 ; 0xA000000162 %shift = lshr i64 %value.knownbits2, 25163 %trunc = trunc i64 %shift to i26164 %add = add i26 %trunc, 55165 %ext = zext i26 %add to i32166 ret i32 %ext167}168