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1; RUN: llc -mtriple=amdgcn -verify-coalescing < %s2 3; The original and requires materializing a 64-bit immediate for4; s_and_b64. This is split into 2 x v_and_i32, part of the immediate5; is folded through the reg_sequence into the v_and_i32 operand, and6; only half of the result is ever used.7;8; During live interval construction, the first sub register def is9; incorrectly marked as dead.10 11declare i32 @llvm.amdgcn.workitem.id.x() #112 13define amdgpu_kernel void @dead_def_subregister(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %in) #0 {14 %tid = call i32 @llvm.amdgcn.workitem.id.x() #115 %in.gep = getelementptr i64, ptr addrspace(1) %in, i32 %tid16 %val = load i64, ptr addrspace(1) %in.gep17 18 %lshr = shl i64 %val, 2419 %and1 = and i64 %lshr, 2190433320969 ; (255 << 33) | 920 %vec = bitcast i64 %and1 to <2 x i32>21 %elt1 = extractelement <2 x i32> %vec, i32 122 23 store i32 %elt1, ptr addrspace(1) %out24 ret void25}26 27attributes #0 = { nounwind }28attributes #1 = { nounwind readnone }29