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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 52# RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx942 -run-pass=peephole-opt -o - %s | FileCheck %s3 4# %2.sub0 -> %0.sub05---6name: reg_sequence_extract_subreg_sub0_from_regsequence_sub0_sub17tracksRegLiveness: true8body: |9 bb.0:10 liveins: $vgpr0_vgpr111 12 ; CHECK-LABEL: name: reg_sequence_extract_subreg_sub0_from_regsequence_sub0_sub113 ; CHECK: liveins: $vgpr0_vgpr114 ; CHECK-NEXT: {{ $}}15 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY $vgpr0_vgpr116 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec17 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]].sub0, %subreg.sub0, [[V_MOV_B32_e32_]], %subreg.sub118 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub019 ; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY1]]20 %0:vreg_64_align2 = COPY $vgpr0_vgpr121 %1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec22 %2:vreg_64_align2 = REG_SEQUENCE %0.sub0, %subreg.sub0, %1, %subreg.sub123 %3:vgpr_32 = COPY %2.sub024 S_ENDPGM 0, implicit %325 26...27 28# %2.sub1 -> %129---30name: reg_sequence_extract_subreg_sub1_from_regsequence_sub0_sub131tracksRegLiveness: true32body: |33 bb.0:34 liveins: $vgpr0_vgpr135 36 ; CHECK-LABEL: name: reg_sequence_extract_subreg_sub1_from_regsequence_sub0_sub137 ; CHECK: liveins: $vgpr0_vgpr138 ; CHECK-NEXT: {{ $}}39 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY $vgpr0_vgpr140 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec41 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[COPY]].sub0, %subreg.sub0, [[V_MOV_B32_e32_]], %subreg.sub142 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[V_MOV_B32_e32_]]43 ; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY1]]44 %0:vreg_64_align2 = COPY $vgpr0_vgpr145 %1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec46 %2:vreg_64_align2 = REG_SEQUENCE %0.sub0, %subreg.sub0, %1, %subreg.sub147 %3:vgpr_32 = COPY %2.sub148 S_ENDPGM 0, implicit %349 50...51 52# %2.sub0 -> %0.sub053---54name: reg_sequence_extract_subreg_sub0_from_regsequence_sub1_sub055tracksRegLiveness: true56body: |57 bb.0:58 liveins: $vgpr0_vgpr159 60 ; CHECK-LABEL: name: reg_sequence_extract_subreg_sub0_from_regsequence_sub1_sub061 ; CHECK: liveins: $vgpr0_vgpr162 ; CHECK-NEXT: {{ $}}63 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY $vgpr0_vgpr164 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec65 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub1, [[COPY]].sub0, %subreg.sub066 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub067 ; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY1]]68 %0:vreg_64_align2 = COPY $vgpr0_vgpr169 %1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec70 %2:vreg_64_align2 = REG_SEQUENCE %1, %subreg.sub1, %0.sub0, %subreg.sub071 %3:vgpr_32 = COPY %2.sub072 S_ENDPGM 0, implicit %373 74...75 76# %2.sub1 -> %177---78name: reg_sequence_extract_subreg_sub1_from_regsequence_sub1_sub079tracksRegLiveness: true80body: |81 bb.0:82 liveins: $vgpr0_vgpr183 84 ; CHECK-LABEL: name: reg_sequence_extract_subreg_sub1_from_regsequence_sub1_sub085 ; CHECK: liveins: $vgpr0_vgpr186 ; CHECK-NEXT: {{ $}}87 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64_align2 = COPY $vgpr0_vgpr188 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec89 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64_align2 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub1, [[COPY]].sub0, %subreg.sub090 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[V_MOV_B32_e32_]]91 ; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY1]]92 %0:vreg_64_align2 = COPY $vgpr0_vgpr193 %1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec94 %2:vreg_64_align2 = REG_SEQUENCE %1, %subreg.sub1, %0.sub0, %subreg.sub095 %3:vgpr_32 = COPY %2.sub196 S_ENDPGM 0, implicit %397 98...99 100# %2.sub0 -> %0.sub0101---102name: reg_sequence_extract_subreg_sub0_from_vreg96103tracksRegLiveness: true104body: |105 bb.0:106 liveins: $vgpr1_vgpr2107 108 ; CHECK-LABEL: name: reg_sequence_extract_subreg_sub0_from_vreg96109 ; CHECK: liveins: $vgpr1_vgpr2110 ; CHECK-NEXT: {{ $}}111 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr1_vgpr2112 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec113 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY]].sub0, %subreg.sub0, [[V_MOV_B32_e32_]], %subreg.sub1, [[COPY]].sub1, %subreg.sub2114 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0115 ; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY1]]116 %0:vreg_64 = COPY $vgpr1_vgpr2117 %1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec118 %2:vreg_96 = REG_SEQUENCE %0.sub0, %subreg.sub0, %1, %subreg.sub1, %0.sub1, %subreg.sub2119 %3:vgpr_32 = COPY %2.sub0120 S_ENDPGM 0, implicit %3121 122...123 124# %2.sub0 -> %0.sub0125---126name: reg_sequence_extract_subreg_sub1_from_vreg96127tracksRegLiveness: true128body: |129 bb.0:130 liveins: $vgpr1_vgpr2131 132 ; CHECK-LABEL: name: reg_sequence_extract_subreg_sub1_from_vreg96133 ; CHECK: liveins: $vgpr1_vgpr2134 ; CHECK-NEXT: {{ $}}135 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr1_vgpr2136 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec137 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY]].sub0, %subreg.sub0, [[V_MOV_B32_e32_]], %subreg.sub1, [[COPY]].sub1, %subreg.sub2138 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0139 ; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY1]]140 %0:vreg_64 = COPY $vgpr1_vgpr2141 %1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec142 %2:vreg_96 = REG_SEQUENCE %0.sub0, %subreg.sub0, %1, %subreg.sub1, %0.sub1, %subreg.sub2143 %3:vgpr_32 = COPY %2.sub0144 S_ENDPGM 0, implicit %3145 146...147 148---149name: reg_sequence_v128_compose_reg_sequence64_x2150tracksRegLiveness: true151body: |152 bb.0:153 liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3154 155 ; CHECK-LABEL: name: reg_sequence_v128_compose_reg_sequence64_x2156 ; CHECK: liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3157 ; CHECK-NEXT: {{ $}}158 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0159 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1160 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY $vgpr2161 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY $vgpr3162 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY]], %subreg.sub0, [[COPY1]], %subreg.sub1163 ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[COPY2]], %subreg.sub0, [[COPY3]], %subreg.sub1164 ; CHECK-NEXT: [[REG_SEQUENCE2:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[REG_SEQUENCE]], %subreg.sub0_sub1, [[REG_SEQUENCE1]], %subreg.sub2_sub3165 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[REG_SEQUENCE1]].sub0166 ; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY4]]167 %0:vgpr_32 = COPY $vgpr0168 %1:vgpr_32 = COPY $vgpr1169 %2:vgpr_32 = COPY $vgpr2170 %3:vgpr_32 = COPY $vgpr3171 %4:vreg_64 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1172 %5:vreg_64 = REG_SEQUENCE %2, %subreg.sub0, %3, %subreg.sub1173 %6:vreg_128 = REG_SEQUENCE %4, %subreg.sub0_sub1, %5, %subreg.sub2_sub3174 %7:vgpr_32 = COPY %6.sub2175 S_ENDPGM 0, implicit %7176 177...178 179---180name: reg_sequence_v128_compose_reg_sequence128_subreg64_extract32_sub2181tracksRegLiveness: true182body: |183 bb.0:184 liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7185 186 ; CHECK-LABEL: name: reg_sequence_v128_compose_reg_sequence128_subreg64_extract32_sub2187 ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7188 ; CHECK-NEXT: {{ $}}189 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr0_vgpr1_vgpr2_vgpr3190 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr4_vgpr5_vgpr6_vgpr7191 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]].sub0_sub1, %subreg.sub0, [[COPY1]], %subreg.sub2_sub3192 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub0193 ; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY2]]194 %0:vreg_128 = COPY $vgpr0_vgpr1_vgpr2_vgpr3195 %1:vreg_128 = COPY $vgpr4_vgpr5_vgpr6_vgpr7196 %2:vreg_128 = REG_SEQUENCE %0.sub0_sub1, %subreg.sub0, %1, %subreg.sub2_sub3197 %3:vgpr_32 = COPY %2.sub2198 S_ENDPGM 0, implicit %3199 200...201 202---203name: reg_sequence_v128_align2_compose_reg_sequence128_subreg64_extract32_sub2204tracksRegLiveness: true205body: |206 bb.0:207 liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7208 209 ; CHECK-LABEL: name: reg_sequence_v128_align2_compose_reg_sequence128_subreg64_extract32_sub2210 ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7211 ; CHECK-NEXT: {{ $}}212 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr0_vgpr1_vgpr2_vgpr3213 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr4_vgpr5_vgpr6_vgpr7214 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY]].sub0_sub1, %subreg.sub0, [[COPY1]], %subreg.sub2_sub3215 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub0216 ; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY2]]217 %0:vreg_128 = COPY $vgpr0_vgpr1_vgpr2_vgpr3218 %1:vreg_128 = COPY $vgpr4_vgpr5_vgpr6_vgpr7219 %2:vreg_128_align2 = REG_SEQUENCE %0.sub0_sub1, %subreg.sub0, %1, %subreg.sub2_sub3220 %3:vgpr_32 = COPY %2.sub2221 S_ENDPGM 0, implicit %3222 223...224 225# Unhandled, spans multiple sources226---227name: reg_sequence_v128_align2_compose_reg_sequence128_subreg64_align2_extract64_sub1_sub2228tracksRegLiveness: true229body: |230 bb.0:231 liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7232 233 ; CHECK-LABEL: name: reg_sequence_v128_align2_compose_reg_sequence128_subreg64_align2_extract64_sub1_sub2234 ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7235 ; CHECK-NEXT: {{ $}}236 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr0_vgpr1_vgpr2_vgpr3237 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr4_vgpr5_vgpr6_vgpr7238 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY]].sub0_sub1, %subreg.sub0, [[COPY1]], %subreg.sub2_sub3239 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE]].sub1_sub2240 ; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY2]]241 %0:vreg_128 = COPY $vgpr0_vgpr1_vgpr2_vgpr3242 %1:vreg_128 = COPY $vgpr4_vgpr5_vgpr6_vgpr7243 %2:vreg_128_align2 = REG_SEQUENCE %0.sub0_sub1, %subreg.sub0, %1, %subreg.sub2_sub3244 %3:vreg_64_align2 = COPY %2.sub1_sub2245 S_ENDPGM 0, implicit %3246 247...248 249# Unhandled, spans multiple sources250---251name: reg_sequence_v128_align2_compose_reg_sequence128_subreg64_align2_extract64_sub2_sub3252tracksRegLiveness: true253body: |254 bb.0:255 liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7256 257 ; CHECK-LABEL: name: reg_sequence_v128_align2_compose_reg_sequence128_subreg64_align2_extract64_sub2_sub3258 ; CHECK: liveins: $vgpr0_vgpr1_vgpr2_vgpr3, $vgpr4_vgpr5_vgpr6_vgpr7259 ; CHECK-NEXT: {{ $}}260 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr0_vgpr1_vgpr2_vgpr3261 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr4_vgpr5_vgpr6_vgpr7262 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128_align2 = REG_SEQUENCE [[COPY]].sub0_sub1, %subreg.sub0, [[COPY1]], %subreg.sub2_sub3263 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vreg_64_align2 = COPY [[REG_SEQUENCE]].sub1_sub2264 ; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY2]]265 %0:vreg_128 = COPY $vgpr0_vgpr1_vgpr2_vgpr3266 %1:vreg_128 = COPY $vgpr4_vgpr5_vgpr6_vgpr7267 %2:vreg_128_align2 = REG_SEQUENCE %0.sub0_sub1, %subreg.sub0, %1, %subreg.sub2_sub3268 %3:vreg_64_align2 = COPY %2.sub1_sub2269 S_ENDPGM 0, implicit %3270 271...272 273 274# %2.sub1 -> %0.sub1275---276name: reg_sequence_compose_0277tracksRegLiveness: true278body: |279 bb.0:280 liveins: $vgpr1_vgpr2281 282 ; CHECK-LABEL: name: reg_sequence_compose_0283 ; CHECK: liveins: $vgpr1_vgpr2284 ; CHECK-NEXT: {{ $}}285 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_64 = COPY $vgpr1_vgpr2286 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec287 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY]], %subreg.sub0_sub1, [[V_MOV_B32_e32_]], %subreg.sub2288 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1289 ; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY1]]290 %0:vreg_64 = COPY $vgpr1_vgpr2291 %1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec292 %2:vreg_96 = REG_SEQUENCE %0, %subreg.sub0_sub1, %1, %subreg.sub2293 %3:vgpr_32 = COPY %2.sub1294 S_ENDPGM 0, implicit %3295 296...297 298# %2.sub0 -> %0.sub2299# %2.sub1 -> %0.sub3300# %2.sub2 -> %0.sub0301---302name: reg_sequence_compose_1303tracksRegLiveness: true304body: |305 bb.0:306 liveins: $vgpr1_vgpr2_vgpr3_vgpr4307 308 ; CHECK-LABEL: name: reg_sequence_compose_1309 ; CHECK: liveins: $vgpr1_vgpr2_vgpr3_vgpr4310 ; CHECK-NEXT: {{ $}}311 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4312 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec313 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_96 = REG_SEQUENCE [[COPY]].sub2_sub3, %subreg.sub0_sub1, [[COPY]].sub0, %subreg.sub2314 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub2315 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub3316 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0317 ; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY1]], implicit [[COPY2]], implicit [[COPY3]]318 %0:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4319 %1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec320 %2:vreg_96 = REG_SEQUENCE %0.sub2_sub3, %subreg.sub0_sub1, %0.sub0, %subreg.sub2321 %3:vgpr_32 = COPY %2.sub0322 %4:vgpr_32 = COPY %2.sub1323 %5:vgpr_32 = COPY %2.sub2324 S_ENDPGM 0, implicit %3, implicit %4, implicit %5325 326...327 328# %3.sub0 -> %0.sub2329---330name: reg_sequence_compose_2331tracksRegLiveness: true332body: |333 bb.0:334 liveins: $vgpr1_vgpr2_vgpr3_vgpr4335 336 ; CHECK-LABEL: name: reg_sequence_compose_2337 ; CHECK: liveins: $vgpr1_vgpr2_vgpr3_vgpr4338 ; CHECK-NEXT: {{ $}}339 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4340 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec341 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec342 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]].sub2_sub3, %subreg.sub0_sub1, [[COPY]].sub0, %subreg.sub2, [[V_MOV_B32_e32_1]], %subreg.sub3343 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub2344 ; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY1]]345 %0:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4346 %1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec347 %2:vgpr_32 = V_MOV_B32_e32 1, implicit $exec348 %3:vreg_128 = REG_SEQUENCE %0.sub2_sub3, %subreg.sub0_sub1, %0.sub0, %subreg.sub2, %2, %subreg.sub3349 %4:vgpr_32 = COPY %3.sub0350 S_ENDPGM 0, implicit %4351 352...353 354# %3.sub1 -> %0.sub3355# %3.sub0 -> %0.sub2356---357name: reg_sequence_compose_3358tracksRegLiveness: true359body: |360 bb.0:361 liveins: $vgpr1_vgpr2_vgpr3_vgpr4362 363 ; CHECK-LABEL: name: reg_sequence_compose_3364 ; CHECK: liveins: $vgpr1_vgpr2_vgpr3_vgpr4365 ; CHECK-NEXT: {{ $}}366 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4367 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec368 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec369 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]].sub2_sub3, %subreg.sub0_sub1, [[COPY]].sub0, %subreg.sub2, [[V_MOV_B32_e32_1]], %subreg.sub3370 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub3371 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub2372 ; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY1]], implicit [[COPY2]]373 %0:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4374 %1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec375 %2:vgpr_32 = V_MOV_B32_e32 1, implicit $exec376 %3:vreg_128 = REG_SEQUENCE %0.sub2_sub3, %subreg.sub0_sub1, %0.sub0, %subreg.sub2, %2, %subreg.sub3377 %4:vgpr_32 = COPY %3.sub1378 %5:vgpr_32 = COPY %3.sub0379 S_ENDPGM 0, implicit %4, implicit %5380 381...382 383# %3.sub2 -> %0.sub0384---385name: reg_sequence_compose_4386tracksRegLiveness: true387body: |388 bb.0:389 liveins: $vgpr1_vgpr2_vgpr3_vgpr4390 391 ; CHECK-LABEL: name: reg_sequence_compose_4392 ; CHECK: liveins: $vgpr1_vgpr2_vgpr3_vgpr4393 ; CHECK-NEXT: {{ $}}394 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4395 ; CHECK-NEXT: [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec396 ; CHECK-NEXT: [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec397 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]].sub2_sub3, %subreg.sub0_sub1, [[COPY]].sub0, %subreg.sub2, [[V_MOV_B32_e32_1]], %subreg.sub3398 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub0399 ; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY1]]400 %0:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4401 %1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec402 %2:vgpr_32 = V_MOV_B32_e32 1, implicit $exec403 %3:vreg_128 = REG_SEQUENCE %0.sub2_sub3, %subreg.sub0_sub1, %0.sub0, %subreg.sub2, %2, %subreg.sub3404 %4:vgpr_32 = COPY %3.sub2405 S_ENDPGM 0, implicit %4406 407...408 409# %2.sub3 -> %1.sub1410---411name: reg_sequence_compose_5412tracksRegLiveness: true413body: |414 bb.0:415 liveins: $vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6_vgpr7_vgpr8416 417 ; CHECK-LABEL: name: reg_sequence_compose_5418 ; CHECK: liveins: $vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6_vgpr7_vgpr8419 ; CHECK-NEXT: {{ $}}420 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4421 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr5_vgpr6_vgpr7_vgpr8422 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]].sub2_sub3, %subreg.sub0_sub1, [[COPY1]].sub0_sub1, %subreg.sub2_sub3423 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub1424 ; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY2]]425 %0:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4426 %1:vreg_128 = COPY $vgpr5_vgpr6_vgpr7_vgpr8427 %2:vreg_128 = REG_SEQUENCE %0.sub2_sub3, %subreg.sub0_sub1, %1.sub0_sub1, %subreg.sub2_sub3428 %3:vgpr_32 = COPY %2.sub3429 S_ENDPGM 0, implicit %3430 431...432 433# %2.sub0 -> %0.sub2434---435name: reg_sequence_compose_6436tracksRegLiveness: true437body: |438 bb.0:439 liveins: $vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6_vgpr7_vgpr8440 441 ; CHECK-LABEL: name: reg_sequence_compose_6442 ; CHECK: liveins: $vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6_vgpr7_vgpr8443 ; CHECK-NEXT: {{ $}}444 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4445 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr5_vgpr6_vgpr7_vgpr8446 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]].sub2_sub3, %subreg.sub0_sub1, [[COPY1]].sub0_sub1, %subreg.sub2_sub3447 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub2448 ; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY2]]449 %0:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4450 %1:vreg_128 = COPY $vgpr5_vgpr6_vgpr7_vgpr8451 %2:vreg_128 = REG_SEQUENCE %0.sub2_sub3, %subreg.sub0_sub1, %1.sub0_sub1, %subreg.sub2_sub3452 %3:vgpr_32 = COPY %2.sub0453 S_ENDPGM 0, implicit %3454 455...456 457# %2.sub1 -> %0.sub3458---459name: reg_sequence_compose_7460tracksRegLiveness: true461body: |462 bb.0:463 liveins: $vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6_vgpr7_vgpr8464 465 ; CHECK-LABEL: name: reg_sequence_compose_7466 ; CHECK: liveins: $vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6_vgpr7_vgpr8467 ; CHECK-NEXT: {{ $}}468 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4469 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr5_vgpr6_vgpr7_vgpr8470 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]].sub2_sub3, %subreg.sub0_sub1, [[COPY1]].sub0_sub1, %subreg.sub2_sub3471 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub3472 ; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY2]]473 %0:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4474 %1:vreg_128 = COPY $vgpr5_vgpr6_vgpr7_vgpr8475 %2:vreg_128 = REG_SEQUENCE %0.sub2_sub3, %subreg.sub0_sub1, %1.sub0_sub1, %subreg.sub2_sub3476 %3:vgpr_32 = COPY %2.sub1477 S_ENDPGM 0, implicit %3478 479...480 481# %2.sub2 -> %1.sub0482---483name: reg_sequence_compose_8484tracksRegLiveness: true485body: |486 bb.0:487 liveins: $vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6_vgpr7_vgpr8488 489 ; CHECK-LABEL: name: reg_sequence_compose_8490 ; CHECK: liveins: $vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6_vgpr7_vgpr8491 ; CHECK-NEXT: {{ $}}492 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4493 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr5_vgpr6_vgpr7_vgpr8494 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]].sub2_sub3, %subreg.sub0_sub1, [[COPY1]].sub0_sub1, %subreg.sub2_sub3495 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub0496 ; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY2]]497 %0:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4498 %1:vreg_128 = COPY $vgpr5_vgpr6_vgpr7_vgpr8499 %2:vreg_128 = REG_SEQUENCE %0.sub2_sub3, %subreg.sub0_sub1, %1.sub0_sub1, %subreg.sub2_sub3500 %3:vgpr_32 = COPY %2.sub2501 S_ENDPGM 0, implicit %3502 503...504 505# %2.sub3 -> %1.sub1506---507name: reg_sequence_compose_9508tracksRegLiveness: true509body: |510 bb.0:511 liveins: $vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6_vgpr7_vgpr8512 513 ; CHECK-LABEL: name: reg_sequence_compose_9514 ; CHECK: liveins: $vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6_vgpr7_vgpr8515 ; CHECK-NEXT: {{ $}}516 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4517 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr5_vgpr6_vgpr7_vgpr8518 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]].sub2_sub3, %subreg.sub0_sub1, [[COPY1]].sub0_sub1, %subreg.sub2_sub3519 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub1520 ; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY2]]521 %0:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4522 %1:vreg_128 = COPY $vgpr5_vgpr6_vgpr7_vgpr8523 %2:vreg_128 = REG_SEQUENCE %0.sub2_sub3, %subreg.sub0_sub1, %1.sub0_sub1, %subreg.sub2_sub3524 %3:vgpr_32 = COPY %2.sub3525 S_ENDPGM 0, implicit %3526 527...528 529# %2.sub3 -> %1.sub1530---531name: reg_sequence_compose_10532tracksRegLiveness: true533body: |534 bb.0:535 liveins: $vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6_vgpr7_vgpr8536 537 ; CHECK-LABEL: name: reg_sequence_compose_10538 ; CHECK: liveins: $vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6_vgpr7_vgpr8539 ; CHECK-NEXT: {{ $}}540 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4541 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr5_vgpr6_vgpr7_vgpr8542 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]].sub0_sub1, %subreg.sub2_sub3, [[COPY]].sub2_sub3, %subreg.sub0_sub1543 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub1544 ; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY2]]545 %0:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4546 %1:vreg_128 = COPY $vgpr5_vgpr6_vgpr7_vgpr8547 %2:vreg_128 = REG_SEQUENCE %1.sub0_sub1, %subreg.sub2_sub3, %0.sub2_sub3, %subreg.sub0_sub1548 %3:vgpr_32 = COPY %2.sub3549 S_ENDPGM 0, implicit %3550 551...552 553# %2.sub1 -> %0.sub3554---555name: reg_sequence_compose_11556tracksRegLiveness: true557body: |558 bb.0:559 liveins: $vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6_vgpr7_vgpr8560 561 ; CHECK-LABEL: name: reg_sequence_compose_11562 ; CHECK: liveins: $vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6_vgpr7_vgpr8563 ; CHECK-NEXT: {{ $}}564 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4565 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_128 = COPY $vgpr5_vgpr6_vgpr7_vgpr8566 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY1]].sub0_sub1, %subreg.sub2_sub3, [[COPY]].sub2_sub3, %subreg.sub0_sub1567 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub3568 ; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY2]]569 %0:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4570 %1:vreg_128 = COPY $vgpr5_vgpr6_vgpr7_vgpr8571 %2:vreg_128 = REG_SEQUENCE %1.sub0_sub1, %subreg.sub2_sub3, %0.sub2_sub3, %subreg.sub0_sub1572 %3:vgpr_32 = COPY %2.sub1573 S_ENDPGM 0, implicit %3574 575...576 577# %2.sub0 -> %0.sub1578---579name: reg_sequence_compose_12580tracksRegLiveness: true581body: |582 bb.0:583 liveins: $vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6584 585 ; CHECK-LABEL: name: reg_sequence_compose_12586 ; CHECK: liveins: $vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6587 ; CHECK-NEXT: {{ $}}588 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4589 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr5_vgpr6590 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]].sub1_sub2_sub3, %subreg.sub0_sub1_sub2, [[COPY1]].sub1, %subreg.sub3591 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1592 ; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY2]]593 %0:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4594 %1:vreg_64 = COPY $vgpr5_vgpr6595 %2:vreg_128 = REG_SEQUENCE %0.sub1_sub2_sub3, %subreg.sub0_sub1_sub2, %1.sub1, %subreg.sub3596 %3:vgpr_32 = COPY %2.sub0597 S_ENDPGM 0, implicit %3598 599...600 601# %2.sub0 -> %0.sub1602# %2.sub1 -> %0.sub2603# %2.sub2 -> %0.sub3604# %2.sub3 -> %1.sub1605---606name: reg_sequence_compose_13607tracksRegLiveness: true608body: |609 bb.0:610 liveins: $vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6611 612 ; CHECK-LABEL: name: reg_sequence_compose_13613 ; CHECK: liveins: $vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6614 ; CHECK-NEXT: {{ $}}615 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4616 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr5_vgpr6617 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_128 = REG_SEQUENCE [[COPY]].sub1_sub2_sub3, %subreg.sub0_sub1_sub2, [[COPY1]].sub1, %subreg.sub3618 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1619 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub2620 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub3621 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub1622 ; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY2]], implicit [[COPY3]], implicit [[COPY4]], implicit [[COPY5]]623 %0:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4624 %1:vreg_64 = COPY $vgpr5_vgpr6625 %2:vreg_128 = REG_SEQUENCE %0.sub1_sub2_sub3, %subreg.sub0_sub1_sub2, %1.sub1, %subreg.sub3626 %3:vgpr_32 = COPY %2.sub0627 %4:vgpr_32 = COPY %2.sub1628 %5:vgpr_32 = COPY %2.sub2629 %6:vgpr_32 = COPY %2.sub3630 S_ENDPGM 0, implicit %3, implicit %4, implicit %5, implicit %6631 632...633 634# %2.sub0 -> %0.sub1635# %2.sub1 -> %0.sub2636# %2.sub2 -> %1.sub0637# %2.sub3 -> %1.sub1638# %2.sub4 -> %0.sub2639# %2.sub5 -> %0.sub3640---641name: reg_sequence_compose_14642tracksRegLiveness: true643body: |644 bb.0:645 liveins: $vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6646 647 ; CHECK-LABEL: name: reg_sequence_compose_14648 ; CHECK: liveins: $vgpr1_vgpr2_vgpr3_vgpr4, $vgpr5_vgpr6649 ; CHECK-NEXT: {{ $}}650 ; CHECK-NEXT: [[COPY:%[0-9]+]]:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4651 ; CHECK-NEXT: [[COPY1:%[0-9]+]]:vreg_64 = COPY $vgpr5_vgpr6652 ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vreg_192 = REG_SEQUENCE [[COPY]].sub2_sub3, %subreg.sub4_sub5, [[COPY]].sub1_sub2, %subreg.sub0_sub1, [[COPY1]], %subreg.sub2_sub3653 ; CHECK-NEXT: [[COPY2:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub1654 ; CHECK-NEXT: [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub2655 ; CHECK-NEXT: [[COPY4:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub0656 ; CHECK-NEXT: [[COPY5:%[0-9]+]]:vgpr_32 = COPY [[COPY1]].sub1657 ; CHECK-NEXT: [[COPY6:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub2658 ; CHECK-NEXT: [[COPY7:%[0-9]+]]:vgpr_32 = COPY [[COPY]].sub3659 ; CHECK-NEXT: S_ENDPGM 0, implicit [[COPY2]], implicit [[COPY3]], implicit [[COPY4]], implicit [[COPY5]], implicit [[COPY6]], implicit [[COPY7]]660 %0:vreg_128 = COPY $vgpr1_vgpr2_vgpr3_vgpr4661 %1:vreg_64 = COPY $vgpr5_vgpr6662 %2:vreg_192 = REG_SEQUENCE %0.sub2_sub3, %subreg.sub4_sub5, %0.sub1_sub2, %subreg.sub0_sub1, %1, %subreg.sub2_sub3663 %3:vgpr_32 = COPY %2.sub0664 %4:vgpr_32 = COPY %2.sub1665 %5:vgpr_32 = COPY %2.sub2666 %6:vgpr_32 = COPY %2.sub3667 %7:vgpr_32 = COPY %2.sub4668 %8:vgpr_32 = COPY %2.sub5669 S_ENDPGM 0, implicit %3, implicit %4, implicit %5, implicit %6, implicit %7, implicit %8670 671...672 673