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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals all --version 52; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -amdgpu-perf-hint < %s | FileCheck -check-prefix=CHECK %s3; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-perf-hint < %s | FileCheck -check-prefix=CHECK %s4; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=GCN %s5 6; GCN-LABEL: {{^}}test_membound:7; GCN: MemoryBound: 18; GCN: WaveLimiterHint : 19define amdgpu_kernel void @test_membound(ptr addrspace(1) nocapture readonly %arg, ptr addrspace(1) nocapture %arg1) {10; CHECK-LABEL: define amdgpu_kernel void @test_membound(11; CHECK-SAME: ptr addrspace(1) readonly captures(none) [[ARG:%.*]], ptr addrspace(1) captures(none) [[ARG1:%.*]]) #[[ATTR0:[0-9]+]] {12; CHECK-NEXT: [[BB:.*:]]13; CHECK-NEXT: [[TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()14; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP]] to i6415; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds <4 x i32>, ptr addrspace(1) [[ARG]], i64 [[TMP2]]16; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr addrspace(1) [[TMP3]], align 1617; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds <4 x i32>, ptr addrspace(1) [[ARG1]], i64 [[TMP2]]18; CHECK-NEXT: store <4 x i32> [[TMP4]], ptr addrspace(1) [[TMP5]], align 1619; CHECK-NEXT: [[TMP6:%.*]] = add nuw nsw i64 [[TMP2]], 120; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds <4 x i32>, ptr addrspace(1) [[ARG]], i64 [[TMP6]]21; CHECK-NEXT: [[TMP8:%.*]] = load <4 x i32>, ptr addrspace(1) [[TMP7]], align 1622; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds <4 x i32>, ptr addrspace(1) [[ARG1]], i64 [[TMP6]]23; CHECK-NEXT: store <4 x i32> [[TMP8]], ptr addrspace(1) [[TMP9]], align 1624; CHECK-NEXT: ret void25;26bb:27 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()28 %tmp2 = zext i32 %tmp to i6429 %tmp3 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg, i64 %tmp230 %tmp4 = load <4 x i32>, ptr addrspace(1) %tmp3, align 1631 %tmp5 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg1, i64 %tmp232 store <4 x i32> %tmp4, ptr addrspace(1) %tmp5, align 1633 %tmp6 = add nuw nsw i64 %tmp2, 134 %tmp7 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg, i64 %tmp635 %tmp8 = load <4 x i32>, ptr addrspace(1) %tmp7, align 1636 %tmp9 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg1, i64 %tmp637 store <4 x i32> %tmp8, ptr addrspace(1) %tmp9, align 1638 ret void39}40 41; GCN-LABEL: {{^}}test_membound_1:42; GCN: MemoryBound: 143define amdgpu_kernel void @test_membound_1(ptr addrspace(1) nocapture readonly %ptr.0,44; CHECK-LABEL: define amdgpu_kernel void @test_membound_1(45; CHECK-SAME: ptr addrspace(1) readonly captures(none) [[PTR_0:%.*]], ptr addrspace(1) captures(none) [[PTR_1:%.*]], <2 x double> [[ARG_0:%.*]], i32 [[ARG_1:%.*]], <4 x double> [[ARG_2:%.*]]) #[[ATTR1:[0-9]+]] {46; CHECK-NEXT: [[BB_ENTRY:.*:]]47; CHECK-NEXT: [[ID_32:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()48; CHECK-NEXT: [[ID_0:%.*]] = zext i32 [[ID_32]] to i6449; CHECK-NEXT: [[GEP_0:%.*]] = getelementptr inbounds <2 x double>, ptr addrspace(1) [[PTR_0]], i64 [[ID_0]]50; CHECK-NEXT: [[LD_0:%.*]] = load <2 x double>, ptr addrspace(1) [[GEP_0]], align 1651; CHECK-NEXT: [[ADD_0:%.*]] = fadd <2 x double> [[ARG_0]], [[LD_0]]52; CHECK-NEXT: [[ID_1:%.*]] = add nuw nsw i64 [[ID_0]], 153; CHECK-NEXT: [[GEP_1:%.*]] = getelementptr inbounds <2 x double>, ptr addrspace(1) [[PTR_0]], i64 [[ID_1]]54; CHECK-NEXT: [[LD_1:%.*]] = load <2 x double>, ptr addrspace(1) [[GEP_1]], align 1655; CHECK-NEXT: [[ADD_1:%.*]] = fadd <2 x double> [[ADD_0]], [[LD_1]]56; CHECK-NEXT: [[ID_2:%.*]] = add nuw nsw i64 [[ID_0]], 257; CHECK-NEXT: [[GEP_2:%.*]] = getelementptr inbounds <2 x double>, ptr addrspace(1) [[PTR_0]], i64 [[ID_2]]58; CHECK-NEXT: [[LD_2:%.*]] = load <2 x double>, ptr addrspace(1) [[GEP_2]], align 1659; CHECK-NEXT: [[ADD_2:%.*]] = fadd <2 x double> [[ADD_1]], [[LD_2]]60; CHECK-NEXT: [[ID_3:%.*]] = add nuw nsw i64 [[ID_0]], 361; CHECK-NEXT: [[GEP_3:%.*]] = getelementptr inbounds <2 x double>, ptr addrspace(1) [[PTR_0]], i64 [[ID_3]]62; CHECK-NEXT: [[LD_3:%.*]] = load <2 x double>, ptr addrspace(1) [[GEP_3]], align 1663; CHECK-NEXT: [[ADD_3:%.*]] = fadd <2 x double> [[ADD_2]], [[LD_3]]64; CHECK-NEXT: [[ID_4:%.*]] = add nuw nsw i64 [[ID_0]], 465; CHECK-NEXT: [[GEP_4:%.*]] = getelementptr inbounds <2 x double>, ptr addrspace(1) [[PTR_0]], i64 [[ID_4]]66; CHECK-NEXT: [[LD_4:%.*]] = load <2 x double>, ptr addrspace(1) [[GEP_4]], align 1667; CHECK-NEXT: [[ADD_4:%.*]] = fadd <2 x double> [[ADD_3]], [[LD_4]]68; CHECK-NEXT: store <2 x double> [[ADD_4]], ptr addrspace(1) [[PTR_1]], align 1669; CHECK-NEXT: [[COND:%.*]] = icmp eq i32 [[ARG_1]], 070; CHECK-NEXT: br i1 [[COND]], label %[[BB_TRUE:.*]], label %[[BB_RET:.*]]71; CHECK: [[BB_TRUE]]:72; CHECK-NEXT: [[I0_ARG_0:%.*]] = extractelement <2 x double> [[ARG_0]], i32 073; CHECK-NEXT: [[I1_ARG_0:%.*]] = extractelement <2 x double> [[ARG_0]], i32 174; CHECK-NEXT: [[ADD_1_0:%.*]] = fadd double [[I0_ARG_0]], [[I1_ARG_0]]75; CHECK-NEXT: [[I0_ARG_2:%.*]] = extractelement <4 x double> [[ARG_2]], i32 076; CHECK-NEXT: [[I1_ARG_2:%.*]] = extractelement <4 x double> [[ARG_2]], i32 177; CHECK-NEXT: [[ADD_1_1:%.*]] = fadd double [[I0_ARG_2]], [[I1_ARG_2]]78; CHECK-NEXT: [[ADD_1_2:%.*]] = fadd double [[ADD_1_0]], [[ADD_1_1]]79; CHECK-NEXT: [[I2_ARG_2:%.*]] = extractelement <4 x double> [[ARG_2]], i32 280; CHECK-NEXT: [[I3_ARG_2:%.*]] = extractelement <4 x double> [[ARG_2]], i32 381; CHECK-NEXT: [[ADD_1_3:%.*]] = fadd double [[I2_ARG_2]], [[I3_ARG_2]]82; CHECK-NEXT: [[ADD_1_4:%.*]] = fadd double [[ADD_1_2]], [[ADD_1_3]]83; CHECK-NEXT: [[I0_ADD_0:%.*]] = extractelement <2 x double> [[ADD_0]], i32 084; CHECK-NEXT: [[I1_ADD_0:%.*]] = extractelement <2 x double> [[ADD_0]], i32 185; CHECK-NEXT: [[ADD_1_5:%.*]] = fadd double [[I0_ADD_0]], [[I1_ADD_0]]86; CHECK-NEXT: [[ADD_1_6:%.*]] = fadd double [[ADD_1_4]], [[ADD_1_5]]87; CHECK-NEXT: [[I0_ADD_1:%.*]] = extractelement <2 x double> [[ADD_1]], i32 088; CHECK-NEXT: [[I1_ADD_1:%.*]] = extractelement <2 x double> [[ADD_1]], i32 189; CHECK-NEXT: [[ADD_1_7:%.*]] = fadd double [[I0_ADD_1]], [[I1_ADD_1]]90; CHECK-NEXT: [[ADD_1_8:%.*]] = fadd double [[ADD_1_6]], [[ADD_1_7]]91; CHECK-NEXT: [[I0_ADD_2:%.*]] = extractelement <2 x double> [[ADD_2]], i32 092; CHECK-NEXT: [[I1_ADD_2:%.*]] = extractelement <2 x double> [[ADD_2]], i32 193; CHECK-NEXT: [[ADD_1_9:%.*]] = fadd double [[I0_ADD_2]], [[I1_ADD_2]]94; CHECK-NEXT: [[ADD_1_10:%.*]] = fadd double [[ADD_1_8]], [[ADD_1_9]]95; CHECK-NEXT: store double [[ADD_1_8]], ptr addrspace(1) [[PTR_1]], align 896; CHECK-NEXT: br label %[[BB_RET]]97; CHECK: [[BB_RET]]:98; CHECK-NEXT: ret void99;100 ptr addrspace(1) nocapture %ptr.1,101 <2 x double> %arg.0, i32 %arg.1, <4 x double> %arg.2) {102bb.entry:103 %id.32 = tail call i32 @llvm.amdgcn.workitem.id.x()104 %id.0 = zext i32 %id.32 to i64105 %gep.0 = getelementptr inbounds <2 x double>, ptr addrspace(1) %ptr.0, i64 %id.0106 %ld.0 = load <2 x double>, ptr addrspace(1) %gep.0, align 16107 %add.0 = fadd <2 x double> %arg.0, %ld.0108 109 %id.1 = add nuw nsw i64 %id.0, 1110 %gep.1 = getelementptr inbounds <2 x double>, ptr addrspace(1) %ptr.0, i64 %id.1111 %ld.1 = load <2 x double>, ptr addrspace(1) %gep.1, align 16112 %add.1 = fadd <2 x double> %add.0, %ld.1113 114 %id.2 = add nuw nsw i64 %id.0, 2115 %gep.2 = getelementptr inbounds <2 x double>, ptr addrspace(1) %ptr.0, i64 %id.2116 %ld.2 = load <2 x double>, ptr addrspace(1) %gep.2, align 16117 %add.2 = fadd <2 x double> %add.1, %ld.2118 119 %id.3 = add nuw nsw i64 %id.0, 3120 %gep.3= getelementptr inbounds <2 x double>, ptr addrspace(1) %ptr.0, i64 %id.3121 %ld.3 = load <2 x double>, ptr addrspace(1) %gep.3, align 16122 %add.3 = fadd <2 x double> %add.2, %ld.3123 124 %id.4 = add nuw nsw i64 %id.0, 4125 %gep.4= getelementptr inbounds <2 x double>, ptr addrspace(1) %ptr.0, i64 %id.4126 %ld.4 = load <2 x double>, ptr addrspace(1) %gep.4, align 16127 %add.4 = fadd <2 x double> %add.3, %ld.4128 129 store <2 x double> %add.4, ptr addrspace(1) %ptr.1, align 16130 %cond = icmp eq i32 %arg.1, 0131 br i1 %cond, label %bb.true, label %bb.ret132 133bb.true:134 %i0.arg.0 = extractelement <2 x double> %arg.0, i32 0135 %i1.arg.0 = extractelement <2 x double> %arg.0, i32 1136 %add.1.0 = fadd double %i0.arg.0, %i1.arg.0137 %i0.arg.2 = extractelement <4 x double> %arg.2, i32 0138 %i1.arg.2 = extractelement <4 x double> %arg.2, i32 1139 %add.1.1 = fadd double %i0.arg.2, %i1.arg.2140 %add.1.2 = fadd double %add.1.0, %add.1.1141 %i2.arg.2 = extractelement <4 x double> %arg.2, i32 2142 %i3.arg.2 = extractelement <4 x double> %arg.2, i32 3143 %add.1.3 = fadd double %i2.arg.2, %i3.arg.2144 %add.1.4 = fadd double %add.1.2, %add.1.3145 %i0.add.0 = extractelement <2 x double> %add.0, i32 0146 %i1.add.0 = extractelement <2 x double> %add.0, i32 1147 %add.1.5 = fadd double %i0.add.0, %i1.add.0148 %add.1.6 = fadd double %add.1.4, %add.1.5149 %i0.add.1 = extractelement <2 x double> %add.1, i32 0150 %i1.add.1 = extractelement <2 x double> %add.1, i32 1151 %add.1.7 = fadd double %i0.add.1, %i1.add.1152 %add.1.8 = fadd double %add.1.6, %add.1.7153 %i0.add.2 = extractelement <2 x double> %add.2, i32 0154 %i1.add.2 = extractelement <2 x double> %add.2, i32 1155 %add.1.9 = fadd double %i0.add.2, %i1.add.2156 %add.1.10 = fadd double %add.1.8, %add.1.9157 158 store double %add.1.8, ptr addrspace(1) %ptr.1, align 8159 br label %bb.ret160 161bb.ret:162 ret void163}164 165; GCN-LABEL: {{^}}test_large_stride:166; GCN: MemoryBound: 0167; GCN: WaveLimiterHint : 1168define amdgpu_kernel void @test_large_stride(ptr addrspace(1) nocapture %arg) {169; CHECK-LABEL: define amdgpu_kernel void @test_large_stride(170; CHECK-SAME: ptr addrspace(1) captures(none) [[ARG:%.*]]) #[[ATTR2:[0-9]+]] {171; CHECK-NEXT: [[BB:.*:]]172; CHECK-NEXT: [[TMP:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[ARG]], i64 4096173; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(1) [[TMP]], align 4174; CHECK-NEXT: [[MUL1:%.*]] = mul i32 [[TMP1]], [[TMP1]]175; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[ARG]], i64 1176; CHECK-NEXT: store i32 [[MUL1]], ptr addrspace(1) [[TMP2]], align 4177; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[ARG]], i64 8192178; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr addrspace(1) [[TMP3]], align 4179; CHECK-NEXT: [[MUL4:%.*]] = mul i32 [[TMP4]], [[TMP4]]180; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[ARG]], i64 2181; CHECK-NEXT: store i32 [[MUL4]], ptr addrspace(1) [[TMP5]], align 4182; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[ARG]], i64 12288183; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) [[TMP6]], align 4184; CHECK-NEXT: [[MUL7:%.*]] = mul i32 [[TMP7]], [[TMP7]]185; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[ARG]], i64 3186; CHECK-NEXT: store i32 [[MUL7]], ptr addrspace(1) [[TMP8]], align 4187; CHECK-NEXT: ret void188;189bb:190 %tmp = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 4096191 %tmp1 = load i32, ptr addrspace(1) %tmp, align 4192 %mul1 = mul i32 %tmp1, %tmp1193 %tmp2 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 1194 store i32 %mul1, ptr addrspace(1) %tmp2, align 4195 %tmp3 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 8192196 %tmp4 = load i32, ptr addrspace(1) %tmp3, align 4197 %mul4 = mul i32 %tmp4, %tmp4198 %tmp5 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 2199 store i32 %mul4, ptr addrspace(1) %tmp5, align 4200 %tmp6 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 12288201 %tmp7 = load i32, ptr addrspace(1) %tmp6, align 4202 %mul7 = mul i32 %tmp7, %tmp7203 %tmp8 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 3204 store i32 %mul7, ptr addrspace(1) %tmp8, align 4205 ret void206}207 208; GCN-LABEL: {{^}}test_indirect:209; GCN: MemoryBound: 1210; GCN: WaveLimiterHint : 1211define amdgpu_kernel void @test_indirect(ptr addrspace(1) nocapture %arg) {212; CHECK-LABEL: define amdgpu_kernel void @test_indirect(213; CHECK-SAME: ptr addrspace(1) captures(none) [[ARG:%.*]]) #[[ATTR2]] {214; CHECK-NEXT: [[BB:.*:]]215; CHECK-NEXT: [[TMP:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[ARG]], i64 1216; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[ARG]], i64 2217; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[ARG]], i64 3218; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr addrspace(1) [[ARG]], align 4219; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i32> [[TMP4]], i32 0220; CHECK-NEXT: [[TMP6:%.*]] = sext i32 [[TMP5]] to i64221; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[ARG]], i64 [[TMP6]]222; CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr addrspace(1) [[TMP7]], align 4223; CHECK-NEXT: store i32 [[TMP8]], ptr addrspace(1) [[ARG]], align 4224; CHECK-NEXT: [[TMP9:%.*]] = extractelement <4 x i32> [[TMP4]], i32 1225; CHECK-NEXT: [[TMP10:%.*]] = sext i32 [[TMP9]] to i64226; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[ARG]], i64 [[TMP10]]227; CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr addrspace(1) [[TMP11]], align 4228; CHECK-NEXT: store i32 [[TMP12]], ptr addrspace(1) [[TMP]], align 4229; CHECK-NEXT: [[TMP13:%.*]] = extractelement <4 x i32> [[TMP4]], i32 2230; CHECK-NEXT: [[TMP14:%.*]] = sext i32 [[TMP13]] to i64231; CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[ARG]], i64 [[TMP14]]232; CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr addrspace(1) [[TMP15]], align 4233; CHECK-NEXT: store i32 [[TMP16]], ptr addrspace(1) [[TMP1]], align 4234; CHECK-NEXT: [[TMP17:%.*]] = extractelement <4 x i32> [[TMP4]], i32 3235; CHECK-NEXT: [[TMP18:%.*]] = sext i32 [[TMP17]] to i64236; CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds i32, ptr addrspace(1) [[ARG]], i64 [[TMP18]]237; CHECK-NEXT: [[TMP20:%.*]] = load i32, ptr addrspace(1) [[TMP19]], align 4238; CHECK-NEXT: store i32 [[TMP20]], ptr addrspace(1) [[TMP2]], align 4239; CHECK-NEXT: ret void240;241bb:242 %tmp = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 1243 %tmp1 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 2244 %tmp2 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 3245 %tmp4 = load <4 x i32>, ptr addrspace(1) %arg, align 4246 %tmp5 = extractelement <4 x i32> %tmp4, i32 0247 %tmp6 = sext i32 %tmp5 to i64248 %tmp7 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 %tmp6249 %tmp8 = load i32, ptr addrspace(1) %tmp7, align 4250 store i32 %tmp8, ptr addrspace(1) %arg, align 4251 %tmp9 = extractelement <4 x i32> %tmp4, i32 1252 %tmp10 = sext i32 %tmp9 to i64253 %tmp11 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 %tmp10254 %tmp12 = load i32, ptr addrspace(1) %tmp11, align 4255 store i32 %tmp12, ptr addrspace(1) %tmp, align 4256 %tmp13 = extractelement <4 x i32> %tmp4, i32 2257 %tmp14 = sext i32 %tmp13 to i64258 %tmp15 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 %tmp14259 %tmp16 = load i32, ptr addrspace(1) %tmp15, align 4260 store i32 %tmp16, ptr addrspace(1) %tmp1, align 4261 %tmp17 = extractelement <4 x i32> %tmp4, i32 3262 %tmp18 = sext i32 %tmp17 to i64263 %tmp19 = getelementptr inbounds i32, ptr addrspace(1) %arg, i64 %tmp18264 %tmp20 = load i32, ptr addrspace(1) %tmp19, align 4265 store i32 %tmp20, ptr addrspace(1) %tmp2, align 4266 ret void267}268 269; GCN-LABEL: {{^}}test_indirect_through_phi:270; GCN: MemoryBound: 0271; GCN: WaveLimiterHint : 0272define amdgpu_kernel void @test_indirect_through_phi(ptr addrspace(1) %arg) {273; CHECK-LABEL: define amdgpu_kernel void @test_indirect_through_phi(274; CHECK-SAME: ptr addrspace(1) [[ARG:%.*]]) {275; CHECK-NEXT: [[BB:.*]]:276; CHECK-NEXT: [[LOAD:%.*]] = load float, ptr addrspace(1) [[ARG]], align 8277; CHECK-NEXT: [[LOAD_F:%.*]] = bitcast float [[LOAD]] to i32278; CHECK-NEXT: [[N:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()279; CHECK-NEXT: br label %[[BB1:.*]]280; CHECK: [[BB1]]:281; CHECK-NEXT: [[PHI:%.*]] = phi i32 [ [[LOAD_F]], %[[BB]] ], [ [[AND2:%.*]], %[[BB1]] ]282; CHECK-NEXT: [[IND:%.*]] = phi i32 [ 0, %[[BB]] ], [ [[INC2:%.*]], %[[BB1]] ]283; CHECK-NEXT: [[AND1:%.*]] = and i32 [[PHI]], [[N]]284; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[ARG]], i32 [[AND1]]285; CHECK-NEXT: store float [[LOAD]], ptr addrspace(1) [[GEP]], align 4286; CHECK-NEXT: [[INC1:%.*]] = add nsw i32 [[PHI]], 1310720287; CHECK-NEXT: [[AND2]] = and i32 [[INC1]], [[N]]288; CHECK-NEXT: [[INC2]] = add nuw nsw i32 [[IND]], 1289; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[INC2]], 1024290; CHECK-NEXT: br i1 [[CMP]], label %[[BB2:.*]], label %[[BB1]]291; CHECK: [[BB2]]:292; CHECK-NEXT: ret void293;294bb:295 %load = load float, ptr addrspace(1) %arg, align 8296 %load.f = bitcast float %load to i32297 %n = tail call i32 @llvm.amdgcn.workitem.id.x()298 br label %bb1299 300bb1: ; preds = %bb1, %bb301 %phi = phi i32 [ %load.f, %bb ], [ %and2, %bb1 ]302 %ind = phi i32 [ 0, %bb ], [ %inc2, %bb1 ]303 %and1 = and i32 %phi, %n304 %gep = getelementptr inbounds float, ptr addrspace(1) %arg, i32 %and1305 store float %load, ptr addrspace(1) %gep, align 4306 %inc1 = add nsw i32 %phi, 1310720307 %and2 = and i32 %inc1, %n308 %inc2 = add nuw nsw i32 %ind, 1309 %cmp = icmp eq i32 %inc2, 1024310 br i1 %cmp, label %bb2, label %bb1311 312bb2: ; preds = %bb1313 ret void314}315 316define void @test_membound_func(ptr addrspace(1) nocapture readonly %arg, ptr addrspace(1) nocapture %arg1) {317; CHECK-LABEL: define void @test_membound_func(318; CHECK-SAME: ptr addrspace(1) readonly captures(none) [[ARG:%.*]], ptr addrspace(1) captures(none) [[ARG1:%.*]]) #[[ATTR1]] {319; CHECK-NEXT: [[BB:.*:]]320; CHECK-NEXT: [[TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()321; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP]] to i64322; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds <4 x i32>, ptr addrspace(1) [[ARG]], i64 [[TMP2]]323; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr addrspace(1) [[TMP3]], align 16324; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds <4 x i32>, ptr addrspace(1) [[ARG1]], i64 [[TMP2]]325; CHECK-NEXT: store <4 x i32> [[TMP4]], ptr addrspace(1) [[TMP5]], align 16326; CHECK-NEXT: [[TMP6:%.*]] = add nuw nsw i64 [[TMP2]], 1327; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds <4 x i32>, ptr addrspace(1) [[ARG]], i64 [[TMP6]]328; CHECK-NEXT: [[TMP8:%.*]] = load <4 x i32>, ptr addrspace(1) [[TMP7]], align 16329; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds <4 x i32>, ptr addrspace(1) [[ARG1]], i64 [[TMP6]]330; CHECK-NEXT: store <4 x i32> [[TMP8]], ptr addrspace(1) [[TMP9]], align 16331; CHECK-NEXT: ret void332;333bb:334 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()335 %tmp2 = zext i32 %tmp to i64336 %tmp3 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg, i64 %tmp2337 %tmp4 = load <4 x i32>, ptr addrspace(1) %tmp3, align 16338 %tmp5 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg1, i64 %tmp2339 store <4 x i32> %tmp4, ptr addrspace(1) %tmp5, align 16340 %tmp6 = add nuw nsw i64 %tmp2, 1341 %tmp7 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg, i64 %tmp6342 %tmp8 = load <4 x i32>, ptr addrspace(1) %tmp7, align 16343 %tmp9 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg1, i64 %tmp6344 store <4 x i32> %tmp8, ptr addrspace(1) %tmp9, align 16345 ret void346}347 348; GCN-LABEL: {{^}}kernel_call_test_membound_func:349; GCN: MemoryBound: 1350; GCN: WaveLimiterHint : 1351define amdgpu_kernel void @kernel_call_test_membound_func(ptr addrspace(1) nocapture readonly %arg, ptr addrspace(1) nocapture %arg1) {352; CHECK-LABEL: define amdgpu_kernel void @kernel_call_test_membound_func(353; CHECK-SAME: ptr addrspace(1) readonly captures(none) [[ARG:%.*]], ptr addrspace(1) captures(none) [[ARG1:%.*]]) #[[ATTR0]] {354; CHECK-NEXT: call void @test_membound_func(ptr addrspace(1) readonly captures(none) [[ARG]], ptr addrspace(1) captures(none) [[ARG1]])355; CHECK-NEXT: ret void356;357 call void @test_membound_func(ptr addrspace(1) nocapture readonly %arg, ptr addrspace(1) nocapture %arg1)358 ret void359}360 361; TODO: Probably should assume yes?362; GCN-LABEL: {{^}}kernel_indirect_call:363; GCN: MemoryBound: 0364; GCN: WaveLimiterHint : 0365define amdgpu_kernel void @kernel_indirect_call(ptr addrspace(1) nocapture readonly %arg, ptr addrspace(1) nocapture %arg1, ptr %fptr) {366; CHECK-LABEL: define amdgpu_kernel void @kernel_indirect_call(367; CHECK-SAME: ptr addrspace(1) readonly captures(none) [[ARG:%.*]], ptr addrspace(1) captures(none) [[ARG1:%.*]], ptr [[FPTR:%.*]]) {368; CHECK-NEXT: call void [[FPTR]](ptr addrspace(1) readonly captures(none) [[ARG]], ptr addrspace(1) captures(none) [[ARG1]])369; CHECK-NEXT: ret void370;371 call void %fptr(ptr addrspace(1) nocapture readonly %arg, ptr addrspace(1) nocapture %arg1)372 ret void373}374 375declare void @extern()376 377define void @maybe_recursive_test_membound_func(ptr addrspace(1) nocapture readonly %arg, ptr addrspace(1) nocapture %arg1) {378; CHECK-LABEL: define void @maybe_recursive_test_membound_func(379; CHECK-SAME: ptr addrspace(1) readonly captures(none) [[ARG:%.*]], ptr addrspace(1) captures(none) [[ARG1:%.*]]) #[[ATTR1]] {380; CHECK-NEXT: [[BB:.*:]]381; CHECK-NEXT: [[TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()382; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP]] to i64383; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds <4 x i32>, ptr addrspace(1) [[ARG]], i64 [[TMP2]]384; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr addrspace(1) [[TMP3]], align 16385; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds <4 x i32>, ptr addrspace(1) [[ARG1]], i64 [[TMP2]]386; CHECK-NEXT: store <4 x i32> [[TMP4]], ptr addrspace(1) [[TMP5]], align 16387; CHECK-NEXT: [[TMP6:%.*]] = add nuw nsw i64 [[TMP2]], 1388; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds <4 x i32>, ptr addrspace(1) [[ARG]], i64 [[TMP6]]389; CHECK-NEXT: [[TMP8:%.*]] = load <4 x i32>, ptr addrspace(1) [[TMP7]], align 16390; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds <4 x i32>, ptr addrspace(1) [[ARG1]], i64 [[TMP6]]391; CHECK-NEXT: store <4 x i32> [[TMP8]], ptr addrspace(1) [[TMP9]], align 16392; CHECK-NEXT: call void @extern()393; CHECK-NEXT: ret void394;395bb:396 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()397 %tmp2 = zext i32 %tmp to i64398 %tmp3 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg, i64 %tmp2399 %tmp4 = load <4 x i32>, ptr addrspace(1) %tmp3, align 16400 %tmp5 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg1, i64 %tmp2401 store <4 x i32> %tmp4, ptr addrspace(1) %tmp5, align 16402 %tmp6 = add nuw nsw i64 %tmp2, 1403 %tmp7 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg, i64 %tmp6404 %tmp8 = load <4 x i32>, ptr addrspace(1) %tmp7, align 16405 %tmp9 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg1, i64 %tmp6406 store <4 x i32> %tmp8, ptr addrspace(1) %tmp9, align 16407 call void @extern()408 ret void409}410 411; GCN-LABEL: {{^}}kernel_call_maybe_recursive_test_membound_func:412; GCN: MemoryBound: 1413; GCN: WaveLimiterHint : 1414define amdgpu_kernel void @kernel_call_maybe_recursive_test_membound_func(ptr addrspace(1) nocapture readonly %arg, ptr addrspace(1) nocapture %arg1, ptr %fptr) {415; CHECK-LABEL: define amdgpu_kernel void @kernel_call_maybe_recursive_test_membound_func(416; CHECK-SAME: ptr addrspace(1) readonly captures(none) [[ARG:%.*]], ptr addrspace(1) captures(none) [[ARG1:%.*]], ptr [[FPTR:%.*]]) #[[ATTR0]] {417; CHECK-NEXT: call void @maybe_recursive_test_membound_func(ptr addrspace(1) readonly captures(none) [[ARG]], ptr addrspace(1) captures(none) [[ARG1]])418; CHECK-NEXT: ret void419;420 call void @maybe_recursive_test_membound_func(ptr addrspace(1) nocapture readonly %arg, ptr addrspace(1) nocapture %arg1)421 ret void422}423 424define void @mutually_recursive_test_membound_func_0(ptr addrspace(1) nocapture readonly %arg, ptr addrspace(1) nocapture %arg1) {425; CHECK-LABEL: define void @mutually_recursive_test_membound_func_0(426; CHECK-SAME: ptr addrspace(1) readonly captures(none) [[ARG:%.*]], ptr addrspace(1) captures(none) [[ARG1:%.*]]) #[[ATTR1]] {427; CHECK-NEXT: [[TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()428; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP]] to i64429; CHECK-NEXT: [[TMP3:%.*]] = getelementptr inbounds <4 x i32>, ptr addrspace(1) [[ARG]], i64 [[TMP2]]430; CHECK-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr addrspace(1) [[TMP3]], align 16431; CHECK-NEXT: [[TMP5:%.*]] = getelementptr inbounds <4 x i32>, ptr addrspace(1) [[ARG1]], i64 [[TMP2]]432; CHECK-NEXT: store <4 x i32> [[TMP4]], ptr addrspace(1) [[TMP5]], align 16433; CHECK-NEXT: call void @mutually_recursive_test_membound_func_0(ptr addrspace(1) readonly captures(none) [[ARG]], ptr addrspace(1) captures(none) [[ARG1]])434; CHECK-NEXT: ret void435;436 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()437 %tmp2 = zext i32 %tmp to i64438 %tmp3 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg, i64 %tmp2439 %tmp4 = load <4 x i32>, ptr addrspace(1) %tmp3, align 16440 %tmp5 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg1, i64 %tmp2441 store <4 x i32> %tmp4, ptr addrspace(1) %tmp5, align 16442 call void @mutually_recursive_test_membound_func_0(ptr addrspace(1) nocapture readonly %arg, ptr addrspace(1) nocapture %arg1)443 ret void444}445 446define void @mutually_recursive_test_membound_func_1(ptr addrspace(1) nocapture readonly %arg, ptr addrspace(1) nocapture %arg1) {447; CHECK-LABEL: define void @mutually_recursive_test_membound_func_1(448; CHECK-SAME: ptr addrspace(1) readonly captures(none) [[ARG:%.*]], ptr addrspace(1) captures(none) [[ARG1:%.*]]) #[[ATTR1]] {449; CHECK-NEXT: [[TMP:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()450; CHECK-NEXT: [[TMP2:%.*]] = zext i32 [[TMP]] to i64451; CHECK-NEXT: [[TMP6:%.*]] = add nuw nsw i64 [[TMP2]], 1452; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds <4 x i32>, ptr addrspace(1) [[ARG]], i64 [[TMP6]]453; CHECK-NEXT: [[TMP8:%.*]] = load <4 x i32>, ptr addrspace(1) [[TMP7]], align 16454; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds <4 x i32>, ptr addrspace(1) [[ARG1]], i64 [[TMP6]]455; CHECK-NEXT: store <4 x i32> [[TMP8]], ptr addrspace(1) [[TMP9]], align 16456; CHECK-NEXT: call void @mutually_recursive_test_membound_func_1(ptr addrspace(1) readonly captures(none) [[ARG]], ptr addrspace(1) captures(none) [[ARG1]])457; CHECK-NEXT: ret void458;459 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()460 %tmp2 = zext i32 %tmp to i64461 %tmp6 = add nuw nsw i64 %tmp2, 1462 %tmp7 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg, i64 %tmp6463 %tmp8 = load <4 x i32>, ptr addrspace(1) %tmp7, align 16464 %tmp9 = getelementptr inbounds <4 x i32>, ptr addrspace(1) %arg1, i64 %tmp6465 store <4 x i32> %tmp8, ptr addrspace(1) %tmp9, align 16466 call void @mutually_recursive_test_membound_func_1(ptr addrspace(1) nocapture readonly %arg, ptr addrspace(1) nocapture %arg1)467 ret void468}469 470; GCN-LABEL: {{^}}kernel_call_mutually_recursive_test_membound_func_0:471; GCN: MemoryBound: 1472; GCN: WaveLimiterHint : 1473define amdgpu_kernel void @kernel_call_mutually_recursive_test_membound_func_0(ptr addrspace(1) nocapture readonly %arg, ptr addrspace(1) nocapture %arg1, ptr %fptr) {474; CHECK-LABEL: define amdgpu_kernel void @kernel_call_mutually_recursive_test_membound_func_0(475; CHECK-SAME: ptr addrspace(1) readonly captures(none) [[ARG:%.*]], ptr addrspace(1) captures(none) [[ARG1:%.*]], ptr [[FPTR:%.*]]) #[[ATTR0]] {476; CHECK-NEXT: call void @mutually_recursive_test_membound_func_0(ptr addrspace(1) readonly captures(none) [[ARG]], ptr addrspace(1) captures(none) [[ARG1]])477; CHECK-NEXT: ret void478;479 call void @mutually_recursive_test_membound_func_0(ptr addrspace(1) nocapture readonly %arg, ptr addrspace(1) nocapture %arg1)480 ret void481}482 483declare i32 @llvm.amdgcn.workitem.id.x()484 485 486;.487; CHECK: attributes #[[ATTR0]] = { "amdgpu-memory-bound"="true" "amdgpu-wave-limiter"="true" }488; CHECK: attributes #[[ATTR1]] = { "amdgpu-memory-bound"="true" }489; CHECK: attributes #[[ATTR2]] = { "amdgpu-wave-limiter"="true" }490; CHECK: attributes #[[ATTR3:[0-9]+]] = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }491;.492