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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -enable-var-scope -check-prefix=GCN %s3 4define amdgpu_kernel void @lsh8_or_and(ptr addrspace(1) nocapture %arg, i32 %arg1) {5; GCN-LABEL: lsh8_or_and:6; GCN: ; %bb.0: ; %bb7; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x248; GCN-NEXT: s_load_dword s2, s[4:5], 0x2c9; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v010; GCN-NEXT: v_mov_b32_e32 v3, 0x605040011; GCN-NEXT: s_waitcnt lgkmcnt(0)12; GCN-NEXT: v_mov_b32_e32 v1, s113; GCN-NEXT: v_add_u32_e32 v0, vcc, s0, v014; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc15; GCN-NEXT: flat_load_dword v2, v[0:1]16; GCN-NEXT: s_waitcnt vmcnt(0)17; GCN-NEXT: v_perm_b32 v2, v2, s2, v318; GCN-NEXT: flat_store_dword v[0:1], v219; GCN-NEXT: s_endpgm20bb:21 %id = tail call i32 @llvm.amdgcn.workitem.id.x()22 %gep = getelementptr i32, ptr addrspace(1) %arg, i32 %id23 %tmp = load i32, ptr addrspace(1) %gep, align 424 %tmp2 = shl i32 %tmp, 825 %tmp3 = and i32 %arg1, 25526 %tmp4 = or i32 %tmp2, %tmp327 store i32 %tmp4, ptr addrspace(1) %gep, align 428 ret void29}30 31define amdgpu_kernel void @lsr24_or_and(ptr addrspace(1) nocapture %arg, i32 %arg1) {32; GCN-LABEL: lsr24_or_and:33; GCN: ; %bb.0: ; %bb34; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2435; GCN-NEXT: s_load_dword s2, s[4:5], 0x2c36; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v037; GCN-NEXT: v_mov_b32_e32 v3, 0x706050338; GCN-NEXT: s_waitcnt lgkmcnt(0)39; GCN-NEXT: v_mov_b32_e32 v1, s140; GCN-NEXT: v_add_u32_e32 v0, vcc, s0, v041; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc42; GCN-NEXT: flat_load_dword v2, v[0:1]43; GCN-NEXT: s_waitcnt vmcnt(0)44; GCN-NEXT: v_perm_b32 v2, s2, v2, v345; GCN-NEXT: flat_store_dword v[0:1], v246; GCN-NEXT: s_endpgm47bb:48 %id = tail call i32 @llvm.amdgcn.workitem.id.x()49 %gep = getelementptr i32, ptr addrspace(1) %arg, i32 %id50 %tmp = load i32, ptr addrspace(1) %gep, align 451 %tmp2 = lshr i32 %tmp, 2452 %tmp3 = and i32 %arg1, 4294967040 ; 0xffffff0053 %tmp4 = or i32 %tmp2, %tmp354 store i32 %tmp4, ptr addrspace(1) %gep, align 455 ret void56}57 58define amdgpu_kernel void @and_or_lsr24(ptr addrspace(1) nocapture %arg, i32 %arg1) {59; GCN-LABEL: and_or_lsr24:60; GCN: ; %bb.0: ; %bb61; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2462; GCN-NEXT: s_load_dword s2, s[4:5], 0x2c63; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v064; GCN-NEXT: v_mov_b32_e32 v3, 0x706050365; GCN-NEXT: s_waitcnt lgkmcnt(0)66; GCN-NEXT: v_mov_b32_e32 v1, s167; GCN-NEXT: v_add_u32_e32 v0, vcc, s0, v068; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc69; GCN-NEXT: flat_load_dword v2, v[0:1]70; GCN-NEXT: s_waitcnt vmcnt(0)71; GCN-NEXT: v_perm_b32 v2, v2, s2, v372; GCN-NEXT: v_xor_b32_e32 v2, 0x80000000, v273; GCN-NEXT: flat_store_dword v[0:1], v274; GCN-NEXT: s_endpgm75bb:76 %id = tail call i32 @llvm.amdgcn.workitem.id.x()77 %gep = getelementptr i32, ptr addrspace(1) %arg, i32 %id78 %tmp = load i32, ptr addrspace(1) %gep, align 479 %tmp2 = and i32 %tmp, 4294967040 ; 0xffffff0080 %tmp3 = lshr i32 %arg1, 2481 %tmp4 = or i32 %tmp2, %tmp382 %tmp5 = xor i32 %tmp4, -214748364883 store i32 %tmp5, ptr addrspace(1) %gep, align 484 ret void85}86 87define amdgpu_kernel void @and_or_and(ptr addrspace(1) nocapture %arg, i32 %arg1) {88; GCN-LABEL: and_or_and:89; GCN: ; %bb.0: ; %bb90; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x2491; GCN-NEXT: s_load_dword s2, s[4:5], 0x2c92; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v093; GCN-NEXT: v_mov_b32_e32 v3, 0x702050094; GCN-NEXT: s_waitcnt lgkmcnt(0)95; GCN-NEXT: v_mov_b32_e32 v1, s196; GCN-NEXT: v_add_u32_e32 v0, vcc, s0, v097; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc98; GCN-NEXT: flat_load_dword v2, v[0:1]99; GCN-NEXT: s_waitcnt vmcnt(0)100; GCN-NEXT: v_perm_b32 v2, v2, s2, v3101; GCN-NEXT: flat_store_dword v[0:1], v2102; GCN-NEXT: s_endpgm103bb:104 %id = tail call i32 @llvm.amdgcn.workitem.id.x()105 %gep = getelementptr i32, ptr addrspace(1) %arg, i32 %id106 %tmp = load i32, ptr addrspace(1) %gep, align 4107 %tmp2 = and i32 %tmp, -16711936108 %tmp3 = and i32 %arg1, 16711935109 %tmp4 = or i32 %tmp2, %tmp3110 store i32 %tmp4, ptr addrspace(1) %gep, align 4111 ret void112}113 114; FIXME: produce v_alignbit_b32 v2, v2, s0, 24 instead of v_perm115define amdgpu_kernel void @lsh8_or_lsr24(ptr addrspace(1) nocapture %arg, i32 %arg1) {116; GCN-LABEL: lsh8_or_lsr24:117; GCN: ; %bb.0: ; %bb118; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24119; GCN-NEXT: s_load_dword s2, s[4:5], 0x2c120; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v0121; GCN-NEXT: v_mov_b32_e32 v3, 0x2010007122; GCN-NEXT: s_waitcnt lgkmcnt(0)123; GCN-NEXT: v_mov_b32_e32 v1, s1124; GCN-NEXT: v_add_u32_e32 v0, vcc, s0, v0125; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc126; GCN-NEXT: flat_load_dword v2, v[0:1]127; GCN-NEXT: s_waitcnt vmcnt(0)128; GCN-NEXT: v_perm_b32 v2, s2, v2, v3129; GCN-NEXT: flat_store_dword v[0:1], v2130; GCN-NEXT: s_endpgm131bb:132 %id = tail call i32 @llvm.amdgcn.workitem.id.x()133 %gep = getelementptr i32, ptr addrspace(1) %arg, i32 %id134 %tmp = load i32, ptr addrspace(1) %gep, align 4135 %tmp2 = shl i32 %tmp, 8136 %tmp3 = lshr i32 %arg1, 24137 %tmp4 = or i32 %tmp2, %tmp3138 store i32 %tmp4, ptr addrspace(1) %gep, align 4139 ret void140}141 142define amdgpu_kernel void @lsh16_or_lsr24(ptr addrspace(1) nocapture %arg, i32 %arg1) {143; GCN-LABEL: lsh16_or_lsr24:144; GCN: ; %bb.0: ; %bb145; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24146; GCN-NEXT: s_load_dword s2, s[4:5], 0x2c147; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v0148; GCN-NEXT: v_mov_b32_e32 v3, 0x5040c03149; GCN-NEXT: s_waitcnt lgkmcnt(0)150; GCN-NEXT: v_mov_b32_e32 v1, s1151; GCN-NEXT: v_add_u32_e32 v0, vcc, s0, v0152; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc153; GCN-NEXT: flat_load_dword v2, v[0:1]154; GCN-NEXT: s_waitcnt vmcnt(0)155; GCN-NEXT: v_perm_b32 v2, v2, s2, v3156; GCN-NEXT: flat_store_dword v[0:1], v2157; GCN-NEXT: s_endpgm158bb:159 %id = tail call i32 @llvm.amdgcn.workitem.id.x()160 %gep = getelementptr i32, ptr addrspace(1) %arg, i32 %id161 %tmp = load i32, ptr addrspace(1) %gep, align 4162 %tmp2 = shl i32 %tmp, 16163 %tmp3 = lshr i32 %arg1, 24164 %tmp4 = or i32 %tmp2, %tmp3165 store i32 %tmp4, ptr addrspace(1) %gep, align 4166 ret void167}168 169define amdgpu_kernel void @and_xor_and(ptr addrspace(1) nocapture %arg, i32 %arg1) {170; GCN-LABEL: and_xor_and:171; GCN: ; %bb.0: ; %bb172; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24173; GCN-NEXT: s_load_dword s2, s[4:5], 0x2c174; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v0175; GCN-NEXT: v_mov_b32_e32 v3, 0x7020104176; GCN-NEXT: s_waitcnt lgkmcnt(0)177; GCN-NEXT: v_mov_b32_e32 v1, s1178; GCN-NEXT: v_add_u32_e32 v0, vcc, s0, v0179; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc180; GCN-NEXT: flat_load_dword v2, v[0:1]181; GCN-NEXT: s_waitcnt vmcnt(0)182; GCN-NEXT: v_perm_b32 v2, v2, s2, v3183; GCN-NEXT: flat_store_dword v[0:1], v2184; GCN-NEXT: s_endpgm185bb:186 %id = tail call i32 @llvm.amdgcn.workitem.id.x()187 %gep = getelementptr i32, ptr addrspace(1) %arg, i32 %id188 %tmp = load i32, ptr addrspace(1) %gep, align 4189 %tmp2 = and i32 %tmp, -16776961190 %tmp3 = and i32 %arg1, 16776960191 %tmp4 = xor i32 %tmp2, %tmp3192 store i32 %tmp4, ptr addrspace(1) %gep, align 4193 ret void194}195 196; FIXME here should have been "v_perm_b32" with 0xffff0500 mask.197define amdgpu_kernel void @and_or_or_and(ptr addrspace(1) nocapture %arg, i32 %arg1) {198; GCN-LABEL: and_or_or_and:199; GCN: ; %bb.0: ; %bb200; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24201; GCN-NEXT: s_load_dword s2, s[4:5], 0x2c202; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v0203; GCN-NEXT: s_waitcnt lgkmcnt(0)204; GCN-NEXT: v_mov_b32_e32 v1, s1205; GCN-NEXT: v_add_u32_e32 v0, vcc, s0, v0206; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc207; GCN-NEXT: flat_load_dword v2, v[0:1]208; GCN-NEXT: s_and_b32 s0, s2, 0xff00209; GCN-NEXT: s_or_b32 s0, s0, 0xffff0000210; GCN-NEXT: s_waitcnt vmcnt(0)211; GCN-NEXT: v_and_b32_e32 v2, 0xff00ff, v2212; GCN-NEXT: v_or_b32_e32 v2, s0, v2213; GCN-NEXT: flat_store_dword v[0:1], v2214; GCN-NEXT: s_endpgm215bb:216 %id = tail call i32 @llvm.amdgcn.workitem.id.x()217 %gep = getelementptr i32, ptr addrspace(1) %arg, i32 %id218 %tmp = load i32, ptr addrspace(1) %gep, align 4219 %and = and i32 %tmp, 16711935 ; 0x00ff00ff220 %tmp1 = and i32 %arg1, 4294967040 ; 0xffffff00221 %tmp2 = or i32 %tmp1, -65536222 %tmp3 = or i32 %tmp2, %and223 store i32 %tmp3, ptr addrspace(1) %gep, align 4224 ret void225}226 227define amdgpu_kernel void @and_or_and_shl(ptr addrspace(1) nocapture %arg, i32 %arg1) {228; GCN-LABEL: and_or_and_shl:229; GCN: ; %bb.0: ; %bb230; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24231; GCN-NEXT: s_load_dword s2, s[4:5], 0x2c232; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v0233; GCN-NEXT: v_mov_b32_e32 v3, 0x50c0c00234; GCN-NEXT: s_waitcnt lgkmcnt(0)235; GCN-NEXT: v_mov_b32_e32 v1, s1236; GCN-NEXT: v_add_u32_e32 v0, vcc, s0, v0237; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc238; GCN-NEXT: flat_load_dword v2, v[0:1]239; GCN-NEXT: s_waitcnt vmcnt(0)240; GCN-NEXT: v_perm_b32 v2, v2, s2, v3241; GCN-NEXT: flat_store_dword v[0:1], v2242; GCN-NEXT: s_endpgm243bb:244 %id = tail call i32 @llvm.amdgcn.workitem.id.x()245 %gep = getelementptr i32, ptr addrspace(1) %arg, i32 %id246 %tmp = load i32, ptr addrspace(1) %gep, align 4247 %tmp2 = shl i32 %tmp, 16248 %tmp3 = and i32 %arg1, 65535249 %tmp4 = or i32 %tmp2, %tmp3250 %and = and i32 %tmp4, 4278190335251 store i32 %and, ptr addrspace(1) %gep, align 4252 ret void253}254 255define amdgpu_kernel void @or_and_or(ptr addrspace(1) nocapture %arg, i32 %arg1) {256; GCN-LABEL: or_and_or:257; GCN: ; %bb.0: ; %bb258; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24259; GCN-NEXT: s_load_dword s2, s[4:5], 0x2c260; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v0261; GCN-NEXT: v_mov_b32_e32 v3, 0x7020104262; GCN-NEXT: s_waitcnt lgkmcnt(0)263; GCN-NEXT: v_mov_b32_e32 v1, s1264; GCN-NEXT: v_add_u32_e32 v0, vcc, s0, v0265; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc266; GCN-NEXT: flat_load_dword v2, v[0:1]267; GCN-NEXT: s_waitcnt vmcnt(0)268; GCN-NEXT: v_perm_b32 v2, v2, s2, v3269; GCN-NEXT: flat_store_dword v[0:1], v2270; GCN-NEXT: s_endpgm271bb:272 %id = tail call i32 @llvm.amdgcn.workitem.id.x()273 %gep = getelementptr i32, ptr addrspace(1) %arg, i32 %id274 %tmp = load i32, ptr addrspace(1) %gep, align 4275 %or1 = or i32 %tmp, 16776960 ; 0x00ffff00276 %or2 = or i32 %arg1, 4278190335 ; 0xff0000ff277 %and = and i32 %or1, %or2278 store i32 %and, ptr addrspace(1) %gep, align 4279 ret void280}281 282; FIXME here should have been "v_perm_b32" with 0xffff0500 mask.283define amdgpu_kernel void @known_ffff0500(ptr addrspace(1) nocapture %arg, i32 %arg1) {284; GCN-LABEL: known_ffff0500:285; GCN: ; %bb.0: ; %bb286; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24287; GCN-NEXT: s_load_dword s2, s[4:5], 0x2c288; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v0289; GCN-NEXT: v_mov_b32_e32 v5, 0xffff8004290; GCN-NEXT: s_waitcnt lgkmcnt(0)291; GCN-NEXT: v_mov_b32_e32 v1, s1292; GCN-NEXT: v_add_u32_e32 v0, vcc, s0, v0293; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc294; GCN-NEXT: flat_load_dword v4, v[0:1]295; GCN-NEXT: s_bitset1_b32 s2, 15296; GCN-NEXT: v_mov_b32_e32 v3, s1297; GCN-NEXT: v_mov_b32_e32 v2, s0298; GCN-NEXT: s_and_b32 s0, s2, 0xff00299; GCN-NEXT: s_or_b32 s0, s0, 0xffff0000300; GCN-NEXT: s_waitcnt vmcnt(0)301; GCN-NEXT: v_or_b32_e32 v4, 4, v4302; GCN-NEXT: v_and_b32_e32 v4, 0xff00ff, v4303; GCN-NEXT: v_or_b32_e32 v4, s0, v4304; GCN-NEXT: flat_store_dword v[0:1], v4305; GCN-NEXT: flat_store_dword v[2:3], v5306; GCN-NEXT: s_endpgm307bb:308 %id = tail call i32 @llvm.amdgcn.workitem.id.x()309 %gep = getelementptr i32, ptr addrspace(1) %arg, i32 %id310 %load = load i32, ptr addrspace(1) %gep, align 4311 %mask1 = or i32 %arg1, 32768 ; 0x8000312 %mask2 = or i32 %load, 4313 %and = and i32 %mask2, 16711935 ; 0x00ff00ff314 %tmp1 = and i32 %mask1, 4294967040 ; 0xffffff00315 %tmp2 = or i32 %tmp1, 4294901760 ; 0xffff0000316 %tmp3 = or i32 %tmp2, %and317 store i32 %tmp3, ptr addrspace(1) %gep, align 4318 %v = and i32 %tmp3, 4294934532 ; 0xffff8004319 store i32 %v, ptr addrspace(1) %arg, align 4320 ret void321}322 323define amdgpu_kernel void @known_050c0c00(ptr addrspace(1) nocapture %arg, i32 %arg1) {324; GCN-LABEL: known_050c0c00:325; GCN: ; %bb.0: ; %bb326; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24327; GCN-NEXT: s_load_dword s2, s[4:5], 0x2c328; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v0329; GCN-NEXT: v_mov_b32_e32 v5, 0x50c0c00330; GCN-NEXT: v_mov_b32_e32 v6, 4331; GCN-NEXT: s_waitcnt lgkmcnt(0)332; GCN-NEXT: v_mov_b32_e32 v1, s1333; GCN-NEXT: v_add_u32_e32 v0, vcc, s0, v0334; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc335; GCN-NEXT: flat_load_dword v4, v[0:1]336; GCN-NEXT: s_or_b32 s2, s2, 4337; GCN-NEXT: v_mov_b32_e32 v3, s1338; GCN-NEXT: v_mov_b32_e32 v2, s0339; GCN-NEXT: s_waitcnt vmcnt(0)340; GCN-NEXT: v_perm_b32 v4, v4, s2, v5341; GCN-NEXT: flat_store_dword v[0:1], v4342; GCN-NEXT: flat_store_dword v[2:3], v6343; GCN-NEXT: s_endpgm344bb:345 %id = tail call i32 @llvm.amdgcn.workitem.id.x()346 %gep = getelementptr i32, ptr addrspace(1) %arg, i32 %id347 %tmp = load i32, ptr addrspace(1) %gep, align 4348 %tmp2 = shl i32 %tmp, 16349 %mask = or i32 %arg1, 4350 %tmp3 = and i32 %mask, 65535351 %tmp4 = or i32 %tmp2, %tmp3352 %and = and i32 %tmp4, 4278190335353 store i32 %and, ptr addrspace(1) %gep, align 4354 %v = and i32 %and, 16776964355 store i32 %v, ptr addrspace(1) %arg, align 4356 ret void357}358 359define amdgpu_kernel void @known_ffff8004(ptr addrspace(1) nocapture %arg, i32 %arg1) {360; GCN-LABEL: known_ffff8004:361; GCN: ; %bb.0: ; %bb362; GCN-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24363; GCN-NEXT: s_load_dword s2, s[4:5], 0x2c364; GCN-NEXT: v_lshlrev_b32_e32 v0, 2, v0365; GCN-NEXT: v_mov_b32_e32 v5, 0xffff0500366; GCN-NEXT: v_mov_b32_e32 v6, 0xffff8004367; GCN-NEXT: s_waitcnt lgkmcnt(0)368; GCN-NEXT: v_mov_b32_e32 v1, s1369; GCN-NEXT: v_add_u32_e32 v0, vcc, s0, v0370; GCN-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc371; GCN-NEXT: flat_load_dword v4, v[0:1]372; GCN-NEXT: s_or_b32 s2, s2, 4373; GCN-NEXT: v_mov_b32_e32 v3, s1374; GCN-NEXT: v_mov_b32_e32 v2, s0375; GCN-NEXT: s_waitcnt vmcnt(0)376; GCN-NEXT: v_or_b32_e32 v4, 0x8000, v4377; GCN-NEXT: v_perm_b32 v4, v4, s2, v5378; GCN-NEXT: flat_store_dword v[0:1], v4379; GCN-NEXT: flat_store_dword v[2:3], v6380; GCN-NEXT: s_endpgm381bb:382 %id = tail call i32 @llvm.amdgcn.workitem.id.x()383 %gep = getelementptr i32, ptr addrspace(1) %arg, i32 %id384 %load = load i32, ptr addrspace(1) %gep, align 4385 %mask1 = or i32 %arg1, 4386 %mask2 = or i32 %load, 32768 ; 0x8000387 %and = and i32 %mask1, 16711935 ; 0x00ff00ff388 %tmp1 = and i32 %mask2, 4294967040 ; 0xffffff00389 %tmp2 = or i32 %tmp1, 4294901760 ; 0xffff0000390 %tmp3 = or i32 %tmp2, %and391 store i32 %tmp3, ptr addrspace(1) %gep, align 4392 %v = and i32 %tmp3, 4294934532 ; 0xffff8004393 store i32 %v, ptr addrspace(1) %arg, align 4394 ret void395}396 397declare i32 @llvm.amdgcn.workitem.id.x()398