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1; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN,GFX9 %s2; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GCN,GFX10 %s3; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefixes=GCN,GFX10 %s4 5; GCN-LABEL: {{^}}test_pk_max_f16_literal_0_1:6; GCN: v_pk_max_f16 v{{[0-9]+}}, v{{[0-9]+}}, 1.0 op_sel:[0,1] op_sel_hi:[1,0]{{$}}7define amdgpu_kernel void @test_pk_max_f16_literal_0_1(ptr addrspace(1) nocapture %arg) {8bb:9 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()10 %tmp1 = zext i32 %tmp to i6411 %tmp2 = getelementptr inbounds <2 x half>, ptr addrspace(1) %arg, i64 %tmp112 %tmp3 = load <2 x half>, ptr addrspace(1) %tmp2, align 413 %tmp4 = tail call <2 x half> @llvm.maxnum.v2f16(<2 x half> %tmp3, <2 x half> <half 0xH0000, half 0xH3C00>)14 store <2 x half> %tmp4, ptr addrspace(1) %tmp2, align 415 ret void16}17 18; GCN-LABEL: {{^}}test_pk_max_f16_literal_1_0:19; GCN: v_pk_max_f16 v{{[0-9]+}}, v{{[0-9]+}}, 1.0{{$}}20define amdgpu_kernel void @test_pk_max_f16_literal_1_0(ptr addrspace(1) nocapture %arg) {21bb:22 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()23 %tmp1 = zext i32 %tmp to i6424 %tmp2 = getelementptr inbounds <2 x half>, ptr addrspace(1) %arg, i64 %tmp125 %tmp3 = load <2 x half>, ptr addrspace(1) %tmp2, align 426 %tmp4 = tail call <2 x half> @llvm.maxnum.v2f16(<2 x half> %tmp3, <2 x half> <half 0xH3C00, half 0xH0000>)27 store <2 x half> %tmp4, ptr addrspace(1) %tmp2, align 428 ret void29}30 31; GCN-LABEL: {{^}}test_pk_max_f16_literal_1_1:32; GCN: v_pk_max_f16 v{{[0-9]+}}, v{{[0-9]+}}, 1.0 op_sel_hi:[1,0]{{$}}33define amdgpu_kernel void @test_pk_max_f16_literal_1_1(ptr addrspace(1) nocapture %arg) {34bb:35 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()36 %tmp1 = zext i32 %tmp to i6437 %tmp2 = getelementptr inbounds <2 x half>, ptr addrspace(1) %arg, i64 %tmp138 %tmp3 = load <2 x half>, ptr addrspace(1) %tmp2, align 439 %tmp4 = tail call <2 x half> @llvm.maxnum.v2f16(<2 x half> %tmp3, <2 x half> <half 0xH3C00, half 0xH3C00>)40 store <2 x half> %tmp4, ptr addrspace(1) %tmp2, align 441 ret void42}43 44; GCN-LABEL: {{^}}test_pk_max_f16_literal_0_m1:45; GCN: v_pk_max_f16 v{{[0-9]+}}, v{{[0-9]+}}, -1.0 op_sel:[0,1] op_sel_hi:[1,0]{{$}}46define amdgpu_kernel void @test_pk_max_f16_literal_0_m1(ptr addrspace(1) nocapture %arg) {47bb:48 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()49 %tmp1 = zext i32 %tmp to i6450 %tmp2 = getelementptr inbounds <2 x half>, ptr addrspace(1) %arg, i64 %tmp151 %tmp3 = load <2 x half>, ptr addrspace(1) %tmp2, align 452 %tmp4 = tail call <2 x half> @llvm.maxnum.v2f16(<2 x half> %tmp3, <2 x half> <half 0xH0000, half 0xHBC00>)53 store <2 x half> %tmp4, ptr addrspace(1) %tmp2, align 454 ret void55}56 57; GCN-LABEL: {{^}}test_pk_max_f16_literal_m1_0:58; GCN: v_pk_max_f16 v{{[0-9]+}}, v{{[0-9]+}}, -1.0{{$}}59define amdgpu_kernel void @test_pk_max_f16_literal_m1_0(ptr addrspace(1) nocapture %arg) {60bb:61 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()62 %tmp1 = zext i32 %tmp to i6463 %tmp2 = getelementptr inbounds <2 x half>, ptr addrspace(1) %arg, i64 %tmp164 %tmp3 = load <2 x half>, ptr addrspace(1) %tmp2, align 465 %tmp4 = tail call <2 x half> @llvm.maxnum.v2f16(<2 x half> %tmp3, <2 x half> <half 0xHBC00, half 0xH0000>)66 store <2 x half> %tmp4, ptr addrspace(1) %tmp2, align 467 ret void68}69 70; GCN-LABEL: {{^}}test_pk_max_f16_literal_m1_m1:71; GCN: v_pk_max_f16 v{{[0-9]+}}, v{{[0-9]+}}, -1.0 op_sel_hi:[1,0]{{$}}72define amdgpu_kernel void @test_pk_max_f16_literal_m1_m1(ptr addrspace(1) nocapture %arg) {73bb:74 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()75 %tmp1 = zext i32 %tmp to i6476 %tmp2 = getelementptr inbounds <2 x half>, ptr addrspace(1) %arg, i64 %tmp177 %tmp3 = load <2 x half>, ptr addrspace(1) %tmp2, align 478 %tmp4 = tail call <2 x half> @llvm.maxnum.v2f16(<2 x half> %tmp3, <2 x half> <half 0xHBC00, half 0xHBC00>)79 store <2 x half> %tmp4, ptr addrspace(1) %tmp2, align 480 ret void81}82 83; GCN-LABEL: {{^}}test_pk_max_f16_literal_0_0:84; GCN: v_pk_max_f16 v{{[0-9]+}}, v{{[0-9]+}}, 0{{$}}85define amdgpu_kernel void @test_pk_max_f16_literal_0_0(ptr addrspace(1) nocapture %arg) {86bb:87 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()88 %tmp1 = zext i32 %tmp to i6489 %tmp2 = getelementptr inbounds <2 x half>, ptr addrspace(1) %arg, i64 %tmp190 %tmp3 = load <2 x half>, ptr addrspace(1) %tmp2, align 491 %tmp4 = tail call <2 x half> @llvm.maxnum.v2f16(<2 x half> %tmp3, <2 x half> <half 0xH0000, half 0xH0000>)92 store <2 x half> %tmp4, ptr addrspace(1) %tmp2, align 493 ret void94}95 96; GCN-LABEL: {{^}}test_pk_max_f16_literal_0_41c8:97; GFX9: s_mov_b32 [[C:s[0-9]+]], 0x41c8000098; GFX9: v_pk_max_f16 v{{[0-9]+}}, v{{[0-9]+}}, [[C]]{{$}}99; GFX10: v_pk_max_f16 v{{[0-9]+}}, 0x41c80000, v{{[0-9]+}}{{$}}100define amdgpu_kernel void @test_pk_max_f16_literal_0_41c8(ptr addrspace(1) nocapture %arg) {101bb:102 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()103 %tmp1 = zext i32 %tmp to i64104 %tmp2 = getelementptr inbounds <2 x half>, ptr addrspace(1) %arg, i64 %tmp1105 %tmp3 = load <2 x half>, ptr addrspace(1) %tmp2, align 4106 %tmp4 = tail call <2 x half> @llvm.maxnum.v2f16(<2 x half> %tmp3, <2 x half> <half 0xH0000, half 0xH41C8>)107 store <2 x half> %tmp4, ptr addrspace(1) %tmp2, align 4108 ret void109}110 111; GCN-LABEL: {{^}}test_pk_max_f16_literal_41c8_0:112; GFX9: s_movk_i32 [[C:s[0-9]+]], 0x41c8113; GFX9: v_pk_max_f16 v{{[0-9]+}}, v{{[0-9]+}}, [[C]]{{$}}114; GFX10: v_pk_max_f16 v{{[0-9]+}}, 0x41c8, v{{[0-9]+}}{{$}}115define amdgpu_kernel void @test_pk_max_f16_literal_41c8_0(ptr addrspace(1) nocapture %arg) {116bb:117 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()118 %tmp1 = zext i32 %tmp to i64119 %tmp2 = getelementptr inbounds <2 x half>, ptr addrspace(1) %arg, i64 %tmp1120 %tmp3 = load <2 x half>, ptr addrspace(1) %tmp2, align 4121 %tmp4 = tail call <2 x half> @llvm.maxnum.v2f16(<2 x half> %tmp3, <2 x half> <half 0xH41C8, half 0xH0>)122 store <2 x half> %tmp4, ptr addrspace(1) %tmp2, align 4123 ret void124}125 126; GCN-LABEL: {{^}}test_pk_max_f16_literal_42ca_41c8:127; GFX9: s_mov_b32 [[C:s[0-9]+]], 0x41c842ca128; GFX9: v_pk_max_f16 v{{[0-9]+}}, v{{[0-9]+}}, [[C]]{{$}}129; GFX10: v_pk_max_f16 v{{[0-9]+}}, 0x41c842ca, v{{[0-9]+}}{{$}}130define amdgpu_kernel void @test_pk_max_f16_literal_42ca_41c8(ptr addrspace(1) nocapture %arg) {131bb:132 %tmp = tail call i32 @llvm.amdgcn.workitem.id.x()133 %tmp1 = zext i32 %tmp to i64134 %tmp2 = getelementptr inbounds <2 x half>, ptr addrspace(1) %arg, i64 %tmp1135 %tmp3 = load <2 x half>, ptr addrspace(1) %tmp2, align 4136 %tmp4 = tail call <2 x half> @llvm.maxnum.v2f16(<2 x half> %tmp3, <2 x half> <half 0xH42CA, half 0xH41C8>)137 store <2 x half> %tmp4, ptr addrspace(1) %tmp2, align 4138 ret void139}140 141declare <2 x half> @llvm.maxnum.v2f16(<2 x half>, <2 x half>)142declare i32 @llvm.amdgcn.workitem.id.x()143