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1; RUN: llc -spec-exec-max-speculation-cost=0 -mtriple=r600 -r600-ir-structurize=0 -mcpu=redwood < %s | FileCheck %s2 3; These tests make sure the compiler is optimizing branches using predicates4; when it is legal to do so.5 6; CHECK-LABEL: {{^}}simple_if:7; CHECK: PRED_SET{{[EGN][ET]*}}_INT * Pred,8; CHECK: LSHL * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, Pred_sel9define amdgpu_kernel void @simple_if(ptr addrspace(1) %out, i32 %in) {10entry:11 %cmp0 = icmp sgt i32 %in, 012 br i1 %cmp0, label %IF, label %ENDIF13 14IF:15 %tmp1 = shl i32 %in, 116 br label %ENDIF17 18ENDIF:19 %tmp2 = phi i32 [ %in, %entry ], [ %tmp1, %IF ]20 store i32 %tmp2, ptr addrspace(1) %out21 ret void22}23 24; CHECK-LABEL: {{^}}simple_if_else:25; CHECK: PRED_SET{{[EGN][ET]*}}_INT * Pred,26; CHECK: LSH{{[LR] \* T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, Pred_sel27; CHECK: LSH{{[LR] \* T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, Pred_sel28define amdgpu_kernel void @simple_if_else(ptr addrspace(1) %out, i32 %in) {29entry:30 %0 = icmp sgt i32 %in, 031 br i1 %0, label %IF, label %ELSE32 33IF:34 %1 = shl i32 %in, 135 br label %ENDIF36 37ELSE:38 %2 = lshr i32 %in, 139 br label %ENDIF40 41ENDIF:42 %3 = phi i32 [ %1, %IF ], [ %2, %ELSE ]43 store i32 %3, ptr addrspace(1) %out44 ret void45}46 47; CHECK-LABEL: {{^}}nested_if:48; CHECK: ALU_PUSH_BEFORE49; CHECK: JUMP50; CHECK: POP51; CHECK: PRED_SET{{[EGN][ET]*}}_INT * Exec52; CHECK: PRED_SET{{[EGN][ET]*}}_INT * Pred,53; CHECK: LSHL * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, Pred_sel54define amdgpu_kernel void @nested_if(ptr addrspace(1) %out, i32 %in) {55entry:56 %0 = icmp sgt i32 %in, 057 br i1 %0, label %IF0, label %ENDIF58 59IF0:60 %1 = add i32 %in, 1061 %2 = icmp sgt i32 %1, 062 br i1 %2, label %IF1, label %ENDIF63 64IF1:65 %3 = shl i32 %1, 166 br label %ENDIF67 68ENDIF:69 %4 = phi i32 [%in, %entry], [%1, %IF0], [%3, %IF1]70 store i32 %4, ptr addrspace(1) %out71 ret void72}73 74; CHECK-LABEL: {{^}}nested_if_else:75; CHECK: ALU_PUSH_BEFORE76; CHECK: JUMP77; CHECK: POP78; CHECK: PRED_SET{{[EGN][ET]*}}_INT * Exec79; CHECK: PRED_SET{{[EGN][ET]*}}_INT * Pred,80; CHECK: LSH{{[LR] \* T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, Pred_sel81; CHECK: LSH{{[LR] \* T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, 1, Pred_sel82define amdgpu_kernel void @nested_if_else(ptr addrspace(1) %out, i32 %in) {83entry:84 %0 = icmp sgt i32 %in, 085 br i1 %0, label %IF0, label %ENDIF86 87IF0:88 %1 = add i32 %in, 1089 %2 = icmp sgt i32 %1, 090 br i1 %2, label %IF1, label %ELSE191 92IF1:93 %3 = shl i32 %1, 194 br label %ENDIF95 96ELSE1:97 %4 = lshr i32 %in, 198 br label %ENDIF99 100ENDIF:101 %5 = phi i32 [%in, %entry], [%3, %IF1], [%4, %ELSE1]102 store i32 %5, ptr addrspace(1) %out103 ret void104}105