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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 42; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx942 < %s | FileCheck -check-prefixes=GFX942 %s3; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx90a < %s | FileCheck -check-prefixes=GFX90a %s4; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx1250 < %s | FileCheck -check-prefixes=GFX1250 %s5 6define amdgpu_kernel void @ptr1_i8(ptr addrspace(1) inreg %out, i8 inreg %arg0) #0 {7; GFX942-LABEL: ptr1_i8:8; GFX942: ; %bb.1:9; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x010; GFX942-NEXT: s_load_dword s4, s[0:1], 0x811; GFX942-NEXT: s_waitcnt lgkmcnt(0)12; GFX942-NEXT: s_branch .LBB0_013; GFX942-NEXT: .p2align 814; GFX942-NEXT: ; %bb.2:15; GFX942-NEXT: .LBB0_0:16; GFX942-NEXT: s_and_b32 s0, s4, 0xff17; GFX942-NEXT: v_mov_b32_e32 v0, 018; GFX942-NEXT: v_mov_b32_e32 v1, s019; GFX942-NEXT: global_store_dword v0, v1, s[2:3]20; GFX942-NEXT: s_endpgm21;22; GFX90a-LABEL: ptr1_i8:23; GFX90a: ; %bb.1:24; GFX90a-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x025; GFX90a-NEXT: s_load_dword s10, s[4:5], 0x826; GFX90a-NEXT: s_waitcnt lgkmcnt(0)27; GFX90a-NEXT: s_branch .LBB0_028; GFX90a-NEXT: .p2align 829; GFX90a-NEXT: ; %bb.2:30; GFX90a-NEXT: .LBB0_0:31; GFX90a-NEXT: s_and_b32 s0, s10, 0xff32; GFX90a-NEXT: v_mov_b32_e32 v0, 033; GFX90a-NEXT: v_mov_b32_e32 v1, s034; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]35; GFX90a-NEXT: s_endpgm36;37; GFX1250-LABEL: ptr1_i8:38; GFX1250: ; %bb.0:39; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 140; GFX1250-NEXT: s_and_b32 s0, s4, 0xff41; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)42; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s043; GFX1250-NEXT: global_store_b32 v0, v1, s[2:3]44; GFX1250-NEXT: s_endpgm45 %ext = zext i8 %arg0 to i3246 store i32 %ext, ptr addrspace(1) %out47 ret void48}49 50define amdgpu_kernel void @ptr1_i8_zext_arg(ptr addrspace(1) inreg %out, i8 zeroext inreg %arg0) #0 {51; GFX942-LABEL: ptr1_i8_zext_arg:52; GFX942: ; %bb.1:53; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x054; GFX942-NEXT: s_load_dword s4, s[0:1], 0x855; GFX942-NEXT: s_waitcnt lgkmcnt(0)56; GFX942-NEXT: s_branch .LBB1_057; GFX942-NEXT: .p2align 858; GFX942-NEXT: ; %bb.2:59; GFX942-NEXT: .LBB1_0:60; GFX942-NEXT: s_and_b32 s0, s4, 0xff61; GFX942-NEXT: v_mov_b32_e32 v0, 062; GFX942-NEXT: v_mov_b32_e32 v1, s063; GFX942-NEXT: global_store_dword v0, v1, s[2:3]64; GFX942-NEXT: s_endpgm65;66; GFX90a-LABEL: ptr1_i8_zext_arg:67; GFX90a: ; %bb.1:68; GFX90a-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x069; GFX90a-NEXT: s_load_dword s10, s[4:5], 0x870; GFX90a-NEXT: s_waitcnt lgkmcnt(0)71; GFX90a-NEXT: s_branch .LBB1_072; GFX90a-NEXT: .p2align 873; GFX90a-NEXT: ; %bb.2:74; GFX90a-NEXT: .LBB1_0:75; GFX90a-NEXT: s_and_b32 s0, s10, 0xff76; GFX90a-NEXT: v_mov_b32_e32 v0, 077; GFX90a-NEXT: v_mov_b32_e32 v1, s078; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]79; GFX90a-NEXT: s_endpgm80;81; GFX1250-LABEL: ptr1_i8_zext_arg:82; GFX1250: ; %bb.0:83; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 184; GFX1250-NEXT: s_and_b32 s0, s4, 0xff85; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)86; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s087; GFX1250-NEXT: global_store_b32 v0, v1, s[2:3]88; GFX1250-NEXT: s_endpgm89 %ext = zext i8 %arg0 to i3290 store i32 %ext, ptr addrspace(1) %out, align 491 ret void92}93 94define amdgpu_kernel void @ptr1_i16_preload_arg(ptr addrspace(1) inreg %out, i16 inreg %arg0) #0 {95; GFX942-LABEL: ptr1_i16_preload_arg:96; GFX942: ; %bb.1:97; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x098; GFX942-NEXT: s_load_dword s4, s[0:1], 0x899; GFX942-NEXT: s_waitcnt lgkmcnt(0)100; GFX942-NEXT: s_branch .LBB2_0101; GFX942-NEXT: .p2align 8102; GFX942-NEXT: ; %bb.2:103; GFX942-NEXT: .LBB2_0:104; GFX942-NEXT: s_and_b32 s0, s4, 0xffff105; GFX942-NEXT: v_mov_b32_e32 v0, 0106; GFX942-NEXT: v_mov_b32_e32 v1, s0107; GFX942-NEXT: global_store_dword v0, v1, s[2:3]108; GFX942-NEXT: s_endpgm109;110; GFX90a-LABEL: ptr1_i16_preload_arg:111; GFX90a: ; %bb.1:112; GFX90a-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0113; GFX90a-NEXT: s_load_dword s10, s[4:5], 0x8114; GFX90a-NEXT: s_waitcnt lgkmcnt(0)115; GFX90a-NEXT: s_branch .LBB2_0116; GFX90a-NEXT: .p2align 8117; GFX90a-NEXT: ; %bb.2:118; GFX90a-NEXT: .LBB2_0:119; GFX90a-NEXT: s_and_b32 s0, s10, 0xffff120; GFX90a-NEXT: v_mov_b32_e32 v0, 0121; GFX90a-NEXT: v_mov_b32_e32 v1, s0122; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]123; GFX90a-NEXT: s_endpgm124;125; GFX1250-LABEL: ptr1_i16_preload_arg:126; GFX1250: ; %bb.0:127; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1128; GFX1250-NEXT: s_and_b32 s0, s4, 0xffff129; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)130; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0131; GFX1250-NEXT: global_store_b32 v0, v1, s[2:3]132; GFX1250-NEXT: s_endpgm133 %ext = zext i16 %arg0 to i32134 store i32 %ext, ptr addrspace(1) %out, align 4135 ret void136}137 138define amdgpu_kernel void @ptr1_i32_preload_arg(ptr addrspace(1) inreg %out, i32 inreg %arg0) #0 {139; GFX942-LABEL: ptr1_i32_preload_arg:140; GFX942: ; %bb.1:141; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0142; GFX942-NEXT: s_load_dword s4, s[0:1], 0x8143; GFX942-NEXT: s_waitcnt lgkmcnt(0)144; GFX942-NEXT: s_branch .LBB3_0145; GFX942-NEXT: .p2align 8146; GFX942-NEXT: ; %bb.2:147; GFX942-NEXT: .LBB3_0:148; GFX942-NEXT: v_mov_b32_e32 v0, 0149; GFX942-NEXT: v_mov_b32_e32 v1, s4150; GFX942-NEXT: global_store_dword v0, v1, s[2:3]151; GFX942-NEXT: s_endpgm152;153; GFX90a-LABEL: ptr1_i32_preload_arg:154; GFX90a: ; %bb.1:155; GFX90a-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0156; GFX90a-NEXT: s_load_dword s10, s[4:5], 0x8157; GFX90a-NEXT: s_waitcnt lgkmcnt(0)158; GFX90a-NEXT: s_branch .LBB3_0159; GFX90a-NEXT: .p2align 8160; GFX90a-NEXT: ; %bb.2:161; GFX90a-NEXT: .LBB3_0:162; GFX90a-NEXT: v_mov_b32_e32 v0, 0163; GFX90a-NEXT: v_mov_b32_e32 v1, s10164; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]165; GFX90a-NEXT: s_endpgm166;167; GFX1250-LABEL: ptr1_i32_preload_arg:168; GFX1250: ; %bb.0:169; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1170; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4171; GFX1250-NEXT: global_store_b32 v0, v1, s[2:3]172; GFX1250-NEXT: s_endpgm173 store i32 %arg0, ptr addrspace(1) %out174 ret void175}176 177 178define amdgpu_kernel void @i32_ptr1_i32_preload_arg(i32 inreg %arg0, ptr addrspace(1) inreg %out, i32 inreg %arg1) #0 {179; GFX942-LABEL: i32_ptr1_i32_preload_arg:180; GFX942: ; %bb.1:181; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0182; GFX942-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8183; GFX942-NEXT: s_load_dword s6, s[0:1], 0x10184; GFX942-NEXT: s_waitcnt lgkmcnt(0)185; GFX942-NEXT: s_branch .LBB4_0186; GFX942-NEXT: .p2align 8187; GFX942-NEXT: ; %bb.2:188; GFX942-NEXT: .LBB4_0:189; GFX942-NEXT: s_add_i32 s0, s2, s6190; GFX942-NEXT: v_mov_b32_e32 v0, 0191; GFX942-NEXT: v_mov_b32_e32 v1, s0192; GFX942-NEXT: global_store_dword v0, v1, s[4:5]193; GFX942-NEXT: s_endpgm194;195; GFX90a-LABEL: i32_ptr1_i32_preload_arg:196; GFX90a: ; %bb.1:197; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0198; GFX90a-NEXT: s_load_dword s12, s[4:5], 0x10199; GFX90a-NEXT: s_waitcnt lgkmcnt(0)200; GFX90a-NEXT: s_branch .LBB4_0201; GFX90a-NEXT: .p2align 8202; GFX90a-NEXT: ; %bb.2:203; GFX90a-NEXT: .LBB4_0:204; GFX90a-NEXT: s_add_i32 s0, s8, s12205; GFX90a-NEXT: v_mov_b32_e32 v0, 0206; GFX90a-NEXT: v_mov_b32_e32 v1, s0207; GFX90a-NEXT: global_store_dword v0, v1, s[10:11]208; GFX90a-NEXT: s_endpgm209;210; GFX1250-LABEL: i32_ptr1_i32_preload_arg:211; GFX1250: ; %bb.0:212; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1213; GFX1250-NEXT: s_add_co_i32 s0, s2, s6214; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)215; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0216; GFX1250-NEXT: global_store_b32 v0, v1, s[4:5]217; GFX1250-NEXT: s_endpgm218 %add = add i32 %arg0, %arg1219 store i32 %add, ptr addrspace(1) %out220 ret void221}222 223define amdgpu_kernel void @ptr1_i16_i16_preload_arg(ptr addrspace(1) inreg %out, i16 inreg %arg0, i16 inreg %arg1) #0 {224; GFX942-LABEL: ptr1_i16_i16_preload_arg:225; GFX942: ; %bb.1:226; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0227; GFX942-NEXT: s_load_dword s4, s[0:1], 0x8228; GFX942-NEXT: s_waitcnt lgkmcnt(0)229; GFX942-NEXT: s_branch .LBB5_0230; GFX942-NEXT: .p2align 8231; GFX942-NEXT: ; %bb.2:232; GFX942-NEXT: .LBB5_0:233; GFX942-NEXT: s_lshr_b32 s0, s4, 16234; GFX942-NEXT: s_and_b32 s1, s4, 0xffff235; GFX942-NEXT: s_add_i32 s0, s1, s0236; GFX942-NEXT: v_mov_b32_e32 v0, 0237; GFX942-NEXT: v_mov_b32_e32 v1, s0238; GFX942-NEXT: global_store_dword v0, v1, s[2:3]239; GFX942-NEXT: s_endpgm240;241; GFX90a-LABEL: ptr1_i16_i16_preload_arg:242; GFX90a: ; %bb.1:243; GFX90a-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0244; GFX90a-NEXT: s_load_dword s10, s[4:5], 0x8245; GFX90a-NEXT: s_waitcnt lgkmcnt(0)246; GFX90a-NEXT: s_branch .LBB5_0247; GFX90a-NEXT: .p2align 8248; GFX90a-NEXT: ; %bb.2:249; GFX90a-NEXT: .LBB5_0:250; GFX90a-NEXT: s_lshr_b32 s0, s10, 16251; GFX90a-NEXT: s_and_b32 s1, s10, 0xffff252; GFX90a-NEXT: s_add_i32 s0, s1, s0253; GFX90a-NEXT: v_mov_b32_e32 v0, 0254; GFX90a-NEXT: v_mov_b32_e32 v1, s0255; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]256; GFX90a-NEXT: s_endpgm257;258; GFX1250-LABEL: ptr1_i16_i16_preload_arg:259; GFX1250: ; %bb.0:260; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1261; GFX1250-NEXT: s_lshr_b32 s0, s4, 16262; GFX1250-NEXT: s_and_b32 s1, s4, 0xffff263; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)264; GFX1250-NEXT: s_add_co_i32 s0, s1, s0265; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0266; GFX1250-NEXT: global_store_b32 v0, v1, s[2:3]267; GFX1250-NEXT: s_endpgm268 %ext = zext i16 %arg0 to i32269 %ext1 = zext i16 %arg1 to i32270 %add = add i32 %ext, %ext1271 store i32 %add, ptr addrspace(1) %out, align 4272 ret void273}274 275define amdgpu_kernel void @ptr1_v2i8_preload_arg(ptr addrspace(1) inreg %out, <2 x i8> inreg %in) #0 {276; GFX942-LABEL: ptr1_v2i8_preload_arg:277; GFX942: ; %bb.1:278; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0279; GFX942-NEXT: s_load_dword s4, s[0:1], 0x8280; GFX942-NEXT: s_waitcnt lgkmcnt(0)281; GFX942-NEXT: s_branch .LBB6_0282; GFX942-NEXT: .p2align 8283; GFX942-NEXT: ; %bb.2:284; GFX942-NEXT: .LBB6_0:285; GFX942-NEXT: v_mov_b32_e32 v0, 0286; GFX942-NEXT: v_mov_b32_e32 v1, s4287; GFX942-NEXT: global_store_short v0, v1, s[2:3]288; GFX942-NEXT: s_endpgm289;290; GFX90a-LABEL: ptr1_v2i8_preload_arg:291; GFX90a: ; %bb.1:292; GFX90a-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0293; GFX90a-NEXT: s_load_dword s10, s[4:5], 0x8294; GFX90a-NEXT: s_waitcnt lgkmcnt(0)295; GFX90a-NEXT: s_branch .LBB6_0296; GFX90a-NEXT: .p2align 8297; GFX90a-NEXT: ; %bb.2:298; GFX90a-NEXT: .LBB6_0:299; GFX90a-NEXT: v_mov_b32_e32 v0, 0300; GFX90a-NEXT: v_mov_b32_e32 v1, s10301; GFX90a-NEXT: global_store_short v0, v1, s[8:9]302; GFX90a-NEXT: s_endpgm303;304; GFX1250-LABEL: ptr1_v2i8_preload_arg:305; GFX1250: ; %bb.0:306; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1307; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4308; GFX1250-NEXT: global_store_b16 v0, v1, s[2:3]309; GFX1250-NEXT: s_endpgm310 store <2 x i8> %in, ptr addrspace(1) %out311 ret void312}313 314 315define amdgpu_kernel void @byref_preload_arg(ptr addrspace(1) inreg %out, ptr addrspace(4) byref(i32) align(256) %in.byref, i32 %after.offset) #0 {316; GFX942-LABEL: byref_preload_arg:317; GFX942: ; %bb.1:318; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0319; GFX942-NEXT: s_waitcnt lgkmcnt(0)320; GFX942-NEXT: s_branch .LBB7_0321; GFX942-NEXT: .p2align 8322; GFX942-NEXT: ; %bb.2:323; GFX942-NEXT: .LBB7_0:324; GFX942-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x100325; GFX942-NEXT: v_mov_b32_e32 v0, 0326; GFX942-NEXT: s_waitcnt lgkmcnt(0)327; GFX942-NEXT: v_mov_b32_e32 v1, s4328; GFX942-NEXT: v_mov_b32_e32 v2, s5329; GFX942-NEXT: global_store_dword v0, v1, s[2:3] sc0 sc1330; GFX942-NEXT: s_waitcnt vmcnt(0)331; GFX942-NEXT: global_store_dword v0, v2, s[2:3] sc0 sc1332; GFX942-NEXT: s_waitcnt vmcnt(0)333; GFX942-NEXT: s_endpgm334;335; GFX90a-LABEL: byref_preload_arg:336; GFX90a: ; %bb.1:337; GFX90a-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0338; GFX90a-NEXT: s_waitcnt lgkmcnt(0)339; GFX90a-NEXT: s_branch .LBB7_0340; GFX90a-NEXT: .p2align 8341; GFX90a-NEXT: ; %bb.2:342; GFX90a-NEXT: .LBB7_0:343; GFX90a-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x100344; GFX90a-NEXT: v_mov_b32_e32 v0, 0345; GFX90a-NEXT: s_waitcnt lgkmcnt(0)346; GFX90a-NEXT: v_mov_b32_e32 v1, s0347; GFX90a-NEXT: v_mov_b32_e32 v2, s1348; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]349; GFX90a-NEXT: s_waitcnt vmcnt(0)350; GFX90a-NEXT: global_store_dword v0, v2, s[8:9]351; GFX90a-NEXT: s_waitcnt vmcnt(0)352; GFX90a-NEXT: s_endpgm353;354; GFX1250-LABEL: byref_preload_arg:355; GFX1250: ; %bb.0:356; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1357; GFX1250-NEXT: s_load_b64 s[4:5], s[0:1], 0x100358; GFX1250-NEXT: s_wait_kmcnt 0x0359; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4360; GFX1250-NEXT: v_mov_b32_e32 v2, s5361; GFX1250-NEXT: global_store_b32 v0, v1, s[2:3] scope:SCOPE_SYS362; GFX1250-NEXT: s_wait_storecnt 0x0363; GFX1250-NEXT: s_wait_xcnt 0x0364; GFX1250-NEXT: global_store_b32 v0, v2, s[2:3] scope:SCOPE_SYS365; GFX1250-NEXT: s_wait_storecnt 0x0366; GFX1250-NEXT: s_endpgm367 %in = load i32, ptr addrspace(4) %in.byref368 store volatile i32 %in, ptr addrspace(1) %out, align 4369 store volatile i32 %after.offset, ptr addrspace(1) %out, align 4370 ret void371}372 373; The second argument is not expected to be preloaded with the current behavior.374 375define amdgpu_kernel void @byref_staggered_preload_arg(ptr addrspace(1) inreg %out, ptr addrspace(4) byref(i32) align(256) %in.byref, i32 inreg %after.offset) #0 {376; GFX942-LABEL: byref_staggered_preload_arg:377; GFX942: ; %bb.1:378; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0379; GFX942-NEXT: s_waitcnt lgkmcnt(0)380; GFX942-NEXT: s_branch .LBB8_0381; GFX942-NEXT: .p2align 8382; GFX942-NEXT: ; %bb.2:383; GFX942-NEXT: .LBB8_0:384; GFX942-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x100385; GFX942-NEXT: v_mov_b32_e32 v0, 0386; GFX942-NEXT: s_waitcnt lgkmcnt(0)387; GFX942-NEXT: v_mov_b32_e32 v1, s4388; GFX942-NEXT: v_mov_b32_e32 v2, s5389; GFX942-NEXT: global_store_dword v0, v1, s[2:3] sc0 sc1390; GFX942-NEXT: s_waitcnt vmcnt(0)391; GFX942-NEXT: global_store_dword v0, v2, s[2:3] sc0 sc1392; GFX942-NEXT: s_waitcnt vmcnt(0)393; GFX942-NEXT: s_endpgm394;395; GFX90a-LABEL: byref_staggered_preload_arg:396; GFX90a: ; %bb.1:397; GFX90a-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0398; GFX90a-NEXT: s_waitcnt lgkmcnt(0)399; GFX90a-NEXT: s_branch .LBB8_0400; GFX90a-NEXT: .p2align 8401; GFX90a-NEXT: ; %bb.2:402; GFX90a-NEXT: .LBB8_0:403; GFX90a-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x100404; GFX90a-NEXT: v_mov_b32_e32 v0, 0405; GFX90a-NEXT: s_waitcnt lgkmcnt(0)406; GFX90a-NEXT: v_mov_b32_e32 v1, s0407; GFX90a-NEXT: v_mov_b32_e32 v2, s1408; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]409; GFX90a-NEXT: s_waitcnt vmcnt(0)410; GFX90a-NEXT: global_store_dword v0, v2, s[8:9]411; GFX90a-NEXT: s_waitcnt vmcnt(0)412; GFX90a-NEXT: s_endpgm413;414; GFX1250-LABEL: byref_staggered_preload_arg:415; GFX1250: ; %bb.0:416; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1417; GFX1250-NEXT: s_load_b64 s[4:5], s[0:1], 0x100418; GFX1250-NEXT: s_wait_kmcnt 0x0419; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4420; GFX1250-NEXT: v_mov_b32_e32 v2, s5421; GFX1250-NEXT: global_store_b32 v0, v1, s[2:3] scope:SCOPE_SYS422; GFX1250-NEXT: s_wait_storecnt 0x0423; GFX1250-NEXT: s_wait_xcnt 0x0424; GFX1250-NEXT: global_store_b32 v0, v2, s[2:3] scope:SCOPE_SYS425; GFX1250-NEXT: s_wait_storecnt 0x0426; GFX1250-NEXT: s_endpgm427 %in = load i32, ptr addrspace(4) %in.byref428 store volatile i32 %in, ptr addrspace(1) %out, align 4429 store volatile i32 %after.offset, ptr addrspace(1) %out, align 4430 ret void431}432 433 434define amdgpu_kernel void @v8i32_arg(ptr addrspace(1) nocapture inreg %out, <8 x i32> inreg %in) #0 {435; GFX942-LABEL: v8i32_arg:436; GFX942: ; %bb.1:437; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0438; GFX942-NEXT: s_waitcnt lgkmcnt(0)439; GFX942-NEXT: s_branch .LBB9_0440; GFX942-NEXT: .p2align 8441; GFX942-NEXT: ; %bb.2:442; GFX942-NEXT: .LBB9_0:443; GFX942-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x20444; GFX942-NEXT: v_mov_b32_e32 v4, 0445; GFX942-NEXT: s_waitcnt lgkmcnt(0)446; GFX942-NEXT: v_mov_b32_e32 v0, s8447; GFX942-NEXT: v_mov_b32_e32 v1, s9448; GFX942-NEXT: v_mov_b32_e32 v2, s10449; GFX942-NEXT: v_mov_b32_e32 v3, s11450; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3] offset:16451; GFX942-NEXT: s_nop 1452; GFX942-NEXT: v_mov_b32_e32 v0, s4453; GFX942-NEXT: v_mov_b32_e32 v1, s5454; GFX942-NEXT: v_mov_b32_e32 v2, s6455; GFX942-NEXT: v_mov_b32_e32 v3, s7456; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3]457; GFX942-NEXT: s_endpgm458;459; GFX90a-LABEL: v8i32_arg:460; GFX90a: ; %bb.1:461; GFX90a-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0462; GFX90a-NEXT: s_waitcnt lgkmcnt(0)463; GFX90a-NEXT: s_branch .LBB9_0464; GFX90a-NEXT: .p2align 8465; GFX90a-NEXT: ; %bb.2:466; GFX90a-NEXT: .LBB9_0:467; GFX90a-NEXT: s_load_dwordx8 s[12:19], s[4:5], 0x20468; GFX90a-NEXT: v_mov_b32_e32 v4, 0469; GFX90a-NEXT: s_waitcnt lgkmcnt(0)470; GFX90a-NEXT: v_mov_b32_e32 v0, s16471; GFX90a-NEXT: v_mov_b32_e32 v1, s17472; GFX90a-NEXT: v_mov_b32_e32 v2, s18473; GFX90a-NEXT: v_mov_b32_e32 v3, s19474; GFX90a-NEXT: global_store_dwordx4 v4, v[0:3], s[8:9] offset:16475; GFX90a-NEXT: s_nop 0476; GFX90a-NEXT: v_mov_b32_e32 v0, s12477; GFX90a-NEXT: v_mov_b32_e32 v1, s13478; GFX90a-NEXT: v_mov_b32_e32 v2, s14479; GFX90a-NEXT: v_mov_b32_e32 v3, s15480; GFX90a-NEXT: global_store_dwordx4 v4, v[0:3], s[8:9]481; GFX90a-NEXT: s_endpgm482;483; GFX1250-LABEL: v8i32_arg:484; GFX1250: ; %bb.0:485; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1486; GFX1250-NEXT: v_dual_mov_b32 v8, 0 :: v_dual_mov_b32 v0, s14487; GFX1250-NEXT: v_dual_mov_b32 v1, s15 :: v_dual_mov_b32 v2, s16488; GFX1250-NEXT: v_dual_mov_b32 v3, s17 :: v_dual_mov_b32 v4, s10489; GFX1250-NEXT: v_dual_mov_b32 v5, s11 :: v_dual_mov_b32 v6, s12490; GFX1250-NEXT: v_mov_b32_e32 v7, s13491; GFX1250-NEXT: s_clause 0x1492; GFX1250-NEXT: global_store_b128 v8, v[0:3], s[2:3] offset:16493; GFX1250-NEXT: global_store_b128 v8, v[4:7], s[2:3]494; GFX1250-NEXT: s_endpgm495 store <8 x i32> %in, ptr addrspace(1) %out, align 4496 ret void497}498 499define amdgpu_kernel void @v3i16_preload_arg(ptr addrspace(1) nocapture inreg %out, <3 x i16> inreg %in) #0 {500; GFX942-LABEL: v3i16_preload_arg:501; GFX942: ; %bb.1:502; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0503; GFX942-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8504; GFX942-NEXT: s_waitcnt lgkmcnt(0)505; GFX942-NEXT: s_branch .LBB10_0506; GFX942-NEXT: .p2align 8507; GFX942-NEXT: ; %bb.2:508; GFX942-NEXT: .LBB10_0:509; GFX942-NEXT: v_mov_b32_e32 v0, 0510; GFX942-NEXT: v_mov_b32_e32 v1, s5511; GFX942-NEXT: global_store_short v0, v1, s[2:3] offset:4512; GFX942-NEXT: v_mov_b32_e32 v1, s4513; GFX942-NEXT: global_store_dword v0, v1, s[2:3]514; GFX942-NEXT: s_endpgm515;516; GFX90a-LABEL: v3i16_preload_arg:517; GFX90a: ; %bb.1:518; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0519; GFX90a-NEXT: s_waitcnt lgkmcnt(0)520; GFX90a-NEXT: s_branch .LBB10_0521; GFX90a-NEXT: .p2align 8522; GFX90a-NEXT: ; %bb.2:523; GFX90a-NEXT: .LBB10_0:524; GFX90a-NEXT: v_mov_b32_e32 v0, 0525; GFX90a-NEXT: v_mov_b32_e32 v1, s11526; GFX90a-NEXT: global_store_short v0, v1, s[8:9] offset:4527; GFX90a-NEXT: v_mov_b32_e32 v1, s10528; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]529; GFX90a-NEXT: s_endpgm530;531; GFX1250-LABEL: v3i16_preload_arg:532; GFX1250: ; %bb.0:533; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1534; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s5535; GFX1250-NEXT: v_mov_b32_e32 v2, s4536; GFX1250-NEXT: s_clause 0x1537; GFX1250-NEXT: global_store_b16 v0, v1, s[2:3] offset:4538; GFX1250-NEXT: global_store_b32 v0, v2, s[2:3]539; GFX1250-NEXT: s_endpgm540 store <3 x i16> %in, ptr addrspace(1) %out, align 4541 ret void542}543 544define amdgpu_kernel void @v3i32_preload_arg(ptr addrspace(1) nocapture inreg %out, <3 x i32> inreg %in) #0 {545; GFX942-LABEL: v3i32_preload_arg:546; GFX942: ; %bb.1:547; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0548; GFX942-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8549; GFX942-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x18550; GFX942-NEXT: s_waitcnt lgkmcnt(0)551; GFX942-NEXT: s_branch .LBB11_0552; GFX942-NEXT: .p2align 8553; GFX942-NEXT: ; %bb.2:554; GFX942-NEXT: .LBB11_0:555; GFX942-NEXT: v_mov_b32_e32 v0, s6556; GFX942-NEXT: v_mov_b32_e32 v1, s7557; GFX942-NEXT: v_mov_b32_e32 v2, s8558; GFX942-NEXT: v_mov_b32_e32 v3, 0559; GFX942-NEXT: global_store_dwordx3 v3, v[0:2], s[2:3]560; GFX942-NEXT: s_endpgm561;562; GFX90a-LABEL: v3i32_preload_arg:563; GFX90a: ; %bb.1:564; GFX90a-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0565; GFX90a-NEXT: s_waitcnt lgkmcnt(0)566; GFX90a-NEXT: s_branch .LBB11_0567; GFX90a-NEXT: .p2align 8568; GFX90a-NEXT: ; %bb.2:569; GFX90a-NEXT: .LBB11_0:570; GFX90a-NEXT: v_mov_b32_e32 v0, s12571; GFX90a-NEXT: v_mov_b32_e32 v1, s13572; GFX90a-NEXT: v_mov_b32_e32 v2, s14573; GFX90a-NEXT: v_mov_b32_e32 v3, 0574; GFX90a-NEXT: global_store_dwordx3 v3, v[0:2], s[8:9]575; GFX90a-NEXT: s_endpgm576;577; GFX1250-LABEL: v3i32_preload_arg:578; GFX1250: ; %bb.0:579; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1580; GFX1250-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s7581; GFX1250-NEXT: v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v3, 0582; GFX1250-NEXT: global_store_b96 v3, v[0:2], s[2:3]583; GFX1250-NEXT: s_endpgm584 store <3 x i32> %in, ptr addrspace(1) %out, align 4585 ret void586}587 588define amdgpu_kernel void @v3f32_preload_arg(ptr addrspace(1) nocapture inreg %out, <3 x float> inreg %in) #0 {589; GFX942-LABEL: v3f32_preload_arg:590; GFX942: ; %bb.1:591; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0592; GFX942-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x8593; GFX942-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x18594; GFX942-NEXT: s_waitcnt lgkmcnt(0)595; GFX942-NEXT: s_branch .LBB12_0596; GFX942-NEXT: .p2align 8597; GFX942-NEXT: ; %bb.2:598; GFX942-NEXT: .LBB12_0:599; GFX942-NEXT: v_mov_b32_e32 v3, 0600; GFX942-NEXT: v_mov_b32_e32 v0, s6601; GFX942-NEXT: v_mov_b32_e32 v1, s7602; GFX942-NEXT: v_mov_b32_e32 v2, s8603; GFX942-NEXT: global_store_dwordx3 v3, v[0:2], s[2:3]604; GFX942-NEXT: s_endpgm605;606; GFX90a-LABEL: v3f32_preload_arg:607; GFX90a: ; %bb.1:608; GFX90a-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x0609; GFX90a-NEXT: s_waitcnt lgkmcnt(0)610; GFX90a-NEXT: s_branch .LBB12_0611; GFX90a-NEXT: .p2align 8612; GFX90a-NEXT: ; %bb.2:613; GFX90a-NEXT: .LBB12_0:614; GFX90a-NEXT: v_mov_b32_e32 v3, 0615; GFX90a-NEXT: v_mov_b32_e32 v0, s12616; GFX90a-NEXT: v_mov_b32_e32 v1, s13617; GFX90a-NEXT: v_mov_b32_e32 v2, s14618; GFX90a-NEXT: global_store_dwordx3 v3, v[0:2], s[8:9]619; GFX90a-NEXT: s_endpgm620;621; GFX1250-LABEL: v3f32_preload_arg:622; GFX1250: ; %bb.0:623; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1624; GFX1250-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v0, s6625; GFX1250-NEXT: v_dual_mov_b32 v1, s7 :: v_dual_mov_b32 v2, s8626; GFX1250-NEXT: global_store_b96 v3, v[0:2], s[2:3]627; GFX1250-NEXT: s_endpgm628 store <3 x float> %in, ptr addrspace(1) %out, align 4629 ret void630}631 632define amdgpu_kernel void @v5i8_preload_arg(ptr addrspace(1) nocapture inreg %out, <5 x i8> inreg %in) #0 {633; GFX942-LABEL: v5i8_preload_arg:634; GFX942: ; %bb.1:635; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0636; GFX942-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8637; GFX942-NEXT: s_waitcnt lgkmcnt(0)638; GFX942-NEXT: s_branch .LBB13_0639; GFX942-NEXT: .p2align 8640; GFX942-NEXT: ; %bb.2:641; GFX942-NEXT: .LBB13_0:642; GFX942-NEXT: s_lshr_b32 s1, s4, 24643; GFX942-NEXT: s_and_b32 s0, s4, 0xffff644; GFX942-NEXT: s_lshl_b32 s1, s1, 8645; GFX942-NEXT: s_bfe_u32 s4, s4, 0x80010646; GFX942-NEXT: s_or_b32 s1, s4, s1647; GFX942-NEXT: s_lshl_b32 s1, s1, 16648; GFX942-NEXT: s_or_b32 s0, s0, s1649; GFX942-NEXT: v_mov_b32_e32 v0, 0650; GFX942-NEXT: v_mov_b32_e32 v1, s5651; GFX942-NEXT: global_store_byte v0, v1, s[2:3] offset:4652; GFX942-NEXT: v_mov_b32_e32 v1, s0653; GFX942-NEXT: global_store_dword v0, v1, s[2:3]654; GFX942-NEXT: s_endpgm655;656; GFX90a-LABEL: v5i8_preload_arg:657; GFX90a: ; %bb.1:658; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0659; GFX90a-NEXT: s_waitcnt lgkmcnt(0)660; GFX90a-NEXT: s_branch .LBB13_0661; GFX90a-NEXT: .p2align 8662; GFX90a-NEXT: ; %bb.2:663; GFX90a-NEXT: .LBB13_0:664; GFX90a-NEXT: s_lshr_b32 s1, s10, 24665; GFX90a-NEXT: s_lshl_b32 s1, s1, 8666; GFX90a-NEXT: s_bfe_u32 s2, s10, 0x80010667; GFX90a-NEXT: s_or_b32 s1, s2, s1668; GFX90a-NEXT: s_and_b32 s0, s10, 0xffff669; GFX90a-NEXT: s_lshl_b32 s1, s1, 16670; GFX90a-NEXT: s_or_b32 s0, s0, s1671; GFX90a-NEXT: v_mov_b32_e32 v0, 0672; GFX90a-NEXT: v_mov_b32_e32 v1, s11673; GFX90a-NEXT: global_store_byte v0, v1, s[8:9] offset:4674; GFX90a-NEXT: v_mov_b32_e32 v1, s0675; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]676; GFX90a-NEXT: s_endpgm677;678; GFX1250-LABEL: v5i8_preload_arg:679; GFX1250: ; %bb.0:680; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1681; GFX1250-NEXT: s_pack_lh_b32_b16 s0, 0, s4682; GFX1250-NEXT: s_and_b32 s1, s4, 0xffff683; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s5684; GFX1250-NEXT: s_or_b32 s0, s1, s0685; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)686; GFX1250-NEXT: v_mov_b32_e32 v2, s0687; GFX1250-NEXT: s_clause 0x1688; GFX1250-NEXT: global_store_b8 v0, v1, s[2:3] offset:4689; GFX1250-NEXT: global_store_b32 v0, v2, s[2:3]690; GFX1250-NEXT: s_endpgm691 store <5 x i8> %in, ptr addrspace(1) %out, align 4692 ret void693}694 695define amdgpu_kernel void @v5f64_arg(ptr addrspace(1) nocapture inreg %out, <5 x double> inreg %in) #0 {696; GFX942-LABEL: v5f64_arg:697; GFX942: ; %bb.1:698; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0699; GFX942-NEXT: s_waitcnt lgkmcnt(0)700; GFX942-NEXT: s_branch .LBB14_0701; GFX942-NEXT: .p2align 8702; GFX942-NEXT: ; %bb.2:703; GFX942-NEXT: .LBB14_0:704; GFX942-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0x60705; GFX942-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x40706; GFX942-NEXT: v_mov_b32_e32 v4, 0707; GFX942-NEXT: s_waitcnt lgkmcnt(0)708; GFX942-NEXT: v_mov_b64_e32 v[2:3], s[12:13]709; GFX942-NEXT: v_mov_b32_e32 v0, s8710; GFX942-NEXT: global_store_dwordx2 v4, v[2:3], s[2:3] offset:32711; GFX942-NEXT: v_mov_b32_e32 v1, s9712; GFX942-NEXT: v_mov_b32_e32 v2, s10713; GFX942-NEXT: v_mov_b32_e32 v3, s11714; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3] offset:16715; GFX942-NEXT: s_nop 1716; GFX942-NEXT: v_mov_b32_e32 v0, s4717; GFX942-NEXT: v_mov_b32_e32 v1, s5718; GFX942-NEXT: v_mov_b32_e32 v2, s6719; GFX942-NEXT: v_mov_b32_e32 v3, s7720; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3]721; GFX942-NEXT: s_endpgm722;723; GFX90a-LABEL: v5f64_arg:724; GFX90a: ; %bb.1:725; GFX90a-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0726; GFX90a-NEXT: s_waitcnt lgkmcnt(0)727; GFX90a-NEXT: s_branch .LBB14_0728; GFX90a-NEXT: .p2align 8729; GFX90a-NEXT: ; %bb.2:730; GFX90a-NEXT: .LBB14_0:731; GFX90a-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x60732; GFX90a-NEXT: s_load_dwordx8 s[12:19], s[4:5], 0x40733; GFX90a-NEXT: v_mov_b32_e32 v4, 0734; GFX90a-NEXT: s_waitcnt lgkmcnt(0)735; GFX90a-NEXT: v_pk_mov_b32 v[2:3], s[0:1], s[0:1] op_sel:[0,1]736; GFX90a-NEXT: v_mov_b32_e32 v0, s16737; GFX90a-NEXT: global_store_dwordx2 v4, v[2:3], s[8:9] offset:32738; GFX90a-NEXT: v_mov_b32_e32 v1, s17739; GFX90a-NEXT: v_mov_b32_e32 v2, s18740; GFX90a-NEXT: v_mov_b32_e32 v3, s19741; GFX90a-NEXT: global_store_dwordx4 v4, v[0:3], s[8:9] offset:16742; GFX90a-NEXT: s_nop 0743; GFX90a-NEXT: v_mov_b32_e32 v0, s12744; GFX90a-NEXT: v_mov_b32_e32 v1, s13745; GFX90a-NEXT: v_mov_b32_e32 v2, s14746; GFX90a-NEXT: v_mov_b32_e32 v3, s15747; GFX90a-NEXT: global_store_dwordx4 v4, v[0:3], s[8:9]748; GFX90a-NEXT: s_endpgm749;750; GFX1250-LABEL: v5f64_arg:751; GFX1250: ; %bb.0:752; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1753; GFX1250-NEXT: s_clause 0x1754; GFX1250-NEXT: s_load_b64 s[12:13], s[0:1], 0x60755; GFX1250-NEXT: s_load_b256 s[4:11], s[0:1], 0x40756; GFX1250-NEXT: v_mov_b32_e32 v10, 0757; GFX1250-NEXT: s_wait_kmcnt 0x0758; GFX1250-NEXT: v_mov_b64_e32 v[8:9], s[12:13]759; GFX1250-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v1, s9760; GFX1250-NEXT: v_dual_mov_b32 v2, s10 :: v_dual_mov_b32 v3, s11761; GFX1250-NEXT: v_dual_mov_b32 v4, s4 :: v_dual_mov_b32 v5, s5762; GFX1250-NEXT: v_dual_mov_b32 v6, s6 :: v_dual_mov_b32 v7, s7763; GFX1250-NEXT: s_clause 0x2764; GFX1250-NEXT: global_store_b64 v10, v[8:9], s[2:3] offset:32765; GFX1250-NEXT: global_store_b128 v10, v[0:3], s[2:3] offset:16766; GFX1250-NEXT: global_store_b128 v10, v[4:7], s[2:3]767; GFX1250-NEXT: s_endpgm768 store <5 x double> %in, ptr addrspace(1) %out, align 8769 ret void770}771 772define amdgpu_kernel void @v8i8_preload_arg(ptr addrspace(1) inreg %out, <8 x i8> inreg %in) #0 {773; GFX942-LABEL: v8i8_preload_arg:774; GFX942: ; %bb.1:775; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0776; GFX942-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8777; GFX942-NEXT: s_waitcnt lgkmcnt(0)778; GFX942-NEXT: s_branch .LBB15_0779; GFX942-NEXT: .p2align 8780; GFX942-NEXT: ; %bb.2:781; GFX942-NEXT: .LBB15_0:782; GFX942-NEXT: s_lshr_b32 s1, s5, 24783; GFX942-NEXT: s_and_b32 s0, s5, 0xffff784; GFX942-NEXT: s_lshl_b32 s1, s1, 8785; GFX942-NEXT: s_bfe_u32 s5, s5, 0x80010786; GFX942-NEXT: s_or_b32 s1, s5, s1787; GFX942-NEXT: s_lshl_b32 s1, s1, 16788; GFX942-NEXT: s_lshr_b32 s5, s4, 24789; GFX942-NEXT: s_or_b32 s0, s0, s1790; GFX942-NEXT: s_and_b32 s1, s4, 0xffff791; GFX942-NEXT: s_lshl_b32 s5, s5, 8792; GFX942-NEXT: s_bfe_u32 s4, s4, 0x80010793; GFX942-NEXT: s_or_b32 s4, s4, s5794; GFX942-NEXT: s_lshl_b32 s4, s4, 16795; GFX942-NEXT: s_or_b32 s1, s1, s4796; GFX942-NEXT: v_mov_b32_e32 v0, s1797; GFX942-NEXT: v_mov_b32_e32 v1, s0798; GFX942-NEXT: v_mov_b32_e32 v2, 0799; GFX942-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]800; GFX942-NEXT: s_endpgm801;802; GFX90a-LABEL: v8i8_preload_arg:803; GFX90a: ; %bb.1:804; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0805; GFX90a-NEXT: s_waitcnt lgkmcnt(0)806; GFX90a-NEXT: s_branch .LBB15_0807; GFX90a-NEXT: .p2align 8808; GFX90a-NEXT: ; %bb.2:809; GFX90a-NEXT: .LBB15_0:810; GFX90a-NEXT: s_lshr_b32 s1, s11, 24811; GFX90a-NEXT: s_lshl_b32 s1, s1, 8812; GFX90a-NEXT: s_bfe_u32 s2, s11, 0x80010813; GFX90a-NEXT: s_or_b32 s1, s2, s1814; GFX90a-NEXT: s_lshr_b32 s2, s10, 24815; GFX90a-NEXT: s_lshl_b32 s2, s2, 8816; GFX90a-NEXT: s_bfe_u32 s3, s10, 0x80010817; GFX90a-NEXT: s_and_b32 s0, s11, 0xffff818; GFX90a-NEXT: s_lshl_b32 s1, s1, 16819; GFX90a-NEXT: s_or_b32 s2, s3, s2820; GFX90a-NEXT: s_or_b32 s0, s0, s1821; GFX90a-NEXT: s_and_b32 s1, s10, 0xffff822; GFX90a-NEXT: s_lshl_b32 s2, s2, 16823; GFX90a-NEXT: s_or_b32 s1, s1, s2824; GFX90a-NEXT: v_mov_b32_e32 v0, s1825; GFX90a-NEXT: v_mov_b32_e32 v1, s0826; GFX90a-NEXT: v_mov_b32_e32 v2, 0827; GFX90a-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9]828; GFX90a-NEXT: s_endpgm829;830; GFX1250-LABEL: v8i8_preload_arg:831; GFX1250: ; %bb.0:832; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1833; GFX1250-NEXT: s_pack_lh_b32_b16 s0, 0, s5834; GFX1250-NEXT: s_pack_lh_b32_b16 s1, 0, s4835; GFX1250-NEXT: s_and_b32 s4, s4, 0xffff836; GFX1250-NEXT: s_and_b32 s5, s5, 0xffff837; GFX1250-NEXT: s_or_b32 s1, s4, s1838; GFX1250-NEXT: s_or_b32 s0, s5, s0839; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)840; GFX1250-NEXT: v_dual_mov_b32 v0, s1 :: v_dual_mov_b32 v1, s0841; GFX1250-NEXT: v_mov_b32_e32 v2, 0842; GFX1250-NEXT: global_store_b64 v2, v[0:1], s[2:3]843; GFX1250-NEXT: s_endpgm844 store <8 x i8> %in, ptr addrspace(1) %out845 ret void846}847 848define amdgpu_kernel void @i64_kernel_preload_arg(ptr addrspace(1) inreg %out, i64 inreg %a) #0 {849; GFX942-LABEL: i64_kernel_preload_arg:850; GFX942: ; %bb.1:851; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0852; GFX942-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8853; GFX942-NEXT: s_waitcnt lgkmcnt(0)854; GFX942-NEXT: s_branch .LBB16_0855; GFX942-NEXT: .p2align 8856; GFX942-NEXT: ; %bb.2:857; GFX942-NEXT: .LBB16_0:858; GFX942-NEXT: v_mov_b32_e32 v0, 0859; GFX942-NEXT: v_mov_b64_e32 v[2:3], s[4:5]860; GFX942-NEXT: global_store_dwordx2 v0, v[2:3], s[2:3]861; GFX942-NEXT: s_endpgm862;863; GFX90a-LABEL: i64_kernel_preload_arg:864; GFX90a: ; %bb.1:865; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0866; GFX90a-NEXT: s_waitcnt lgkmcnt(0)867; GFX90a-NEXT: s_branch .LBB16_0868; GFX90a-NEXT: .p2align 8869; GFX90a-NEXT: ; %bb.2:870; GFX90a-NEXT: .LBB16_0:871; GFX90a-NEXT: v_mov_b32_e32 v0, 0872; GFX90a-NEXT: v_pk_mov_b32 v[2:3], s[10:11], s[10:11] op_sel:[0,1]873; GFX90a-NEXT: global_store_dwordx2 v0, v[2:3], s[8:9]874; GFX90a-NEXT: s_endpgm875;876; GFX1250-LABEL: i64_kernel_preload_arg:877; GFX1250: ; %bb.0:878; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1879; GFX1250-NEXT: v_mov_b64_e32 v[0:1], s[4:5]880; GFX1250-NEXT: v_mov_b32_e32 v2, 0881; GFX1250-NEXT: global_store_b64 v2, v[0:1], s[2:3]882; GFX1250-NEXT: s_endpgm883 store i64 %a, ptr addrspace(1) %out, align 8884 ret void885}886 887define amdgpu_kernel void @f64_kernel_preload_arg(ptr addrspace(1) inreg %out, double inreg %in) #0 {888; GFX942-LABEL: f64_kernel_preload_arg:889; GFX942: ; %bb.1:890; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0891; GFX942-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x8892; GFX942-NEXT: s_waitcnt lgkmcnt(0)893; GFX942-NEXT: s_branch .LBB17_0894; GFX942-NEXT: .p2align 8895; GFX942-NEXT: ; %bb.2:896; GFX942-NEXT: .LBB17_0:897; GFX942-NEXT: v_mov_b32_e32 v0, 0898; GFX942-NEXT: v_mov_b64_e32 v[2:3], s[4:5]899; GFX942-NEXT: global_store_dwordx2 v0, v[2:3], s[2:3]900; GFX942-NEXT: s_endpgm901;902; GFX90a-LABEL: f64_kernel_preload_arg:903; GFX90a: ; %bb.1:904; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x0905; GFX90a-NEXT: s_waitcnt lgkmcnt(0)906; GFX90a-NEXT: s_branch .LBB17_0907; GFX90a-NEXT: .p2align 8908; GFX90a-NEXT: ; %bb.2:909; GFX90a-NEXT: .LBB17_0:910; GFX90a-NEXT: v_mov_b32_e32 v0, 0911; GFX90a-NEXT: v_pk_mov_b32 v[2:3], s[10:11], s[10:11] op_sel:[0,1]912; GFX90a-NEXT: global_store_dwordx2 v0, v[2:3], s[8:9]913; GFX90a-NEXT: s_endpgm914;915; GFX1250-LABEL: f64_kernel_preload_arg:916; GFX1250: ; %bb.0:917; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1918; GFX1250-NEXT: v_mov_b64_e32 v[0:1], s[4:5]919; GFX1250-NEXT: v_mov_b32_e32 v2, 0920; GFX1250-NEXT: global_store_b64 v2, v[0:1], s[2:3]921; GFX1250-NEXT: s_endpgm922 store double %in, ptr addrspace(1) %out923 ret void924}925 926define amdgpu_kernel void @half_kernel_preload_arg(ptr addrspace(1) inreg %out, half inreg %in) #0 {927; GFX942-LABEL: half_kernel_preload_arg:928; GFX942: ; %bb.1:929; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0930; GFX942-NEXT: s_load_dword s4, s[0:1], 0x8931; GFX942-NEXT: s_waitcnt lgkmcnt(0)932; GFX942-NEXT: s_branch .LBB18_0933; GFX942-NEXT: .p2align 8934; GFX942-NEXT: ; %bb.2:935; GFX942-NEXT: .LBB18_0:936; GFX942-NEXT: v_mov_b32_e32 v0, 0937; GFX942-NEXT: v_mov_b32_e32 v1, s4938; GFX942-NEXT: global_store_short v0, v1, s[2:3]939; GFX942-NEXT: s_endpgm940;941; GFX90a-LABEL: half_kernel_preload_arg:942; GFX90a: ; %bb.1:943; GFX90a-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0944; GFX90a-NEXT: s_load_dword s10, s[4:5], 0x8945; GFX90a-NEXT: s_waitcnt lgkmcnt(0)946; GFX90a-NEXT: s_branch .LBB18_0947; GFX90a-NEXT: .p2align 8948; GFX90a-NEXT: ; %bb.2:949; GFX90a-NEXT: .LBB18_0:950; GFX90a-NEXT: v_mov_b32_e32 v0, 0951; GFX90a-NEXT: v_mov_b32_e32 v1, s10952; GFX90a-NEXT: global_store_short v0, v1, s[8:9]953; GFX90a-NEXT: s_endpgm954;955; GFX1250-LABEL: half_kernel_preload_arg:956; GFX1250: ; %bb.0:957; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1958; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4959; GFX1250-NEXT: global_store_b16 v0, v1, s[2:3]960; GFX1250-NEXT: s_endpgm961 store half %in, ptr addrspace(1) %out962 ret void963}964 965define amdgpu_kernel void @bfloat_kernel_preload_arg(ptr addrspace(1) inreg %out, bfloat inreg %in) #0 {966; GFX942-LABEL: bfloat_kernel_preload_arg:967; GFX942: ; %bb.1:968; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x0969; GFX942-NEXT: s_load_dword s4, s[0:1], 0x8970; GFX942-NEXT: s_waitcnt lgkmcnt(0)971; GFX942-NEXT: s_branch .LBB19_0972; GFX942-NEXT: .p2align 8973; GFX942-NEXT: ; %bb.2:974; GFX942-NEXT: .LBB19_0:975; GFX942-NEXT: v_mov_b32_e32 v0, 0976; GFX942-NEXT: v_mov_b32_e32 v1, s4977; GFX942-NEXT: global_store_short v0, v1, s[2:3]978; GFX942-NEXT: s_endpgm979;980; GFX90a-LABEL: bfloat_kernel_preload_arg:981; GFX90a: ; %bb.1:982; GFX90a-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0983; GFX90a-NEXT: s_load_dword s10, s[4:5], 0x8984; GFX90a-NEXT: s_waitcnt lgkmcnt(0)985; GFX90a-NEXT: s_branch .LBB19_0986; GFX90a-NEXT: .p2align 8987; GFX90a-NEXT: ; %bb.2:988; GFX90a-NEXT: .LBB19_0:989; GFX90a-NEXT: v_mov_b32_e32 v0, 0990; GFX90a-NEXT: v_mov_b32_e32 v1, s10991; GFX90a-NEXT: global_store_short v0, v1, s[8:9]992; GFX90a-NEXT: s_endpgm993;994; GFX1250-LABEL: bfloat_kernel_preload_arg:995; GFX1250: ; %bb.0:996; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 1997; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s4998; GFX1250-NEXT: global_store_b16 v0, v1, s[2:3]999; GFX1250-NEXT: s_endpgm1000 store bfloat %in, ptr addrspace(1) %out1001 ret void1002}1003 1004define amdgpu_kernel void @v2bfloat_kernel_preload_arg(ptr addrspace(1) inreg %out, <2 x bfloat> inreg %in) #0 {1005; GFX942-LABEL: v2bfloat_kernel_preload_arg:1006; GFX942: ; %bb.1:1007; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x01008; GFX942-NEXT: s_load_dword s4, s[0:1], 0x81009; GFX942-NEXT: s_waitcnt lgkmcnt(0)1010; GFX942-NEXT: s_branch .LBB20_01011; GFX942-NEXT: .p2align 81012; GFX942-NEXT: ; %bb.2:1013; GFX942-NEXT: .LBB20_0:1014; GFX942-NEXT: v_mov_b32_e32 v0, 01015; GFX942-NEXT: v_mov_b32_e32 v1, s41016; GFX942-NEXT: global_store_dword v0, v1, s[2:3]1017; GFX942-NEXT: s_endpgm1018;1019; GFX90a-LABEL: v2bfloat_kernel_preload_arg:1020; GFX90a: ; %bb.1:1021; GFX90a-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x01022; GFX90a-NEXT: s_load_dword s10, s[4:5], 0x81023; GFX90a-NEXT: s_waitcnt lgkmcnt(0)1024; GFX90a-NEXT: s_branch .LBB20_01025; GFX90a-NEXT: .p2align 81026; GFX90a-NEXT: ; %bb.2:1027; GFX90a-NEXT: .LBB20_0:1028; GFX90a-NEXT: v_mov_b32_e32 v0, 01029; GFX90a-NEXT: v_mov_b32_e32 v1, s101030; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]1031; GFX90a-NEXT: s_endpgm1032;1033; GFX1250-LABEL: v2bfloat_kernel_preload_arg:1034; GFX1250: ; %bb.0:1035; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11036; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s41037; GFX1250-NEXT: global_store_b32 v0, v1, s[2:3]1038; GFX1250-NEXT: s_endpgm1039 store <2 x bfloat> %in, ptr addrspace(1) %out1040 ret void1041}1042 1043define amdgpu_kernel void @v3bfloat_kernel_preload_arg(ptr addrspace(1) inreg %out, <3 x bfloat> inreg %in) #0 {1044; GFX942-LABEL: v3bfloat_kernel_preload_arg:1045; GFX942: ; %bb.1:1046; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x01047; GFX942-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x81048; GFX942-NEXT: s_waitcnt lgkmcnt(0)1049; GFX942-NEXT: s_branch .LBB21_01050; GFX942-NEXT: .p2align 81051; GFX942-NEXT: ; %bb.2:1052; GFX942-NEXT: .LBB21_0:1053; GFX942-NEXT: v_mov_b32_e32 v0, 01054; GFX942-NEXT: v_mov_b32_e32 v1, s51055; GFX942-NEXT: global_store_short v0, v1, s[2:3] offset:41056; GFX942-NEXT: v_mov_b32_e32 v1, s41057; GFX942-NEXT: global_store_dword v0, v1, s[2:3]1058; GFX942-NEXT: s_endpgm1059;1060; GFX90a-LABEL: v3bfloat_kernel_preload_arg:1061; GFX90a: ; %bb.1:1062; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x01063; GFX90a-NEXT: s_waitcnt lgkmcnt(0)1064; GFX90a-NEXT: s_branch .LBB21_01065; GFX90a-NEXT: .p2align 81066; GFX90a-NEXT: ; %bb.2:1067; GFX90a-NEXT: .LBB21_0:1068; GFX90a-NEXT: v_mov_b32_e32 v0, 01069; GFX90a-NEXT: v_mov_b32_e32 v1, s111070; GFX90a-NEXT: global_store_short v0, v1, s[8:9] offset:41071; GFX90a-NEXT: v_mov_b32_e32 v1, s101072; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]1073; GFX90a-NEXT: s_endpgm1074;1075; GFX1250-LABEL: v3bfloat_kernel_preload_arg:1076; GFX1250: ; %bb.0:1077; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11078; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s51079; GFX1250-NEXT: v_mov_b32_e32 v2, s41080; GFX1250-NEXT: s_clause 0x11081; GFX1250-NEXT: global_store_b16 v0, v1, s[2:3] offset:41082; GFX1250-NEXT: global_store_b32 v0, v2, s[2:3]1083; GFX1250-NEXT: s_endpgm1084 store <3 x bfloat> %in, ptr addrspace(1) %out1085 ret void1086}1087 1088define amdgpu_kernel void @v6bfloat_kernel_preload_arg(ptr addrspace(1) inreg %out, <6 x bfloat> inreg %in) #0 {1089; GFX942-LABEL: v6bfloat_kernel_preload_arg:1090; GFX942: ; %bb.1:1091; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x01092; GFX942-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x81093; GFX942-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x181094; GFX942-NEXT: s_waitcnt lgkmcnt(0)1095; GFX942-NEXT: s_branch .LBB22_01096; GFX942-NEXT: .p2align 81097; GFX942-NEXT: ; %bb.2:1098; GFX942-NEXT: .LBB22_0:1099; GFX942-NEXT: v_mov_b32_e32 v0, s61100; GFX942-NEXT: v_mov_b32_e32 v1, s71101; GFX942-NEXT: v_mov_b32_e32 v2, s81102; GFX942-NEXT: v_mov_b32_e32 v3, 01103; GFX942-NEXT: global_store_dwordx3 v3, v[0:2], s[2:3]1104; GFX942-NEXT: s_endpgm1105;1106; GFX90a-LABEL: v6bfloat_kernel_preload_arg:1107; GFX90a: ; %bb.1:1108; GFX90a-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x01109; GFX90a-NEXT: s_waitcnt lgkmcnt(0)1110; GFX90a-NEXT: s_branch .LBB22_01111; GFX90a-NEXT: .p2align 81112; GFX90a-NEXT: ; %bb.2:1113; GFX90a-NEXT: .LBB22_0:1114; GFX90a-NEXT: v_mov_b32_e32 v0, s121115; GFX90a-NEXT: v_mov_b32_e32 v1, s131116; GFX90a-NEXT: v_mov_b32_e32 v2, s141117; GFX90a-NEXT: v_mov_b32_e32 v3, 01118; GFX90a-NEXT: global_store_dwordx3 v3, v[0:2], s[8:9]1119; GFX90a-NEXT: s_endpgm1120;1121; GFX1250-LABEL: v6bfloat_kernel_preload_arg:1122; GFX1250: ; %bb.0:1123; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11124; GFX1250-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s71125; GFX1250-NEXT: v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v3, 01126; GFX1250-NEXT: global_store_b96 v3, v[0:2], s[2:3]1127; GFX1250-NEXT: s_endpgm1128 store <6 x bfloat> %in, ptr addrspace(1) %out1129 ret void1130}1131 1132define amdgpu_kernel void @half_v7bfloat_kernel_preload_arg(ptr addrspace(1) inreg %out, half inreg %in, <7 x bfloat> inreg %in2, ptr addrspace(1) inreg %out2) #0 {1133; GFX942-LABEL: half_v7bfloat_kernel_preload_arg:1134; GFX942: ; %bb.1:1135; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x01136; GFX942-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x81137; GFX942-NEXT: s_waitcnt lgkmcnt(0)1138; GFX942-NEXT: s_branch .LBB23_01139; GFX942-NEXT: .p2align 81140; GFX942-NEXT: ; %bb.2:1141; GFX942-NEXT: .LBB23_0:1142; GFX942-NEXT: v_mov_b32_e32 v3, 01143; GFX942-NEXT: v_mov_b32_e32 v0, s41144; GFX942-NEXT: global_store_short v3, v0, s[2:3]1145; GFX942-NEXT: v_mov_b32_e32 v0, s91146; GFX942-NEXT: global_store_short v3, v0, s[10:11] offset:121147; GFX942-NEXT: v_mov_b32_e32 v2, s81148; GFX942-NEXT: v_mov_b32_e32 v0, s61149; GFX942-NEXT: v_mov_b32_e32 v1, s71150; GFX942-NEXT: global_store_dwordx3 v3, v[0:2], s[10:11]1151; GFX942-NEXT: s_endpgm1152;1153; GFX90a-LABEL: half_v7bfloat_kernel_preload_arg:1154; GFX90a: ; %bb.1:1155; GFX90a-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x01156; GFX90a-NEXT: s_waitcnt lgkmcnt(0)1157; GFX90a-NEXT: s_branch .LBB23_01158; GFX90a-NEXT: .p2align 81159; GFX90a-NEXT: ; %bb.2:1160; GFX90a-NEXT: .LBB23_0:1161; GFX90a-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x201162; GFX90a-NEXT: v_mov_b32_e32 v3, 01163; GFX90a-NEXT: v_mov_b32_e32 v0, s101164; GFX90a-NEXT: global_store_short v3, v0, s[8:9]1165; GFX90a-NEXT: v_mov_b32_e32 v0, s151166; GFX90a-NEXT: s_waitcnt lgkmcnt(0)1167; GFX90a-NEXT: global_store_short v3, v0, s[0:1] offset:121168; GFX90a-NEXT: v_mov_b32_e32 v2, s141169; GFX90a-NEXT: v_mov_b32_e32 v0, s121170; GFX90a-NEXT: v_mov_b32_e32 v1, s131171; GFX90a-NEXT: global_store_dwordx3 v3, v[0:2], s[0:1]1172; GFX90a-NEXT: s_endpgm1173;1174; GFX1250-LABEL: half_v7bfloat_kernel_preload_arg:1175; GFX1250: ; %bb.0:1176; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11177; GFX1250-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, s41178; GFX1250-NEXT: v_dual_mov_b32 v5, s9 :: v_dual_mov_b32 v2, s81179; GFX1250-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s71180; GFX1250-NEXT: s_clause 0x21181; GFX1250-NEXT: global_store_b16 v3, v4, s[2:3]1182; GFX1250-NEXT: global_store_b16 v3, v5, s[10:11] offset:121183; GFX1250-NEXT: global_store_b96 v3, v[0:2], s[10:11]1184; GFX1250-NEXT: s_endpgm1185 store half %in, ptr addrspace(1) %out1186 store <7 x bfloat> %in2, ptr addrspace(1) %out21187 ret void1188}1189 1190define amdgpu_kernel void @i1_kernel_preload_arg(ptr addrspace(1) inreg %out, i1 inreg %in) #0 {1191; GFX942-LABEL: i1_kernel_preload_arg:1192; GFX942: ; %bb.1:1193; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x01194; GFX942-NEXT: s_load_dword s4, s[0:1], 0x81195; GFX942-NEXT: s_waitcnt lgkmcnt(0)1196; GFX942-NEXT: s_branch .LBB24_01197; GFX942-NEXT: .p2align 81198; GFX942-NEXT: ; %bb.2:1199; GFX942-NEXT: .LBB24_0:1200; GFX942-NEXT: s_and_b32 s0, s4, 11201; GFX942-NEXT: v_mov_b32_e32 v0, 01202; GFX942-NEXT: v_mov_b32_e32 v1, s01203; GFX942-NEXT: global_store_byte v0, v1, s[2:3]1204; GFX942-NEXT: s_endpgm1205;1206; GFX90a-LABEL: i1_kernel_preload_arg:1207; GFX90a: ; %bb.1:1208; GFX90a-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x01209; GFX90a-NEXT: s_load_dword s10, s[4:5], 0x81210; GFX90a-NEXT: s_waitcnt lgkmcnt(0)1211; GFX90a-NEXT: s_branch .LBB24_01212; GFX90a-NEXT: .p2align 81213; GFX90a-NEXT: ; %bb.2:1214; GFX90a-NEXT: .LBB24_0:1215; GFX90a-NEXT: s_and_b32 s0, s10, 11216; GFX90a-NEXT: v_mov_b32_e32 v0, 01217; GFX90a-NEXT: v_mov_b32_e32 v1, s01218; GFX90a-NEXT: global_store_byte v0, v1, s[8:9]1219; GFX90a-NEXT: s_endpgm1220;1221; GFX1250-LABEL: i1_kernel_preload_arg:1222; GFX1250: ; %bb.0:1223; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11224; GFX1250-NEXT: s_and_b32 s0, s4, 11225; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)1226; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s01227; GFX1250-NEXT: global_store_b8 v0, v1, s[2:3]1228; GFX1250-NEXT: s_endpgm1229 store i1 %in, ptr addrspace(1) %out1230 ret void1231}1232 1233define amdgpu_kernel void @fp128_kernel_preload_arg(ptr addrspace(1) inreg %out, fp128 inreg %in) #0 {1234; GFX942-LABEL: fp128_kernel_preload_arg:1235; GFX942: ; %bb.1:1236; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x01237; GFX942-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x81238; GFX942-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x181239; GFX942-NEXT: s_waitcnt lgkmcnt(0)1240; GFX942-NEXT: s_branch .LBB25_01241; GFX942-NEXT: .p2align 81242; GFX942-NEXT: ; %bb.2:1243; GFX942-NEXT: .LBB25_0:1244; GFX942-NEXT: v_mov_b32_e32 v4, 01245; GFX942-NEXT: v_mov_b32_e32 v0, s61246; GFX942-NEXT: v_mov_b32_e32 v1, s71247; GFX942-NEXT: v_mov_b32_e32 v2, s81248; GFX942-NEXT: v_mov_b32_e32 v3, s91249; GFX942-NEXT: global_store_dwordx4 v4, v[0:3], s[2:3]1250; GFX942-NEXT: s_endpgm1251;1252; GFX90a-LABEL: fp128_kernel_preload_arg:1253; GFX90a: ; %bb.1:1254; GFX90a-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x01255; GFX90a-NEXT: s_waitcnt lgkmcnt(0)1256; GFX90a-NEXT: s_branch .LBB25_01257; GFX90a-NEXT: .p2align 81258; GFX90a-NEXT: ; %bb.2:1259; GFX90a-NEXT: .LBB25_0:1260; GFX90a-NEXT: v_mov_b32_e32 v4, 01261; GFX90a-NEXT: v_mov_b32_e32 v0, s121262; GFX90a-NEXT: v_mov_b32_e32 v1, s131263; GFX90a-NEXT: v_mov_b32_e32 v2, s141264; GFX90a-NEXT: v_mov_b32_e32 v3, s151265; GFX90a-NEXT: global_store_dwordx4 v4, v[0:3], s[8:9]1266; GFX90a-NEXT: s_endpgm1267;1268; GFX1250-LABEL: fp128_kernel_preload_arg:1269; GFX1250: ; %bb.0:1270; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11271; GFX1250-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v0, s61272; GFX1250-NEXT: v_dual_mov_b32 v1, s7 :: v_dual_mov_b32 v2, s81273; GFX1250-NEXT: v_mov_b32_e32 v3, s91274; GFX1250-NEXT: global_store_b128 v4, v[0:3], s[2:3]1275; GFX1250-NEXT: s_endpgm1276 store fp128 %in, ptr addrspace(1) %out1277 ret void1278}1279 1280define amdgpu_kernel void @v7i8_kernel_preload_arg(ptr addrspace(1) inreg %out, <7 x i8> inreg %in) #0 {1281; GFX942-LABEL: v7i8_kernel_preload_arg:1282; GFX942: ; %bb.1:1283; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x01284; GFX942-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x81285; GFX942-NEXT: s_waitcnt lgkmcnt(0)1286; GFX942-NEXT: s_branch .LBB26_01287; GFX942-NEXT: .p2align 81288; GFX942-NEXT: ; %bb.2:1289; GFX942-NEXT: .LBB26_0:1290; GFX942-NEXT: s_lshr_b32 s1, s4, 241291; GFX942-NEXT: s_and_b32 s0, s4, 0xffff1292; GFX942-NEXT: s_lshl_b32 s1, s1, 81293; GFX942-NEXT: s_bfe_u32 s4, s4, 0x800101294; GFX942-NEXT: s_or_b32 s1, s4, s11295; GFX942-NEXT: s_lshl_b32 s1, s1, 161296; GFX942-NEXT: s_or_b32 s0, s0, s11297; GFX942-NEXT: v_mov_b32_e32 v0, 01298; GFX942-NEXT: v_mov_b32_e32 v1, s51299; GFX942-NEXT: global_store_byte_d16_hi v0, v1, s[2:3] offset:61300; GFX942-NEXT: global_store_short v0, v1, s[2:3] offset:41301; GFX942-NEXT: v_mov_b32_e32 v1, s01302; GFX942-NEXT: global_store_dword v0, v1, s[2:3]1303; GFX942-NEXT: s_endpgm1304;1305; GFX90a-LABEL: v7i8_kernel_preload_arg:1306; GFX90a: ; %bb.1:1307; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x01308; GFX90a-NEXT: s_waitcnt lgkmcnt(0)1309; GFX90a-NEXT: s_branch .LBB26_01310; GFX90a-NEXT: .p2align 81311; GFX90a-NEXT: ; %bb.2:1312; GFX90a-NEXT: .LBB26_0:1313; GFX90a-NEXT: s_lshr_b32 s1, s10, 241314; GFX90a-NEXT: s_lshl_b32 s1, s1, 81315; GFX90a-NEXT: s_bfe_u32 s2, s10, 0x800101316; GFX90a-NEXT: s_or_b32 s1, s2, s11317; GFX90a-NEXT: s_and_b32 s0, s10, 0xffff1318; GFX90a-NEXT: s_lshl_b32 s1, s1, 161319; GFX90a-NEXT: s_or_b32 s0, s0, s11320; GFX90a-NEXT: v_mov_b32_e32 v0, 01321; GFX90a-NEXT: v_mov_b32_e32 v1, s111322; GFX90a-NEXT: global_store_byte_d16_hi v0, v1, s[8:9] offset:61323; GFX90a-NEXT: global_store_short v0, v1, s[8:9] offset:41324; GFX90a-NEXT: v_mov_b32_e32 v1, s01325; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]1326; GFX90a-NEXT: s_endpgm1327;1328; GFX1250-LABEL: v7i8_kernel_preload_arg:1329; GFX1250: ; %bb.0:1330; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11331; GFX1250-NEXT: s_pack_lh_b32_b16 s0, 0, s41332; GFX1250-NEXT: s_and_b32 s1, s4, 0xffff1333; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s51334; GFX1250-NEXT: s_or_b32 s0, s1, s01335; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)1336; GFX1250-NEXT: v_mov_b32_e32 v2, s01337; GFX1250-NEXT: s_clause 0x21338; GFX1250-NEXT: global_store_d16_hi_b8 v0, v1, s[2:3] offset:61339; GFX1250-NEXT: global_store_b16 v0, v1, s[2:3] offset:41340; GFX1250-NEXT: global_store_b32 v0, v2, s[2:3]1341; GFX1250-NEXT: s_endpgm1342 store <7 x i8> %in, ptr addrspace(1) %out1343 ret void1344}1345 1346define amdgpu_kernel void @v7half_kernel_preload_arg(ptr addrspace(1) inreg %out, <7 x half> inreg %in) #0 {1347; GFX942-LABEL: v7half_kernel_preload_arg:1348; GFX942: ; %bb.1:1349; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x01350; GFX942-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x81351; GFX942-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x181352; GFX942-NEXT: s_waitcnt lgkmcnt(0)1353; GFX942-NEXT: s_branch .LBB27_01354; GFX942-NEXT: .p2align 81355; GFX942-NEXT: ; %bb.2:1356; GFX942-NEXT: .LBB27_0:1357; GFX942-NEXT: v_mov_b32_e32 v3, 01358; GFX942-NEXT: v_mov_b32_e32 v0, s91359; GFX942-NEXT: global_store_short v3, v0, s[2:3] offset:121360; GFX942-NEXT: v_mov_b32_e32 v2, s81361; GFX942-NEXT: v_mov_b32_e32 v0, s61362; GFX942-NEXT: v_mov_b32_e32 v1, s71363; GFX942-NEXT: global_store_dwordx3 v3, v[0:2], s[2:3]1364; GFX942-NEXT: s_endpgm1365;1366; GFX90a-LABEL: v7half_kernel_preload_arg:1367; GFX90a: ; %bb.1:1368; GFX90a-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x01369; GFX90a-NEXT: s_waitcnt lgkmcnt(0)1370; GFX90a-NEXT: s_branch .LBB27_01371; GFX90a-NEXT: .p2align 81372; GFX90a-NEXT: ; %bb.2:1373; GFX90a-NEXT: .LBB27_0:1374; GFX90a-NEXT: v_mov_b32_e32 v3, 01375; GFX90a-NEXT: v_mov_b32_e32 v0, s151376; GFX90a-NEXT: global_store_short v3, v0, s[8:9] offset:121377; GFX90a-NEXT: v_mov_b32_e32 v2, s141378; GFX90a-NEXT: v_mov_b32_e32 v0, s121379; GFX90a-NEXT: v_mov_b32_e32 v1, s131380; GFX90a-NEXT: global_store_dwordx3 v3, v[0:2], s[8:9]1381; GFX90a-NEXT: s_endpgm1382;1383; GFX1250-LABEL: v7half_kernel_preload_arg:1384; GFX1250: ; %bb.0:1385; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11386; GFX1250-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, s91387; GFX1250-NEXT: v_dual_mov_b32 v2, s8 :: v_dual_mov_b32 v0, s61388; GFX1250-NEXT: v_mov_b32_e32 v1, s71389; GFX1250-NEXT: s_clause 0x11390; GFX1250-NEXT: global_store_b16 v3, v4, s[2:3] offset:121391; GFX1250-NEXT: global_store_b96 v3, v[0:2], s[2:3]1392; GFX1250-NEXT: s_endpgm1393 store <7 x half> %in, ptr addrspace(1) %out1394 ret void1395}1396 1397define amdgpu_kernel void @i16_i32_kernel_preload_arg(ptr addrspace(1) inreg %out, i16 inreg %in, i32 inreg %in2, ptr addrspace(1) inreg %out2) #0 {1398; GFX942-LABEL: i16_i32_kernel_preload_arg:1399; GFX942: ; %bb.1:1400; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x01401; GFX942-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x81402; GFX942-NEXT: s_waitcnt lgkmcnt(0)1403; GFX942-NEXT: s_branch .LBB28_01404; GFX942-NEXT: .p2align 81405; GFX942-NEXT: ; %bb.2:1406; GFX942-NEXT: .LBB28_0:1407; GFX942-NEXT: v_mov_b32_e32 v0, 01408; GFX942-NEXT: v_mov_b32_e32 v1, s41409; GFX942-NEXT: global_store_short v0, v1, s[2:3]1410; GFX942-NEXT: v_mov_b32_e32 v1, s51411; GFX942-NEXT: global_store_dword v0, v1, s[6:7]1412; GFX942-NEXT: s_endpgm1413;1414; GFX90a-LABEL: i16_i32_kernel_preload_arg:1415; GFX90a: ; %bb.1:1416; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x01417; GFX90a-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x101418; GFX90a-NEXT: s_waitcnt lgkmcnt(0)1419; GFX90a-NEXT: s_branch .LBB28_01420; GFX90a-NEXT: .p2align 81421; GFX90a-NEXT: ; %bb.2:1422; GFX90a-NEXT: .LBB28_0:1423; GFX90a-NEXT: v_mov_b32_e32 v0, 01424; GFX90a-NEXT: v_mov_b32_e32 v1, s101425; GFX90a-NEXT: global_store_short v0, v1, s[8:9]1426; GFX90a-NEXT: v_mov_b32_e32 v1, s111427; GFX90a-NEXT: global_store_dword v0, v1, s[12:13]1428; GFX90a-NEXT: s_endpgm1429;1430; GFX1250-LABEL: i16_i32_kernel_preload_arg:1431; GFX1250: ; %bb.0:1432; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11433; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s41434; GFX1250-NEXT: v_mov_b32_e32 v2, s51435; GFX1250-NEXT: s_clause 0x11436; GFX1250-NEXT: global_store_b16 v0, v1, s[2:3]1437; GFX1250-NEXT: global_store_b32 v0, v2, s[6:7]1438; GFX1250-NEXT: s_endpgm1439 store i16 %in, ptr addrspace(1) %out1440 store i32 %in2, ptr addrspace(1) %out21441 ret void1442}1443 1444define amdgpu_kernel void @i16_v3i32_kernel_preload_arg(ptr addrspace(1) inreg %out, i16 inreg %in, <3 x i32> inreg %in2, ptr addrspace(1) inreg %out2) #0 {1445; GFX942-LABEL: i16_v3i32_kernel_preload_arg:1446; GFX942: ; %bb.1:1447; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x01448; GFX942-NEXT: s_load_dwordx8 s[4:11], s[0:1], 0x81449; GFX942-NEXT: s_waitcnt lgkmcnt(0)1450; GFX942-NEXT: s_branch .LBB29_01451; GFX942-NEXT: .p2align 81452; GFX942-NEXT: ; %bb.2:1453; GFX942-NEXT: .LBB29_0:1454; GFX942-NEXT: v_mov_b32_e32 v3, 01455; GFX942-NEXT: v_mov_b32_e32 v4, s41456; GFX942-NEXT: v_mov_b32_e32 v0, s61457; GFX942-NEXT: v_mov_b32_e32 v1, s71458; GFX942-NEXT: v_mov_b32_e32 v2, s81459; GFX942-NEXT: global_store_short v3, v4, s[2:3]1460; GFX942-NEXT: global_store_dwordx3 v3, v[0:2], s[10:11]1461; GFX942-NEXT: s_endpgm1462;1463; GFX90a-LABEL: i16_v3i32_kernel_preload_arg:1464; GFX90a: ; %bb.1:1465; GFX90a-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x01466; GFX90a-NEXT: s_waitcnt lgkmcnt(0)1467; GFX90a-NEXT: s_branch .LBB29_01468; GFX90a-NEXT: .p2align 81469; GFX90a-NEXT: ; %bb.2:1470; GFX90a-NEXT: .LBB29_0:1471; GFX90a-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x201472; GFX90a-NEXT: v_mov_b32_e32 v3, 01473; GFX90a-NEXT: v_mov_b32_e32 v4, s101474; GFX90a-NEXT: v_mov_b32_e32 v0, s121475; GFX90a-NEXT: v_mov_b32_e32 v1, s131476; GFX90a-NEXT: v_mov_b32_e32 v2, s141477; GFX90a-NEXT: global_store_short v3, v4, s[8:9]1478; GFX90a-NEXT: s_waitcnt lgkmcnt(0)1479; GFX90a-NEXT: global_store_dwordx3 v3, v[0:2], s[0:1]1480; GFX90a-NEXT: s_endpgm1481;1482; GFX1250-LABEL: i16_v3i32_kernel_preload_arg:1483; GFX1250: ; %bb.0:1484; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11485; GFX1250-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_mov_b32 v4, s41486; GFX1250-NEXT: v_dual_mov_b32 v0, s6 :: v_dual_mov_b32 v1, s71487; GFX1250-NEXT: v_mov_b32_e32 v2, s81488; GFX1250-NEXT: s_clause 0x11489; GFX1250-NEXT: global_store_b16 v3, v4, s[2:3]1490; GFX1250-NEXT: global_store_b96 v3, v[0:2], s[10:11]1491; GFX1250-NEXT: s_endpgm1492 store i16 %in, ptr addrspace(1) %out1493 store <3 x i32> %in2, ptr addrspace(1) %out21494 ret void1495}1496 1497define amdgpu_kernel void @i16_i16_kernel_preload_arg(ptr addrspace(1) inreg %out, i16 inreg %in, i16 inreg %in2, ptr addrspace(1) inreg %out2) #0 {1498; GFX942-LABEL: i16_i16_kernel_preload_arg:1499; GFX942: ; %bb.1:1500; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x01501; GFX942-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x81502; GFX942-NEXT: s_waitcnt lgkmcnt(0)1503; GFX942-NEXT: s_branch .LBB30_01504; GFX942-NEXT: .p2align 81505; GFX942-NEXT: ; %bb.2:1506; GFX942-NEXT: .LBB30_0:1507; GFX942-NEXT: v_mov_b32_e32 v0, 01508; GFX942-NEXT: v_mov_b32_e32 v1, s41509; GFX942-NEXT: global_store_short v0, v1, s[2:3]1510; GFX942-NEXT: global_store_short_d16_hi v0, v1, s[6:7]1511; GFX942-NEXT: s_endpgm1512;1513; GFX90a-LABEL: i16_i16_kernel_preload_arg:1514; GFX90a: ; %bb.1:1515; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x01516; GFX90a-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x101517; GFX90a-NEXT: s_waitcnt lgkmcnt(0)1518; GFX90a-NEXT: s_branch .LBB30_01519; GFX90a-NEXT: .p2align 81520; GFX90a-NEXT: ; %bb.2:1521; GFX90a-NEXT: .LBB30_0:1522; GFX90a-NEXT: v_mov_b32_e32 v0, 01523; GFX90a-NEXT: v_mov_b32_e32 v1, s101524; GFX90a-NEXT: global_store_short v0, v1, s[8:9]1525; GFX90a-NEXT: global_store_short_d16_hi v0, v1, s[12:13]1526; GFX90a-NEXT: s_endpgm1527;1528; GFX1250-LABEL: i16_i16_kernel_preload_arg:1529; GFX1250: ; %bb.0:1530; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11531; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s41532; GFX1250-NEXT: s_clause 0x11533; GFX1250-NEXT: global_store_b16 v0, v1, s[2:3]1534; GFX1250-NEXT: global_store_d16_hi_b16 v0, v1, s[6:7]1535; GFX1250-NEXT: s_endpgm1536 store i16 %in, ptr addrspace(1) %out1537 store i16 %in2, ptr addrspace(1) %out21538 ret void1539}1540 1541define amdgpu_kernel void @i16_v2i8_kernel_preload_arg(ptr addrspace(1) inreg %out, i16 inreg %in, <2 x i8> inreg %in2, ptr addrspace(1) inreg %out2) #0 {1542; GFX942-LABEL: i16_v2i8_kernel_preload_arg:1543; GFX942: ; %bb.1:1544; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x01545; GFX942-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x81546; GFX942-NEXT: s_waitcnt lgkmcnt(0)1547; GFX942-NEXT: s_branch .LBB31_01548; GFX942-NEXT: .p2align 81549; GFX942-NEXT: ; %bb.2:1550; GFX942-NEXT: .LBB31_0:1551; GFX942-NEXT: s_lshr_b32 s0, s4, 241552; GFX942-NEXT: s_lshl_b32 s0, s0, 81553; GFX942-NEXT: s_bfe_u32 s1, s4, 0x800101554; GFX942-NEXT: s_or_b32 s0, s1, s01555; GFX942-NEXT: v_mov_b32_e32 v0, 01556; GFX942-NEXT: v_mov_b32_e32 v1, s41557; GFX942-NEXT: global_store_short v0, v1, s[2:3]1558; GFX942-NEXT: v_mov_b32_e32 v1, s01559; GFX942-NEXT: global_store_short v0, v1, s[6:7]1560; GFX942-NEXT: s_endpgm1561;1562; GFX90a-LABEL: i16_v2i8_kernel_preload_arg:1563; GFX90a: ; %bb.1:1564; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x01565; GFX90a-NEXT: s_load_dwordx2 s[12:13], s[4:5], 0x101566; GFX90a-NEXT: s_waitcnt lgkmcnt(0)1567; GFX90a-NEXT: s_branch .LBB31_01568; GFX90a-NEXT: .p2align 81569; GFX90a-NEXT: ; %bb.2:1570; GFX90a-NEXT: .LBB31_0:1571; GFX90a-NEXT: s_lshr_b32 s0, s10, 241572; GFX90a-NEXT: s_lshl_b32 s0, s0, 81573; GFX90a-NEXT: s_bfe_u32 s1, s10, 0x800101574; GFX90a-NEXT: s_or_b32 s0, s1, s01575; GFX90a-NEXT: v_mov_b32_e32 v0, 01576; GFX90a-NEXT: v_mov_b32_e32 v1, s101577; GFX90a-NEXT: global_store_short v0, v1, s[8:9]1578; GFX90a-NEXT: v_mov_b32_e32 v1, s01579; GFX90a-NEXT: global_store_short v0, v1, s[12:13]1580; GFX90a-NEXT: s_endpgm1581;1582; GFX1250-LABEL: i16_v2i8_kernel_preload_arg:1583; GFX1250: ; %bb.0:1584; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11585; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s41586; GFX1250-NEXT: s_clause 0x11587; GFX1250-NEXT: global_store_b16 v0, v1, s[2:3]1588; GFX1250-NEXT: global_store_d16_hi_b16 v0, v1, s[6:7]1589; GFX1250-NEXT: s_endpgm1590 store i16 %in, ptr addrspace(1) %out1591 store <2 x i8> %in2, ptr addrspace(1) %out21592 ret void1593}1594 1595; The second argument is not expected to be preloaded with the current behavior.1596 1597define amdgpu_kernel void @i32_ptr1_i32_staggered_preload_arg(i32 inreg %arg0, ptr addrspace(1) %out, i32 inreg %arg1) #0 {1598; GFX942-LABEL: i32_ptr1_i32_staggered_preload_arg:1599; GFX942: ; %bb.1:1600; GFX942-NEXT: s_load_dword s2, s[0:1], 0x01601; GFX942-NEXT: s_waitcnt lgkmcnt(0)1602; GFX942-NEXT: s_branch .LBB32_01603; GFX942-NEXT: .p2align 81604; GFX942-NEXT: ; %bb.2:1605; GFX942-NEXT: .LBB32_0:1606; GFX942-NEXT: s_load_dword s3, s[0:1], 0x101607; GFX942-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x81608; GFX942-NEXT: v_mov_b32_e32 v0, 01609; GFX942-NEXT: s_waitcnt lgkmcnt(0)1610; GFX942-NEXT: s_add_i32 s0, s2, s31611; GFX942-NEXT: v_mov_b32_e32 v1, s01612; GFX942-NEXT: global_store_dword v0, v1, s[4:5]1613; GFX942-NEXT: s_endpgm1614;1615; GFX90a-LABEL: i32_ptr1_i32_staggered_preload_arg:1616; GFX90a: ; %bb.1:1617; GFX90a-NEXT: s_load_dword s8, s[4:5], 0x01618; GFX90a-NEXT: s_waitcnt lgkmcnt(0)1619; GFX90a-NEXT: s_branch .LBB32_01620; GFX90a-NEXT: .p2align 81621; GFX90a-NEXT: ; %bb.2:1622; GFX90a-NEXT: .LBB32_0:1623; GFX90a-NEXT: s_load_dword s2, s[4:5], 0x101624; GFX90a-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x81625; GFX90a-NEXT: v_mov_b32_e32 v0, 01626; GFX90a-NEXT: s_waitcnt lgkmcnt(0)1627; GFX90a-NEXT: s_add_i32 s2, s8, s21628; GFX90a-NEXT: v_mov_b32_e32 v1, s21629; GFX90a-NEXT: global_store_dword v0, v1, s[0:1]1630; GFX90a-NEXT: s_endpgm1631;1632; GFX1250-LABEL: i32_ptr1_i32_staggered_preload_arg:1633; GFX1250: ; %bb.0:1634; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11635; GFX1250-NEXT: s_load_b96 s[4:6], s[0:1], 0x81636; GFX1250-NEXT: s_wait_kmcnt 0x01637; GFX1250-NEXT: s_add_co_i32 s0, s2, s61638; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)1639; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s01640; GFX1250-NEXT: global_store_b32 v0, v1, s[4:5]1641; GFX1250-NEXT: s_endpgm1642 %add = add i32 %arg0, %arg11643 store i32 %add, ptr addrspace(1) %out1644 ret void1645}1646 1647define amdgpu_kernel void @ptr1_i8_trailing_unused(ptr addrspace(1) inreg %out, i8 inreg %arg0, i32 inreg %unused) #0 {1648; GFX942-LABEL: ptr1_i8_trailing_unused:1649; GFX942: ; %bb.1:1650; GFX942-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x01651; GFX942-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x81652; GFX942-NEXT: s_waitcnt lgkmcnt(0)1653; GFX942-NEXT: s_branch .LBB33_01654; GFX942-NEXT: .p2align 81655; GFX942-NEXT: ; %bb.2:1656; GFX942-NEXT: .LBB33_0:1657; GFX942-NEXT: s_and_b32 s0, s4, 0xff1658; GFX942-NEXT: v_mov_b32_e32 v0, 01659; GFX942-NEXT: v_mov_b32_e32 v1, s01660; GFX942-NEXT: global_store_dword v0, v1, s[2:3]1661; GFX942-NEXT: s_endpgm1662;1663; GFX90a-LABEL: ptr1_i8_trailing_unused:1664; GFX90a: ; %bb.1:1665; GFX90a-NEXT: s_load_dwordx4 s[8:11], s[4:5], 0x01666; GFX90a-NEXT: s_waitcnt lgkmcnt(0)1667; GFX90a-NEXT: s_branch .LBB33_01668; GFX90a-NEXT: .p2align 81669; GFX90a-NEXT: ; %bb.2:1670; GFX90a-NEXT: .LBB33_0:1671; GFX90a-NEXT: s_and_b32 s0, s10, 0xff1672; GFX90a-NEXT: v_mov_b32_e32 v0, 01673; GFX90a-NEXT: v_mov_b32_e32 v1, s01674; GFX90a-NEXT: global_store_dword v0, v1, s[8:9]1675; GFX90a-NEXT: s_endpgm1676;1677; GFX1250-LABEL: ptr1_i8_trailing_unused:1678; GFX1250: ; %bb.0:1679; GFX1250-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_WAVE_MODE, 25, 1), 11680; GFX1250-NEXT: s_and_b32 s0, s4, 0xff1681; GFX1250-NEXT: s_delay_alu instid0(SALU_CYCLE_1)1682; GFX1250-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s01683; GFX1250-NEXT: global_store_b32 v0, v1, s[2:3]1684; GFX1250-NEXT: s_endpgm1685 %ext = zext i8 %arg0 to i321686 store i32 %ext, ptr addrspace(1) %out1687 ret void1688}1689 1690attributes #0 = { "amdgpu-agpr-alloc"="0" "amdgpu-no-completion-action" "amdgpu-no-default-queue" "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" }1691