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1; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=fiji < %s | FileCheck -enable-var-scope --check-prefixes=GCN,OPT %s2; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=hawaii < %s | FileCheck -enable-var-scope --check-prefixes=GCN,OPT %s3; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=iceland < %s | FileCheck -enable-var-scope --check-prefixes=GCN,OPT %s4; RUN: llc -O0 -mtriple=amdgcn--amdhsa -mcpu=fiji < %s | FileCheck -enable-var-scope --check-prefixes=GCN,OPTNONE %s5 6; There are no stack objects, but still a private memory access. The7; private access regiters need to be correctly initialized anyway, and8; shifted down to the end of the used registers.9 10; GCN-LABEL: {{^}}store_to_undef:11; OPT-DAG: s_mov_b64 s[[[RSRC_LO:[0-9]+]]:{{[0-9]+\]}}, s[0:1]12; OPT-DAG: s_mov_b64 s{{\[[0-9]+}}:[[RSRC_HI:[0-9]+]]], s[2:3]13; OPT: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[[[RSRC_LO]]:[[RSRC_HI]]], 0 offen{{$}}14 15; -O0 should assume spilling, so the input scratch resource descriptor16; -should be used directly without any copies.17 18; OPTNONE-NOT: s_mov_b3219; OPTNONE: buffer_store_dword v{{[0-9]+}}, v{{[0-9]+}}, s[0:3], 0 offen{{$}}20define amdgpu_kernel void @store_to_undef() #0 {21 store volatile i32 0, ptr addrspace(5) poison22 ret void23}24 25; GCN-LABEL: {{^}}store_to_inttoptr:26; OPT-DAG: s_mov_b64 s[[[RSRC_LO:[0-9]+]]:{{[0-9]+\]}}, s[0:1]27; OPT-DAG: s_mov_b64 s{{\[[0-9]+}}:[[RSRC_HI:[0-9]+]]], s[2:3]28; OPT: buffer_store_dword v{{[0-9]+}}, off, s[[[RSRC_LO]]:[[RSRC_HI]]], 0 offset:124{{$}}29define amdgpu_kernel void @store_to_inttoptr() #0 {30 store volatile i32 0, ptr addrspace(5) inttoptr (i32 124 to ptr addrspace(5))31 ret void32}33 34; GCN-LABEL: {{^}}load_from_undef:35; OPT-DAG: s_mov_b64 s[[[RSRC_LO:[0-9]+]]:{{[0-9]+\]}}, s[0:1]36; OPT-DAG: s_mov_b64 s{{\[[0-9]+}}:[[RSRC_HI:[0-9]+]]], s[2:3]37; OPT: buffer_load_dword v{{[0-9]+}}, v{{[0-9]+}}, s[[[RSRC_LO]]:[[RSRC_HI]]], 0 offen glc{{$}}38define amdgpu_kernel void @load_from_undef() #0 {39 %ld = load volatile i32, ptr addrspace(5) poison40 ret void41}42 43; GCN-LABEL: {{^}}load_from_inttoptr:44; OPT-DAG: s_mov_b64 s[[[RSRC_LO:[0-9]+]]:{{[0-9]+\]}}, s[0:1]45; OPT-DAG: s_mov_b64 s{{\[[0-9]+}}:[[RSRC_HI:[0-9]+]]], s[2:3]46; OPT: buffer_load_dword v{{[0-9]+}}, off, s[[[RSRC_LO]]:[[RSRC_HI]]], 0 offset:124 glc{{$}}47define amdgpu_kernel void @load_from_inttoptr() #0 {48 %ld = load volatile i32, ptr addrspace(5) inttoptr (i32 124 to ptr addrspace(5))49 ret void50}51 52attributes #0 = { nounwind }53