211 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 22; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -passes=amdgpu-promote-alloca < %s | FileCheck %s3 4define amdgpu_kernel void @test_overwrite(i64 %val, i1 %cond) {5; CHECK-LABEL: define amdgpu_kernel void @test_overwrite6; CHECK-SAME: (i64 [[VAL:%.*]], i1 [[COND:%.*]]) {7; CHECK-NEXT: entry:8; CHECK-NEXT: [[STACK:%.*]] = freeze <3 x i64> poison9; CHECK-NEXT: [[TMP0:%.*]] = insertelement <3 x i64> [[STACK]], i64 43, i32 010; CHECK-NEXT: br i1 [[COND]], label [[LOOP:%.*]], label [[END:%.*]]11; CHECK: loop:12; CHECK-NEXT: [[PROMOTEALLOCA1:%.*]] = phi <3 x i64> [ [[TMP3:%.*]], [[LOOP]] ], [ [[TMP0]], [[ENTRY:%.*]] ]13; CHECK-NEXT: [[TMP1:%.*]] = extractelement <3 x i64> [[PROMOTEALLOCA1]], i32 014; CHECK-NEXT: [[TMP2:%.*]] = insertelement <3 x i64> [[PROMOTEALLOCA1]], i64 68, i32 015; CHECK-NEXT: [[TMP3]] = insertelement <3 x i64> [[TMP2]], i64 32, i32 016; CHECK-NEXT: [[LOOP_CC:%.*]] = icmp ne i64 [[TMP1]], 6817; CHECK-NEXT: br i1 [[LOOP_CC]], label [[LOOP]], label [[END]]18; CHECK: end:19; CHECK-NEXT: [[PROMOTEALLOCA:%.*]] = phi <3 x i64> [ [[TMP3]], [[LOOP]] ], [ [[TMP0]], [[ENTRY]] ]20; CHECK-NEXT: [[TMP4:%.*]] = extractelement <3 x i64> [[PROMOTEALLOCA]], i32 021; CHECK-NEXT: ret void22;23entry:24 %stack = alloca [3 x i64], align 4, addrspace(5)25 store i64 43, ptr addrspace(5) %stack26 br i1 %cond, label %loop, label %end27 28loop:29 %load.0 = load i64, ptr addrspace(5) %stack30 store i64 68, ptr addrspace(5) %stack31 %load.1 = load i64, ptr addrspace(5) %stack32 store i64 32, ptr addrspace(5) %stack33 %loop.cc = icmp ne i64 %load.0, %load.134 br i1 %loop.cc, label %loop, label %end35 36end:37 %reload = load i64, ptr addrspace(5) %stack38 ret void39}40 41define <4 x i64> @test_fullvec_out_of_bounds(<4 x i64> %arg) {42; CHECK-LABEL: define <4 x i64> @test_fullvec_out_of_bounds43; CHECK-SAME: (<4 x i64> [[ARG:%.*]]) {44; CHECK-NEXT: entry:45; CHECK-NEXT: [[STACK:%.*]] = freeze <4 x i64> poison46; CHECK-NEXT: [[TMP0:%.*]] = extractelement <4 x i64> [[ARG]], i64 047; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i64> [[STACK]], i64 [[TMP0]], i32 348; CHECK-NEXT: [[TMP2:%.*]] = extractelement <4 x i64> [[ARG]], i64 149; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x i64> [[ARG]], i64 250; CHECK-NEXT: [[TMP4:%.*]] = extractelement <4 x i64> [[ARG]], i64 351; CHECK-NEXT: ret <4 x i64> poison52;53entry:54 %stack = alloca [4 x i64], align 4, addrspace(5)55 %stack.2 = getelementptr inbounds [4 x i64], ptr addrspace(5) %stack, i32 0, i32 256 %stack.3 = getelementptr inbounds [4 x i64], ptr addrspace(5) %stack, i32 0, i32 357 store <4 x i64> %arg, ptr addrspace(5) %stack.358 %reload = load <4 x i64>, ptr addrspace(5) %stack.259 ret <4 x i64> %reload60}61 62define amdgpu_kernel void @test_no_overwrite(i64 %val, i1 %cond) {63; CHECK-LABEL: define amdgpu_kernel void @test_no_overwrite64; CHECK-SAME: (i64 [[VAL:%.*]], i1 [[COND:%.*]]) {65; CHECK-NEXT: entry:66; CHECK-NEXT: [[STACK:%.*]] = freeze <3 x i64> poison67; CHECK-NEXT: [[TMP0:%.*]] = insertelement <3 x i64> [[STACK]], i64 43, i32 068; CHECK-NEXT: br i1 [[COND]], label [[LOOP:%.*]], label [[END:%.*]]69; CHECK: loop:70; CHECK-NEXT: [[PROMOTEALLOCA1:%.*]] = phi <3 x i64> [ [[TMP2:%.*]], [[LOOP]] ], [ [[TMP0]], [[ENTRY:%.*]] ]71; CHECK-NEXT: [[TMP1:%.*]] = extractelement <3 x i64> [[PROMOTEALLOCA1]], i32 072; CHECK-NEXT: [[TMP2]] = insertelement <3 x i64> [[PROMOTEALLOCA1]], i64 32, i32 173; CHECK-NEXT: [[LOOP_CC:%.*]] = icmp ne i64 [[TMP1]], 3274; CHECK-NEXT: br i1 [[LOOP_CC]], label [[LOOP]], label [[END]]75; CHECK: end:76; CHECK-NEXT: [[PROMOTEALLOCA:%.*]] = phi <3 x i64> [ [[TMP2]], [[LOOP]] ], [ [[TMP0]], [[ENTRY]] ]77; CHECK-NEXT: [[TMP3:%.*]] = extractelement <3 x i64> [[PROMOTEALLOCA]], i32 078; CHECK-NEXT: [[TMP4:%.*]] = extractelement <3 x i64> [[PROMOTEALLOCA]], i32 179; CHECK-NEXT: ret void80;81entry:82 %stack = alloca [3 x i64], align 4, addrspace(5)83 %stack.1 = getelementptr inbounds i64, ptr addrspace(5) %stack, i32 184 store i64 43, ptr addrspace(5) %stack85 br i1 %cond, label %loop, label %end86 87loop:88 %load = load i64, ptr addrspace(5) %stack89 store i64 32, ptr addrspace(5) %stack.190 %loop.cc = icmp ne i64 %load, 3291 br i1 %loop.cc, label %loop, label %end92 93end:94 %reload = load i64, ptr addrspace(5) %stack95 %reload.1 = load i64, ptr addrspace(5) %stack.196 ret void97}98 99define ptr @alloca_load_store_ptr64_full_ivec(ptr %arg) {100; CHECK-LABEL: define ptr @alloca_load_store_ptr64_full_ivec101; CHECK-SAME: (ptr [[ARG:%.*]]) {102; CHECK-NEXT: entry:103; CHECK-NEXT: [[ALLOCA:%.*]] = freeze <8 x i8> poison104; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr [[ARG]] to i64105; CHECK-NEXT: [[TMP1:%.*]] = bitcast i64 [[TMP0]] to <8 x i8>106; CHECK-NEXT: ret ptr [[ARG]]107;108entry:109 %alloca = alloca [8 x i8], align 8, addrspace(5)110 store ptr %arg, ptr addrspace(5) %alloca, align 8111 %tmp = load ptr, ptr addrspace(5) %alloca, align 8112 ret ptr %tmp113}114 115define ptr addrspace(3) @alloca_load_store_ptr32_full_ivec(ptr addrspace(3) %arg) {116; CHECK-LABEL: define ptr addrspace(3) @alloca_load_store_ptr32_full_ivec117; CHECK-SAME: (ptr addrspace(3) [[ARG:%.*]]) {118; CHECK-NEXT: entry:119; CHECK-NEXT: [[ALLOCA:%.*]] = freeze <4 x i8> poison120; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint ptr addrspace(3) [[ARG]] to i32121; CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[TMP0]] to <4 x i8>122; CHECK-NEXT: ret ptr addrspace(3) [[ARG]]123;124entry:125 %alloca = alloca [4 x i8], align 8, addrspace(5)126 store ptr addrspace(3) %arg, ptr addrspace(5) %alloca, align 8127 %tmp = load ptr addrspace(3), ptr addrspace(5) %alloca, align 8128 ret ptr addrspace(3) %tmp129}130 131define <4 x ptr addrspace(3)> @alloca_load_store_ptr_mixed_full_ptrvec(<2 x ptr> %arg) {132; CHECK-LABEL: define <4 x ptr addrspace(3)> @alloca_load_store_ptr_mixed_full_ptrvec133; CHECK-SAME: (<2 x ptr> [[ARG:%.*]]) {134; CHECK-NEXT: entry:135; CHECK-NEXT: [[ALLOCA:%.*]] = freeze <4 x i32> poison136; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint <2 x ptr> [[ARG]] to <2 x i64>137; CHECK-NEXT: [[TMP1:%.*]] = bitcast <2 x i64> [[TMP0]] to <4 x i32>138; CHECK-NEXT: [[TMP2:%.*]] = inttoptr <4 x i32> [[TMP1]] to <4 x ptr addrspace(3)>139; CHECK-NEXT: ret <4 x ptr addrspace(3)> [[TMP2]]140;141entry:142 %alloca = alloca [4 x i32], align 8, addrspace(5)143 store <2 x ptr> %arg, ptr addrspace(5) %alloca, align 8144 %tmp = load <4 x ptr addrspace(3)>, ptr addrspace(5) %alloca, align 8145 ret <4 x ptr addrspace(3)> %tmp146}147 148define <8 x i16> @ptralloca_load_store_ints_full(<2 x i64> %arg) {149; CHECK-LABEL: define <8 x i16> @ptralloca_load_store_ints_full150; CHECK-SAME: (<2 x i64> [[ARG:%.*]]) {151; CHECK-NEXT: entry:152; CHECK-NEXT: [[STACK:%.*]] = freeze <4 x ptr addrspace(5)> poison153; CHECK-NEXT: [[TMP0:%.*]] = bitcast <2 x i64> [[ARG]] to <4 x i32>154; CHECK-NEXT: [[TMP1:%.*]] = inttoptr <4 x i32> [[TMP0]] to <4 x ptr addrspace(5)>155; CHECK-NEXT: [[TMP2:%.*]] = bitcast <4 x i32> [[TMP0]] to <8 x i16>156; CHECK-NEXT: ret <8 x i16> [[TMP2]]157;158entry:159 %stack = alloca [4 x ptr addrspace(5)], align 4, addrspace(5)160 store <2 x i64> %arg, ptr addrspace(5) %stack161 %reload = load <8 x i16>, ptr addrspace(5) %stack162 ret <8 x i16> %reload163}164 165define void @alloca_load_store_ptr_mixed_ptrvec(<2 x ptr addrspace(3)> %arg) {166; CHECK-LABEL: define void @alloca_load_store_ptr_mixed_ptrvec167; CHECK-SAME: (<2 x ptr addrspace(3)> [[ARG:%.*]]) {168; CHECK-NEXT: entry:169; CHECK-NEXT: [[ALLOCA:%.*]] = freeze <8 x i32> poison170; CHECK-NEXT: [[TMP0:%.*]] = ptrtoint <2 x ptr addrspace(3)> [[ARG]] to <2 x i32>171; CHECK-NEXT: [[TMP1:%.*]] = extractelement <2 x i32> [[TMP0]], i64 0172; CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x i32> [[ALLOCA]], i32 [[TMP1]], i32 0173; CHECK-NEXT: [[TMP3:%.*]] = extractelement <2 x i32> [[TMP0]], i64 1174; CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x i32> [[TMP2]], i32 [[TMP3]], i32 1175; CHECK-NEXT: [[TMP5:%.*]] = insertelement <2 x i32> poison, i32 [[TMP1]], i64 0176; CHECK-NEXT: [[TMP6:%.*]] = insertelement <2 x i32> [[TMP5]], i32 [[TMP3]], i64 1177; CHECK-NEXT: [[TMP7:%.*]] = inttoptr <2 x i32> [[TMP6]] to <2 x ptr addrspace(3)>178; CHECK-NEXT: [[TMP8:%.*]] = insertelement <4 x i32> poison, i32 [[TMP1]], i64 0179; CHECK-NEXT: [[TMP9:%.*]] = insertelement <4 x i32> [[TMP8]], i32 [[TMP3]], i64 1180; CHECK-NEXT: [[TMP10:%.*]] = extractelement <8 x i32> [[TMP4]], i32 2181; CHECK-NEXT: [[TMP11:%.*]] = insertelement <4 x i32> [[TMP9]], i32 [[TMP10]], i64 2182; CHECK-NEXT: [[TMP12:%.*]] = extractelement <8 x i32> [[TMP4]], i32 3183; CHECK-NEXT: [[TMP13:%.*]] = insertelement <4 x i32> [[TMP11]], i32 [[TMP12]], i64 3184; CHECK-NEXT: [[TMP14:%.*]] = inttoptr <4 x i32> [[TMP13]] to <4 x ptr addrspace(3)>185; CHECK-NEXT: ret void186;187entry:188 %alloca = alloca [8 x i32], align 8, addrspace(5)189 store <2 x ptr addrspace(3)> %arg, ptr addrspace(5) %alloca, align 8190 %tmp = load <2 x ptr addrspace(3)>, ptr addrspace(5) %alloca, align 8191 %tmp.full = load <4 x ptr addrspace(3)>, ptr addrspace(5) %alloca, align 8192 ret void193}194 195; Will not vectorize because we're accessing a 64 bit vector with a 32 bits pointer.196define ptr addrspace(3) @alloca_load_store_ptr_mixed_full_ivec(ptr addrspace(3) %arg) {197; CHECK-LABEL: define ptr addrspace(3) @alloca_load_store_ptr_mixed_full_ivec198; CHECK-SAME: (ptr addrspace(3) [[ARG:%.*]]) {199; CHECK-NEXT: entry:200; CHECK-NEXT: [[ALLOCA:%.*]] = alloca [8 x i8], align 8, addrspace(5)201; CHECK-NEXT: store ptr addrspace(3) [[ARG]], ptr addrspace(5) [[ALLOCA]], align 8202; CHECK-NEXT: [[TMP:%.*]] = load ptr addrspace(3), ptr addrspace(5) [[ALLOCA]], align 8203; CHECK-NEXT: ret ptr addrspace(3) [[TMP]]204;205entry:206 %alloca = alloca [8 x i8], align 8, addrspace(5)207 store ptr addrspace(3) %arg, ptr addrspace(5) %alloca, align 8208 %tmp = load ptr addrspace(3), ptr addrspace(5) %alloca, align 8209 ret ptr addrspace(3) %tmp210}211