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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-promote-alloca -disable-promote-alloca-to-lds=1 -amdgpu-promote-alloca-to-vector-max-regs=16 < %s | FileCheck --check-prefix=BASE --check-prefix=MAX16 %s3; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-promote-alloca -disable-promote-alloca-to-lds=1 -amdgpu-promote-alloca-to-vector-max-regs=24 < %s | FileCheck --check-prefix=BASE %s --check-prefix=MAX244; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-promote-alloca -disable-promote-alloca-to-lds=1 < %s | FileCheck --check-prefix=BASE %s --check-prefix=DEFAULT5 6define amdgpu_kernel void @i32_24_elements(ptr %out) #0 {7; MAX16-LABEL: define amdgpu_kernel void @i32_24_elements(8; MAX16-SAME: ptr [[OUT:%.*]]) #[[ATTR0:[0-9]+]] {9; MAX16-NEXT: [[X:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()10; MAX16-NEXT: [[Y:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.y()11; MAX16-NEXT: [[C1:%.*]] = icmp uge i32 [[X]], 312; MAX16-NEXT: [[C2:%.*]] = icmp uge i32 [[Y]], 313; MAX16-NEXT: [[SEL1:%.*]] = select i1 [[C1]], i32 1, i32 214; MAX16-NEXT: [[SEL2:%.*]] = select i1 [[C2]], i32 0, i32 [[SEL1]]15; MAX16-NEXT: [[ALLOCA:%.*]] = alloca [24 x i32], align 16, addrspace(5)16; MAX16-NEXT: call void @llvm.memset.p5.i32(ptr addrspace(5) [[ALLOCA]], i8 0, i32 96, i1 false)17; MAX16-NEXT: [[GEP_0:%.*]] = getelementptr inbounds [24 x i32], ptr addrspace(5) [[ALLOCA]], i32 0, i32 018; MAX16-NEXT: [[GEP_1:%.*]] = getelementptr inbounds [24 x i32], ptr addrspace(5) [[ALLOCA]], i32 0, i32 2019; MAX16-NEXT: store i32 42, ptr addrspace(5) [[GEP_0]], align 420; MAX16-NEXT: store i32 43, ptr addrspace(5) [[GEP_1]], align 421; MAX16-NEXT: [[GEP:%.*]] = getelementptr inbounds [24 x i32], ptr addrspace(5) [[ALLOCA]], i32 0, i32 [[SEL2]]22; MAX16-NEXT: [[LOAD:%.*]] = load i32, ptr addrspace(5) [[GEP]], align 423; MAX16-NEXT: store i32 [[LOAD]], ptr [[OUT]], align 424; MAX16-NEXT: ret void25;26; MAX24-LABEL: define amdgpu_kernel void @i32_24_elements(27; MAX24-SAME: ptr [[OUT:%.*]]) #[[ATTR0:[0-9]+]] {28; MAX24-NEXT: [[X:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()29; MAX24-NEXT: [[Y:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.y()30; MAX24-NEXT: [[C1:%.*]] = icmp uge i32 [[X]], 331; MAX24-NEXT: [[C2:%.*]] = icmp uge i32 [[Y]], 332; MAX24-NEXT: [[SEL1:%.*]] = select i1 [[C1]], i32 1, i32 233; MAX24-NEXT: [[SEL2:%.*]] = select i1 [[C2]], i32 0, i32 [[SEL1]]34; MAX24-NEXT: [[ALLOCA:%.*]] = freeze <24 x i32> poison35; MAX24-NEXT: [[TMP1:%.*]] = extractelement <24 x i32> <i32 42, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 43, i32 0, i32 0, i32 0>, i32 [[SEL2]]36; MAX24-NEXT: store i32 [[TMP1]], ptr [[OUT]], align 437; MAX24-NEXT: ret void38;39; DEFAULT-LABEL: define amdgpu_kernel void @i32_24_elements(40; DEFAULT-SAME: ptr [[OUT:%.*]]) #[[ATTR0:[0-9]+]] {41; DEFAULT-NEXT: [[X:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()42; DEFAULT-NEXT: [[Y:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.y()43; DEFAULT-NEXT: [[C1:%.*]] = icmp uge i32 [[X]], 344; DEFAULT-NEXT: [[C2:%.*]] = icmp uge i32 [[Y]], 345; DEFAULT-NEXT: [[SEL1:%.*]] = select i1 [[C1]], i32 1, i32 246; DEFAULT-NEXT: [[SEL2:%.*]] = select i1 [[C2]], i32 0, i32 [[SEL1]]47; DEFAULT-NEXT: [[ALLOCA:%.*]] = alloca [24 x i32], align 16, addrspace(5)48; DEFAULT-NEXT: call void @llvm.memset.p5.i32(ptr addrspace(5) [[ALLOCA]], i8 0, i32 96, i1 false)49; DEFAULT-NEXT: [[GEP_0:%.*]] = getelementptr inbounds [24 x i32], ptr addrspace(5) [[ALLOCA]], i32 0, i32 050; DEFAULT-NEXT: [[GEP_1:%.*]] = getelementptr inbounds [24 x i32], ptr addrspace(5) [[ALLOCA]], i32 0, i32 2051; DEFAULT-NEXT: store i32 42, ptr addrspace(5) [[GEP_0]], align 452; DEFAULT-NEXT: store i32 43, ptr addrspace(5) [[GEP_1]], align 453; DEFAULT-NEXT: [[GEP:%.*]] = getelementptr inbounds [24 x i32], ptr addrspace(5) [[ALLOCA]], i32 0, i32 [[SEL2]]54; DEFAULT-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(5) [[GEP]], align 455; DEFAULT-NEXT: store i32 [[TMP1]], ptr [[OUT]], align 456; DEFAULT-NEXT: ret void57;58 %x = tail call i32 @llvm.amdgcn.workitem.id.x()59 %y = tail call i32 @llvm.amdgcn.workitem.id.y()60 %c1 = icmp uge i32 %x, 361 %c2 = icmp uge i32 %y, 362 %sel1 = select i1 %c1, i32 1, i32 263 %sel2 = select i1 %c2, i32 0, i32 %sel164 %alloca = alloca [24 x i32], align 16, addrspace(5)65 call void @llvm.memset.p5.i32(ptr addrspace(5) %alloca, i8 0, i32 96, i1 false)66 %gep.0 = getelementptr inbounds [24 x i32], ptr addrspace(5) %alloca, i32 0, i32 067 %gep.1 = getelementptr inbounds [24 x i32], ptr addrspace(5) %alloca, i32 0, i32 2068 store i32 42, ptr addrspace(5) %gep.069 store i32 43, ptr addrspace(5) %gep.170 %gep = getelementptr inbounds [24 x i32], ptr addrspace(5) %alloca, i32 0, i32 %sel271 %load = load i32, ptr addrspace(5) %gep72 store i32 %load, ptr %out73 ret void74}75 76define amdgpu_kernel void @i32_24_elements_attrib(ptr %out) #1 {77; MAX16-LABEL: define amdgpu_kernel void @i32_24_elements_attrib(78; MAX16-SAME: ptr [[OUT:%.*]]) #[[ATTR1:[0-9]+]] {79; MAX16-NEXT: [[X:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()80; MAX16-NEXT: [[Y:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.y()81; MAX16-NEXT: [[C1:%.*]] = icmp uge i32 [[X]], 382; MAX16-NEXT: [[C2:%.*]] = icmp uge i32 [[Y]], 383; MAX16-NEXT: [[SEL1:%.*]] = select i1 [[C1]], i32 1, i32 284; MAX16-NEXT: [[SEL2:%.*]] = select i1 [[C2]], i32 0, i32 [[SEL1]]85; MAX16-NEXT: [[ALLOCA:%.*]] = alloca [24 x i32], align 16, addrspace(5)86; MAX16-NEXT: call void @llvm.memset.p5.i32(ptr addrspace(5) [[ALLOCA]], i8 0, i32 96, i1 false)87; MAX16-NEXT: [[GEP_0:%.*]] = getelementptr inbounds [24 x i32], ptr addrspace(5) [[ALLOCA]], i32 0, i32 088; MAX16-NEXT: [[GEP_1:%.*]] = getelementptr inbounds [24 x i32], ptr addrspace(5) [[ALLOCA]], i32 0, i32 2089; MAX16-NEXT: store i32 42, ptr addrspace(5) [[GEP_0]], align 490; MAX16-NEXT: store i32 43, ptr addrspace(5) [[GEP_1]], align 491; MAX16-NEXT: [[GEP:%.*]] = getelementptr inbounds [24 x i32], ptr addrspace(5) [[ALLOCA]], i32 0, i32 [[SEL2]]92; MAX16-NEXT: [[LOAD:%.*]] = load i32, ptr addrspace(5) [[GEP]], align 493; MAX16-NEXT: store i32 [[LOAD]], ptr [[OUT]], align 494; MAX16-NEXT: ret void95;96; MAX24-LABEL: define amdgpu_kernel void @i32_24_elements_attrib(97; MAX24-SAME: ptr [[OUT:%.*]]) #[[ATTR1:[0-9]+]] {98; MAX24-NEXT: [[X:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()99; MAX24-NEXT: [[Y:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.y()100; MAX24-NEXT: [[C1:%.*]] = icmp uge i32 [[X]], 3101; MAX24-NEXT: [[C2:%.*]] = icmp uge i32 [[Y]], 3102; MAX24-NEXT: [[SEL1:%.*]] = select i1 [[C1]], i32 1, i32 2103; MAX24-NEXT: [[SEL2:%.*]] = select i1 [[C2]], i32 0, i32 [[SEL1]]104; MAX24-NEXT: [[ALLOCA:%.*]] = freeze <24 x i32> poison105; MAX24-NEXT: [[TMP1:%.*]] = extractelement <24 x i32> <i32 42, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 43, i32 0, i32 0, i32 0>, i32 [[SEL2]]106; MAX24-NEXT: store i32 [[TMP1]], ptr [[OUT]], align 4107; MAX24-NEXT: ret void108;109; DEFAULT-LABEL: define amdgpu_kernel void @i32_24_elements_attrib(110; DEFAULT-SAME: ptr [[OUT:%.*]]) #[[ATTR1:[0-9]+]] {111; DEFAULT-NEXT: [[X:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()112; DEFAULT-NEXT: [[Y:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.y()113; DEFAULT-NEXT: [[C1:%.*]] = icmp uge i32 [[X]], 3114; DEFAULT-NEXT: [[C2:%.*]] = icmp uge i32 [[Y]], 3115; DEFAULT-NEXT: [[SEL1:%.*]] = select i1 [[C1]], i32 1, i32 2116; DEFAULT-NEXT: [[SEL2:%.*]] = select i1 [[C2]], i32 0, i32 [[SEL1]]117; DEFAULT-NEXT: [[ALLOCA:%.*]] = freeze <24 x i32> poison118; DEFAULT-NEXT: [[TMP1:%.*]] = extractelement <24 x i32> <i32 42, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 43, i32 0, i32 0, i32 0>, i32 [[SEL2]]119; DEFAULT-NEXT: store i32 [[TMP1]], ptr [[OUT]], align 4120; DEFAULT-NEXT: ret void121;122 %x = tail call i32 @llvm.amdgcn.workitem.id.x()123 %y = tail call i32 @llvm.amdgcn.workitem.id.y()124 %c1 = icmp uge i32 %x, 3125 %c2 = icmp uge i32 %y, 3126 %sel1 = select i1 %c1, i32 1, i32 2127 %sel2 = select i1 %c2, i32 0, i32 %sel1128 %alloca = alloca [24 x i32], align 16, addrspace(5)129 call void @llvm.memset.p5.i32(ptr addrspace(5) %alloca, i8 0, i32 96, i1 false)130 %gep.0 = getelementptr inbounds [24 x i32], ptr addrspace(5) %alloca, i32 0, i32 0131 %gep.1 = getelementptr inbounds [24 x i32], ptr addrspace(5) %alloca, i32 0, i32 20132 store i32 42, ptr addrspace(5) %gep.0133 store i32 43, ptr addrspace(5) %gep.1134 %gep = getelementptr inbounds [24 x i32], ptr addrspace(5) %alloca, i32 0, i32 %sel2135 %load = load i32, ptr addrspace(5) %gep136 store i32 %load, ptr %out137 ret void138}139 140define amdgpu_kernel void @i32_32_elements(ptr %out) #0 {141; BASE-LABEL: define amdgpu_kernel void @i32_32_elements(142; BASE-SAME: ptr [[OUT:%.*]]) #[[ATTR0:[0-9]+]] {143; BASE-NEXT: [[X:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()144; BASE-NEXT: [[Y:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.y()145; BASE-NEXT: [[C1:%.*]] = icmp uge i32 [[X]], 3146; BASE-NEXT: [[C2:%.*]] = icmp uge i32 [[Y]], 3147; BASE-NEXT: [[SEL1:%.*]] = select i1 [[C1]], i32 1, i32 2148; BASE-NEXT: [[SEL2:%.*]] = select i1 [[C2]], i32 0, i32 [[SEL1]]149; BASE-NEXT: [[ALLOCA:%.*]] = alloca [32 x i32], align 16, addrspace(5)150; BASE-NEXT: call void @llvm.memset.p5.i32(ptr addrspace(5) [[ALLOCA]], i8 0, i32 128, i1 false)151; BASE-NEXT: [[GEP_0:%.*]] = getelementptr inbounds [32 x i32], ptr addrspace(5) [[ALLOCA]], i32 0, i32 0152; BASE-NEXT: [[GEP_1:%.*]] = getelementptr inbounds [32 x i32], ptr addrspace(5) [[ALLOCA]], i32 0, i32 30153; BASE-NEXT: store i32 42, ptr addrspace(5) [[GEP_0]], align 4154; BASE-NEXT: store i32 43, ptr addrspace(5) [[GEP_1]], align 4155; BASE-NEXT: [[GEP:%.*]] = getelementptr inbounds [32 x i32], ptr addrspace(5) [[ALLOCA]], i32 0, i32 [[SEL2]]156; BASE-NEXT: [[LOAD:%.*]] = load i32, ptr addrspace(5) [[GEP]], align 4157; BASE-NEXT: store i32 [[LOAD]], ptr [[OUT]], align 4158; BASE-NEXT: ret void159;160 %x = tail call i32 @llvm.amdgcn.workitem.id.x()161 %y = tail call i32 @llvm.amdgcn.workitem.id.y()162 %c1 = icmp uge i32 %x, 3163 %c2 = icmp uge i32 %y, 3164 %sel1 = select i1 %c1, i32 1, i32 2165 %sel2 = select i1 %c2, i32 0, i32 %sel1166 %alloca = alloca [32 x i32], align 16, addrspace(5)167 call void @llvm.memset.p5.i32(ptr addrspace(5) %alloca, i8 0, i32 128, i1 false)168 %gep.0 = getelementptr inbounds [32 x i32], ptr addrspace(5) %alloca, i32 0, i32 0169 %gep.1 = getelementptr inbounds [32 x i32], ptr addrspace(5) %alloca, i32 0, i32 30170 store i32 42, ptr addrspace(5) %gep.0171 store i32 43, ptr addrspace(5) %gep.1172 %gep = getelementptr inbounds [32 x i32], ptr addrspace(5) %alloca, i32 0, i32 %sel2173 %load = load i32, ptr addrspace(5) %gep174 store i32 %load, ptr %out175 ret void176}177 178define amdgpu_kernel void @i32_32_elements_attrib(ptr %out) #2 {179; MAX16-LABEL: define amdgpu_kernel void @i32_32_elements_attrib(180; MAX16-SAME: ptr [[OUT:%.*]]) #[[ATTR2:[0-9]+]] {181; MAX16-NEXT: [[X:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()182; MAX16-NEXT: [[Y:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.y()183; MAX16-NEXT: [[C1:%.*]] = icmp uge i32 [[X]], 3184; MAX16-NEXT: [[C2:%.*]] = icmp uge i32 [[Y]], 3185; MAX16-NEXT: [[SEL1:%.*]] = select i1 [[C1]], i32 1, i32 2186; MAX16-NEXT: [[SEL2:%.*]] = select i1 [[C2]], i32 0, i32 [[SEL1]]187; MAX16-NEXT: [[ALLOCA:%.*]] = alloca [32 x i32], align 16, addrspace(5)188; MAX16-NEXT: call void @llvm.memset.p5.i32(ptr addrspace(5) [[ALLOCA]], i8 0, i32 128, i1 false)189; MAX16-NEXT: [[GEP_0:%.*]] = getelementptr inbounds [32 x i32], ptr addrspace(5) [[ALLOCA]], i32 0, i32 0190; MAX16-NEXT: [[GEP_1:%.*]] = getelementptr inbounds [32 x i32], ptr addrspace(5) [[ALLOCA]], i32 0, i32 30191; MAX16-NEXT: store i32 42, ptr addrspace(5) [[GEP_0]], align 4192; MAX16-NEXT: store i32 43, ptr addrspace(5) [[GEP_1]], align 4193; MAX16-NEXT: [[GEP:%.*]] = getelementptr inbounds [32 x i32], ptr addrspace(5) [[ALLOCA]], i32 0, i32 [[SEL2]]194; MAX16-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(5) [[GEP]], align 4195; MAX16-NEXT: store i32 [[TMP1]], ptr [[OUT]], align 4196; MAX16-NEXT: ret void197;198; MAX24-LABEL: define amdgpu_kernel void @i32_32_elements_attrib(199; MAX24-SAME: ptr [[OUT:%.*]]) #[[ATTR2:[0-9]+]] {200; MAX24-NEXT: [[X:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()201; MAX24-NEXT: [[Y:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.y()202; MAX24-NEXT: [[C1:%.*]] = icmp uge i32 [[X]], 3203; MAX24-NEXT: [[C2:%.*]] = icmp uge i32 [[Y]], 3204; MAX24-NEXT: [[SEL1:%.*]] = select i1 [[C1]], i32 1, i32 2205; MAX24-NEXT: [[SEL2:%.*]] = select i1 [[C2]], i32 0, i32 [[SEL1]]206; MAX24-NEXT: [[ALLOCA:%.*]] = alloca [32 x i32], align 16, addrspace(5)207; MAX24-NEXT: call void @llvm.memset.p5.i32(ptr addrspace(5) [[ALLOCA]], i8 0, i32 128, i1 false)208; MAX24-NEXT: [[GEP_0:%.*]] = getelementptr inbounds [32 x i32], ptr addrspace(5) [[ALLOCA]], i32 0, i32 0209; MAX24-NEXT: [[GEP_1:%.*]] = getelementptr inbounds [32 x i32], ptr addrspace(5) [[ALLOCA]], i32 0, i32 30210; MAX24-NEXT: store i32 42, ptr addrspace(5) [[GEP_0]], align 4211; MAX24-NEXT: store i32 43, ptr addrspace(5) [[GEP_1]], align 4212; MAX24-NEXT: [[GEP:%.*]] = getelementptr inbounds [32 x i32], ptr addrspace(5) [[ALLOCA]], i32 0, i32 [[SEL2]]213; MAX24-NEXT: [[LOAD:%.*]] = load i32, ptr addrspace(5) [[GEP]], align 4214; MAX24-NEXT: store i32 [[LOAD]], ptr [[OUT]], align 4215; MAX24-NEXT: ret void216;217; DEFAULT-LABEL: define amdgpu_kernel void @i32_32_elements_attrib(218; DEFAULT-SAME: ptr [[OUT:%.*]]) #[[ATTR2:[0-9]+]] {219; DEFAULT-NEXT: [[X:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()220; DEFAULT-NEXT: [[Y:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.y()221; DEFAULT-NEXT: [[C1:%.*]] = icmp uge i32 [[X]], 3222; DEFAULT-NEXT: [[C2:%.*]] = icmp uge i32 [[Y]], 3223; DEFAULT-NEXT: [[SEL1:%.*]] = select i1 [[C1]], i32 1, i32 2224; DEFAULT-NEXT: [[SEL2:%.*]] = select i1 [[C2]], i32 0, i32 [[SEL1]]225; DEFAULT-NEXT: [[ALLOCA:%.*]] = freeze <32 x i32> poison226; DEFAULT-NEXT: [[TMP1:%.*]] = extractelement <32 x i32> <i32 42, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 43, i32 0>, i32 [[SEL2]]227; DEFAULT-NEXT: store i32 [[TMP1]], ptr [[OUT]], align 4228; DEFAULT-NEXT: ret void229;230 %x = tail call i32 @llvm.amdgcn.workitem.id.x()231 %y = tail call i32 @llvm.amdgcn.workitem.id.y()232 %c1 = icmp uge i32 %x, 3233 %c2 = icmp uge i32 %y, 3234 %sel1 = select i1 %c1, i32 1, i32 2235 %sel2 = select i1 %c2, i32 0, i32 %sel1236 %alloca = alloca [32 x i32], align 16, addrspace(5)237 call void @llvm.memset.p5.i32(ptr addrspace(5) %alloca, i8 0, i32 128, i1 false)238 %gep.0 = getelementptr inbounds [32 x i32], ptr addrspace(5) %alloca, i32 0, i32 0239 %gep.1 = getelementptr inbounds [32 x i32], ptr addrspace(5) %alloca, i32 0, i32 30240 store i32 42, ptr addrspace(5) %gep.0241 store i32 43, ptr addrspace(5) %gep.1242 %gep = getelementptr inbounds [32 x i32], ptr addrspace(5) %alloca, i32 0, i32 %sel2243 %load = load i32, ptr addrspace(5) %gep244 store i32 %load, ptr %out245 ret void246}247 248declare i32 @llvm.amdgcn.workitem.id.x()249declare i32 @llvm.amdgcn.workitem.id.y()250declare void @llvm.memset.p5.i32(ptr addrspace(5) nocapture writeonly, i8, i32, i1 immarg)251 252attributes #0 = { nounwind "amdgpu-flat-work-group-size"="64,64" "amdgpu-waves-per-eu"="1,3" "amdgpu-promote-alloca-to-vector-max-regs"="16" }253attributes #1 = { nounwind "amdgpu-flat-work-group-size"="64,64" "amdgpu-waves-per-eu"="1,3" "amdgpu-promote-alloca-to-vector-max-regs"="24" }254attributes #2 = { nounwind "amdgpu-flat-work-group-size"="64,64" "amdgpu-waves-per-eu"="1,3" }255