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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -S -mtriple=amdgcn-unknown-amdhsa -passes=amdgpu-promote-alloca < %s | FileCheck %s3 4; Checks that memsets don't block PromoteAlloca.5 6define amdgpu_kernel void @memset_all_zero(i64 %val) {7; CHECK-LABEL: @memset_all_zero(8; CHECK-NEXT: entry:9; CHECK-NEXT: [[STACK:%.*]] = freeze <6 x i64> poison10; CHECK-NEXT: [[TMP0:%.*]] = insertelement <6 x i64> zeroinitializer, i64 [[VAL:%.*]], i32 011; CHECK-NEXT: [[TMP1:%.*]] = insertelement <6 x i64> [[TMP0]], i64 [[VAL]], i32 112; CHECK-NEXT: ret void13;14entry:15 %stack = alloca [6 x i64], align 4, addrspace(5)16 call void @llvm.memset.p5.i64(ptr addrspace(5) %stack, i8 0, i64 48, i1 false)17 store i64 %val, ptr addrspace(5) %stack18 %reload = load i64, ptr addrspace(5) %stack19 %stack.1 = getelementptr [6 x i64], ptr addrspace(5) %stack, i64 0, i64 120 store i64 %val, ptr addrspace(5) %stack.121 ret void22}23 24define amdgpu_kernel void @memset_all_5(i64 %val) {25; CHECK-LABEL: @memset_all_5(26; CHECK-NEXT: entry:27; CHECK-NEXT: [[STACK:%.*]] = freeze <4 x i64> poison28; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i64> splat (i64 361700864190383365), i64 [[VAL:%.*]], i32 029; CHECK-NEXT: [[TMP1:%.*]] = insertelement <4 x i64> [[TMP0]], i64 [[VAL]], i32 130; CHECK-NEXT: ret void31;32entry:33 %stack = alloca [4 x i64], align 4, addrspace(5)34 call void @llvm.memset.p5.i64(ptr addrspace(5) %stack, i8 5, i64 32, i1 false)35 store i64 %val, ptr addrspace(5) %stack36 %reload = load i64, ptr addrspace(5) %stack37 %stack.1 = getelementptr [6 x i64], ptr addrspace(5) %stack, i64 0, i64 138 store i64 %val, ptr addrspace(5) %stack.139 ret void40}41 42define amdgpu_kernel void @memset_volatile_nopromote(i64 %val) {43; CHECK-LABEL: @memset_volatile_nopromote(44; CHECK-NEXT: entry:45; CHECK-NEXT: [[STACK:%.*]] = alloca [4 x i64], align 4, addrspace(5)46; CHECK-NEXT: call void @llvm.memset.p5.i64(ptr addrspace(5) [[STACK]], i8 0, i64 32, i1 true)47; CHECK-NEXT: store i64 [[VAL:%.*]], ptr addrspace(5) [[STACK]], align 848; CHECK-NEXT: ret void49;50entry:51 %stack = alloca [4 x i64], align 4, addrspace(5)52 call void @llvm.memset.p5.i64(ptr addrspace(5) %stack, i8 0, i64 32, i1 true)53 store i64 %val, ptr addrspace(5) %stack54 ret void55}56 57define amdgpu_kernel void @memset_badsize_nopromote(i64 %val) {58; CHECK-LABEL: @memset_badsize_nopromote(59; CHECK-NEXT: entry:60; CHECK-NEXT: [[STACK:%.*]] = alloca [4 x i64], align 4, addrspace(5)61; CHECK-NEXT: call void @llvm.memset.p5.i64(ptr addrspace(5) [[STACK]], i8 0, i64 31, i1 true)62; CHECK-NEXT: store i64 [[VAL:%.*]], ptr addrspace(5) [[STACK]], align 863; CHECK-NEXT: ret void64;65entry:66 %stack = alloca [4 x i64], align 4, addrspace(5)67 call void @llvm.memset.p5.i64(ptr addrspace(5) %stack, i8 0, i64 31, i1 true)68 store i64 %val, ptr addrspace(5) %stack69 ret void70}71 72define amdgpu_kernel void @memset_offset_ptr_nopromote(i64 %val) {73; CHECK-LABEL: @memset_offset_ptr_nopromote(74; CHECK-NEXT: entry:75; CHECK-NEXT: [[STACK:%.*]] = alloca [4 x i64], align 4, addrspace(5)76; CHECK-NEXT: [[GEP:%.*]] = getelementptr [4 x i64], ptr addrspace(5) [[STACK]], i64 0, i64 177; CHECK-NEXT: call void @llvm.memset.p5.i64(ptr addrspace(5) [[GEP]], i8 0, i64 24, i1 true)78; CHECK-NEXT: store i64 [[VAL:%.*]], ptr addrspace(5) [[STACK]], align 879; CHECK-NEXT: ret void80;81entry:82 %stack = alloca [4 x i64], align 4, addrspace(5)83 %gep = getelementptr [4 x i64], ptr addrspace(5) %stack, i64 0, i64 184 call void @llvm.memset.p5.i64(ptr addrspace(5) %gep, i8 0, i64 24, i1 true)85 store i64 %val, ptr addrspace(5) %stack86 ret void87}88 89define amdgpu_kernel void @memset_array_ptr_alloca(ptr %out) {90; CHECK-LABEL: @memset_array_ptr_alloca(91; CHECK-NEXT: [[ALLOCA:%.*]] = freeze <6 x ptr> poison92; CHECK-NEXT: store i64 0, ptr [[OUT:%.*]], align 893; CHECK-NEXT: ret void94;95 %alloca = alloca [6 x ptr], align 16, addrspace(5)96 call void @llvm.memset.p5.i64(ptr addrspace(5) %alloca, i8 0, i64 48, i1 false)97 %load = load i64, ptr addrspace(5) %alloca98 store i64 %load, ptr %out99 ret void100}101 102define amdgpu_kernel void @memset_vector_ptr_alloca(ptr %out) {103; CHECK-LABEL: @memset_vector_ptr_alloca(104; CHECK-NEXT: [[ALLOCA:%.*]] = freeze <6 x ptr> poison105; CHECK-NEXT: store i64 0, ptr [[OUT:%.*]], align 8106; CHECK-NEXT: ret void107;108 %alloca = alloca <6 x ptr>, align 16, addrspace(5)109 call void @llvm.memset.p5.i64(ptr addrspace(5) %alloca, i8 0, i64 48, i1 false)110 %load = load i64, ptr addrspace(5) %alloca111 store i64 %load, ptr %out112 ret void113}114 115define amdgpu_kernel void @memset_array_of_array_ptr_alloca(ptr %out) {116; CHECK-LABEL: @memset_array_of_array_ptr_alloca(117; CHECK-NEXT: [[ALLOCA:%.*]] = freeze <6 x ptr> poison118; CHECK-NEXT: store i64 0, ptr [[OUT:%.*]], align 8119; CHECK-NEXT: ret void120;121 %alloca = alloca [2 x [3 x ptr]], align 16, addrspace(5)122 call void @llvm.memset.p5.i64(ptr addrspace(5) %alloca, i8 0, i64 48, i1 false)123 %load = load i64, ptr addrspace(5) %alloca124 store i64 %load, ptr %out125 ret void126}127 128define amdgpu_kernel void @memset_array_of_vec_ptr_alloca(ptr %out) {129; CHECK-LABEL: @memset_array_of_vec_ptr_alloca(130; CHECK-NEXT: [[ALLOCA:%.*]] = freeze <8 x ptr> poison131; CHECK-NEXT: store i64 0, ptr [[OUT:%.*]], align 8132; CHECK-NEXT: ret void133;134 %alloca = alloca [2 x <3 x ptr>], align 16, addrspace(5)135 call void @llvm.memset.p5.i64(ptr addrspace(5) %alloca, i8 0, i64 64, i1 false)136 %load = load i64, ptr addrspace(5) %alloca137 store i64 %load, ptr %out138 ret void139}140 141declare void @llvm.memset.p5.i64(ptr addrspace(5) nocapture writeonly, i8, i64, i1 immarg)142