573 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-promote-alloca -disable-promote-alloca-to-lds=1 < %s | FileCheck %s3 4define amdgpu_kernel void @i32_2d_load_store(ptr %out) {5; CHECK-LABEL: define amdgpu_kernel void @i32_2d_load_store(6; CHECK-SAME: ptr [[OUT:%.*]]) {7; CHECK-NEXT: [[ALLOCA:%.*]] = freeze <6 x i32> poison8; CHECK-NEXT: [[TMP1:%.*]] = insertelement <6 x i32> [[ALLOCA]], i32 0, i32 09; CHECK-NEXT: [[TMP2:%.*]] = insertelement <6 x i32> [[TMP1]], i32 1, i32 110; CHECK-NEXT: [[TMP3:%.*]] = insertelement <6 x i32> [[TMP2]], i32 2, i32 211; CHECK-NEXT: [[TMP4:%.*]] = insertelement <6 x i32> [[TMP3]], i32 3, i32 312; CHECK-NEXT: [[TMP5:%.*]] = insertelement <6 x i32> [[TMP4]], i32 4, i32 413; CHECK-NEXT: [[TMP6:%.*]] = insertelement <6 x i32> [[TMP5]], i32 5, i32 514; CHECK-NEXT: store i32 3, ptr [[OUT]], align 415; CHECK-NEXT: ret void16;17 %alloca = alloca [2 x [3 x i32]], align 16, addrspace(5)18 %gep.00 = getelementptr inbounds [2 x [3 x i32]], ptr addrspace(5) %alloca, i32 0, i32 0, i32 019 %gep.01 = getelementptr inbounds [2 x [3 x i32]], ptr addrspace(5) %alloca, i32 0, i32 0, i32 120 %gep.02 = getelementptr inbounds [2 x [3 x i32]], ptr addrspace(5) %alloca, i32 0, i32 0, i32 221 %gep.10 = getelementptr inbounds [2 x [3 x i32]], ptr addrspace(5) %alloca, i32 0, i32 1, i32 022 %gep.11 = getelementptr inbounds [2 x [3 x i32]], ptr addrspace(5) %alloca, i32 0, i32 1, i32 123 %gep.12 = getelementptr inbounds [2 x [3 x i32]], ptr addrspace(5) %alloca, i32 0, i32 1, i32 224 store i32 0, ptr addrspace(5) %gep.0025 store i32 1, ptr addrspace(5) %gep.0126 store i32 2, ptr addrspace(5) %gep.0227 store i32 3, ptr addrspace(5) %gep.1028 store i32 4, ptr addrspace(5) %gep.1129 store i32 5, ptr addrspace(5) %gep.1230 %gep = getelementptr inbounds [2 x [3 x i32]], ptr addrspace(5) %alloca, i32 0, i32 131 %load = load i32, ptr addrspace(5) %gep32 store i32 %load, ptr %out33 ret void34}35 36define amdgpu_kernel void @i64_2d_load_store(ptr %out) {37; CHECK-LABEL: define amdgpu_kernel void @i64_2d_load_store(38; CHECK-SAME: ptr [[OUT:%.*]]) {39; CHECK-NEXT: [[ALLOCA:%.*]] = freeze <6 x i64> poison40; CHECK-NEXT: [[TMP1:%.*]] = insertelement <6 x i64> [[ALLOCA]], i64 0, i32 041; CHECK-NEXT: [[TMP2:%.*]] = insertelement <6 x i64> [[TMP1]], i64 1, i32 142; CHECK-NEXT: [[TMP3:%.*]] = insertelement <6 x i64> [[TMP2]], i64 2, i32 243; CHECK-NEXT: [[TMP4:%.*]] = insertelement <6 x i64> [[TMP3]], i64 3, i32 344; CHECK-NEXT: [[TMP5:%.*]] = insertelement <6 x i64> [[TMP4]], i64 4, i32 445; CHECK-NEXT: [[TMP6:%.*]] = insertelement <6 x i64> [[TMP5]], i64 5, i32 546; CHECK-NEXT: store i64 3, ptr [[OUT]], align 847; CHECK-NEXT: ret void48;49 %alloca = alloca [2 x [3 x i64]], align 16, addrspace(5)50 %gep.00 = getelementptr inbounds [2 x [3 x i64]], ptr addrspace(5) %alloca, i32 0, i32 0, i32 051 %gep.01 = getelementptr inbounds [2 x [3 x i64]], ptr addrspace(5) %alloca, i32 0, i32 0, i32 152 %gep.02 = getelementptr inbounds [2 x [3 x i64]], ptr addrspace(5) %alloca, i32 0, i32 0, i32 253 %gep.10 = getelementptr inbounds [2 x [3 x i64]], ptr addrspace(5) %alloca, i32 0, i32 1, i32 054 %gep.11 = getelementptr inbounds [2 x [3 x i64]], ptr addrspace(5) %alloca, i32 0, i32 1, i32 155 %gep.12 = getelementptr inbounds [2 x [3 x i64]], ptr addrspace(5) %alloca, i32 0, i32 1, i32 256 store i64 0, ptr addrspace(5) %gep.0057 store i64 1, ptr addrspace(5) %gep.0158 store i64 2, ptr addrspace(5) %gep.0259 store i64 3, ptr addrspace(5) %gep.1060 store i64 4, ptr addrspace(5) %gep.1161 store i64 5, ptr addrspace(5) %gep.1262 %gep = getelementptr inbounds [2 x [3 x i64]], ptr addrspace(5) %alloca, i32 0, i32 163 %load = load i64, ptr addrspace(5) %gep64 store i64 %load, ptr %out65 ret void66}67 68define amdgpu_kernel void @i32_2d_alloca_store_partial(ptr addrspace(1) %out, ptr addrspace(3) %dummy_lds) {69; CHECK-LABEL: define amdgpu_kernel void @i32_2d_alloca_store_partial(70; CHECK-SAME: ptr addrspace(1) [[OUT:%.*]], ptr addrspace(3) [[DUMMY_LDS:%.*]]) {71; CHECK-NEXT: [[BB:.*:]]72; CHECK-NEXT: [[X:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()73; CHECK-NEXT: [[Y:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.y()74; CHECK-NEXT: [[C1:%.*]] = icmp uge i32 [[X]], 375; CHECK-NEXT: [[C2:%.*]] = icmp uge i32 [[Y]], 376; CHECK-NEXT: [[SEL1:%.*]] = select i1 [[C1]], i32 1, i32 277; CHECK-NEXT: [[SEL2:%.*]] = select i1 [[C2]], i32 0, i32 [[SEL1]]78; CHECK-NEXT: [[ALLOCA:%.*]] = freeze <8 x i32> poison79; CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x i32> [[ALLOCA]], i32 1, i32 080; CHECK-NEXT: [[TMP5:%.*]] = insertelement <8 x i32> [[TMP4]], i32 2, i32 181; CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x i32> [[TMP5]], i32 3, i32 282; CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x i32> [[TMP2]], i32 4, i32 383; CHECK-NEXT: [[TMP0:%.*]] = extractelement <8 x i32> [[TMP3]], i32 [[SEL2]]84; CHECK-NEXT: [[TMP1:%.*]] = bitcast i32 [[TMP0]] to float85; CHECK-NEXT: store float [[TMP1]], ptr addrspace(1) [[OUT]], align 486; CHECK-NEXT: ret void87;88bb:89 %x = tail call i32 @llvm.amdgcn.workitem.id.x()90 %y = tail call i32 @llvm.amdgcn.workitem.id.y()91 %c1 = icmp uge i32 %x, 392 %c2 = icmp uge i32 %y, 393 %sel1 = select i1 %c1, i32 1, i32 294 %sel2 = select i1 %c2, i32 0, i32 %sel195 %alloca = alloca [2 x [4 x i32]], align 4, addrspace(5)96 %gep = getelementptr inbounds <4 x i32>, ptr addrspace(5) %alloca, i32 0, i32 %sel297 store <4 x i32> <i32 1, i32 2, i32 3, i32 4>, ptr addrspace(5) %alloca, align 498 %load = load float, ptr addrspace(5) %gep, align 499 store float %load, ptr addrspace(1) %out, align 4100 ret void101}102 103 104define amdgpu_kernel void @i64_2d_load_store_cast(ptr %out) {105; CHECK-LABEL: define amdgpu_kernel void @i64_2d_load_store_cast(106; CHECK-SAME: ptr [[OUT:%.*]]) {107; CHECK-NEXT: [[X:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()108; CHECK-NEXT: [[Y:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.y()109; CHECK-NEXT: [[C1:%.*]] = icmp uge i32 [[X]], 3110; CHECK-NEXT: [[C2:%.*]] = icmp uge i32 [[Y]], 3111; CHECK-NEXT: [[SEL1:%.*]] = select i1 [[C1]], i32 1, i32 2112; CHECK-NEXT: [[SEL2:%.*]] = select i1 [[C2]], i32 0, i32 [[SEL1]]113; CHECK-NEXT: [[ALLOCA:%.*]] = freeze <6 x i64> poison114; CHECK-NEXT: [[TMP7:%.*]] = insertelement <6 x i64> [[ALLOCA]], i64 0, i32 0115; CHECK-NEXT: [[TMP2:%.*]] = insertelement <6 x i64> [[TMP7]], i64 1, i32 1116; CHECK-NEXT: [[TMP3:%.*]] = insertelement <6 x i64> [[TMP2]], i64 2, i32 2117; CHECK-NEXT: [[TMP4:%.*]] = insertelement <6 x i64> [[TMP3]], i64 3, i32 3118; CHECK-NEXT: [[TMP5:%.*]] = insertelement <6 x i64> [[TMP4]], i64 4, i32 4119; CHECK-NEXT: [[TMP6:%.*]] = insertelement <6 x i64> [[TMP5]], i64 5, i32 5120; CHECK-NEXT: [[TMP1:%.*]] = extractelement <6 x i64> [[TMP6]], i32 [[SEL2]]121; CHECK-NEXT: store i64 [[TMP1]], ptr [[OUT]], align 8122; CHECK-NEXT: ret void123;124 %x = tail call i32 @llvm.amdgcn.workitem.id.x()125 %y = tail call i32 @llvm.amdgcn.workitem.id.y()126 %c1 = icmp uge i32 %x, 3127 %c2 = icmp uge i32 %y, 3128 %sel1 = select i1 %c1, i32 1, i32 2129 %sel2 = select i1 %c2, i32 0, i32 %sel1130 %alloca = alloca [2 x [3 x i64]], align 16, addrspace(5)131 %gep.00 = getelementptr inbounds [2 x [3 x i64]], ptr addrspace(5) %alloca, i32 0, i32 0, i32 0132 %gep.01 = getelementptr inbounds [2 x [3 x i64]], ptr addrspace(5) %alloca, i32 0, i32 0, i32 1133 %gep.02 = getelementptr inbounds [2 x [3 x i64]], ptr addrspace(5) %alloca, i32 0, i32 0, i32 2134 %gep.10 = getelementptr inbounds [2 x [3 x i64]], ptr addrspace(5) %alloca, i32 0, i32 1, i32 0135 %gep.11 = getelementptr inbounds [2 x [3 x i64]], ptr addrspace(5) %alloca, i32 0, i32 1, i32 1136 %gep.12 = getelementptr inbounds [2 x [3 x i64]], ptr addrspace(5) %alloca, i32 0, i32 1, i32 2137 store i64 0, ptr addrspace(5) %gep.00138 store i64 1, ptr addrspace(5) %gep.01139 store i64 2, ptr addrspace(5) %gep.02140 store i64 3, ptr addrspace(5) %gep.10141 store i64 4, ptr addrspace(5) %gep.11142 store i64 5, ptr addrspace(5) %gep.12143 %gep = getelementptr inbounds [6 x i64], ptr addrspace(5) %alloca, i32 0, i32 %sel2144 %load = load i64, ptr addrspace(5) %gep145 store i64 %load, ptr %out146 ret void147}148 149define amdgpu_kernel void @i64_2d_load_store_subvec_1(ptr %out) {150; CHECK-LABEL: define amdgpu_kernel void @i64_2d_load_store_subvec_1(151; CHECK-SAME: ptr [[OUT:%.*]]) {152; CHECK-NEXT: [[ALLOCA:%.*]] = freeze <6 x i64> poison153; CHECK-NEXT: [[TMP1:%.*]] = insertelement <6 x i64> [[ALLOCA]], i64 0, i32 0154; CHECK-NEXT: [[TMP2:%.*]] = insertelement <6 x i64> [[TMP1]], i64 1, i32 1155; CHECK-NEXT: [[TMP3:%.*]] = insertelement <6 x i64> [[TMP2]], i64 2, i32 2156; CHECK-NEXT: [[TMP4:%.*]] = insertelement <6 x i64> [[TMP3]], i64 3, i32 3157; CHECK-NEXT: [[TMP5:%.*]] = insertelement <6 x i64> [[TMP4]], i64 4, i32 4158; CHECK-NEXT: [[TMP6:%.*]] = insertelement <6 x i64> [[TMP5]], i64 5, i32 5159; CHECK-NEXT: [[ELEM:%.*]] = extractelement <3 x i64> <i64 3, i64 4, i64 5>, i32 2160; CHECK-NEXT: store i64 [[ELEM]], ptr [[OUT]], align 8161; CHECK-NEXT: ret void162;163 %alloca = alloca [2 x [3 x i64]], align 16, addrspace(5)164 %gep.00 = getelementptr inbounds [2 x [3 x i64]], ptr addrspace(5) %alloca, i32 0165 %gep.01 = getelementptr inbounds [2 x [3 x i64]], ptr addrspace(5) %alloca, i32 0, i32 1, i32 0166 store <3 x i64> <i64 0, i64 1, i64 2>, ptr addrspace(5) %gep.00167 store <3 x i64> <i64 3, i64 4, i64 5>, ptr addrspace(5) %gep.01168 %gep = getelementptr inbounds [2 x [3 x i64]], ptr addrspace(5) %alloca, i32 0, i32 1169 %load = load <3 x i64>, ptr addrspace(5) %gep170 %elem = extractelement <3 x i64> %load, i32 2171 store i64 %elem, ptr %out172 ret void173}174 175define amdgpu_kernel void @i64_2d_load_store_subvec_2(ptr %out) {176; CHECK-LABEL: define amdgpu_kernel void @i64_2d_load_store_subvec_2(177; CHECK-SAME: ptr [[OUT:%.*]]) {178; CHECK-NEXT: [[ALLOCA:%.*]] = freeze <8 x i64> poison179; CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i64> [[ALLOCA]], i64 0, i32 0180; CHECK-NEXT: [[TMP2:%.*]] = insertelement <8 x i64> [[TMP1]], i64 1, i32 1181; CHECK-NEXT: [[TMP3:%.*]] = insertelement <8 x i64> [[TMP2]], i64 2, i32 2182; CHECK-NEXT: [[TMP4:%.*]] = insertelement <8 x i64> [[TMP3]], i64 3, i32 4183; CHECK-NEXT: [[TMP5:%.*]] = insertelement <8 x i64> [[TMP4]], i64 4, i32 5184; CHECK-NEXT: [[TMP6:%.*]] = insertelement <8 x i64> [[TMP5]], i64 5, i32 6185; CHECK-NEXT: [[ELEM:%.*]] = extractelement <3 x i64> <i64 3, i64 4, i64 5>, i32 2186; CHECK-NEXT: store i64 [[ELEM]], ptr [[OUT]], align 8187; CHECK-NEXT: ret void188;189 %alloca = alloca [2 x <3 x i64>], align 16, addrspace(5)190 %gep.00 = getelementptr inbounds [2 x <3 x i64>], ptr addrspace(5) %alloca, i32 0191 %gep.01 = getelementptr inbounds [2 x <3 x i64>], ptr addrspace(5) %alloca, i32 0, i32 1, i32 0192 store <3 x i64> <i64 0, i64 1, i64 2>, ptr addrspace(5) %gep.00193 store <3 x i64> <i64 3, i64 4, i64 5>, ptr addrspace(5) %gep.01194 %gep = getelementptr inbounds [2 x <3 x i64>], ptr addrspace(5) %alloca, i32 0, i32 1195 %load = load <3 x i64>, ptr addrspace(5) %gep196 %elem = extractelement <3 x i64> %load, i32 2197 store i64 %elem, ptr %out198 ret void199}200 201define amdgpu_kernel void @i64_2d_load_store_subvec_3(ptr %out) {202; CHECK-LABEL: define amdgpu_kernel void @i64_2d_load_store_subvec_3(203; CHECK-SAME: ptr [[OUT:%.*]]) {204; CHECK-NEXT: [[X:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()205; CHECK-NEXT: [[Y:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.y()206; CHECK-NEXT: [[C1:%.*]] = icmp uge i32 [[X]], 3207; CHECK-NEXT: [[C2:%.*]] = icmp uge i32 [[Y]], 3208; CHECK-NEXT: [[SEL1:%.*]] = select i1 [[C1]], i32 1, i32 2209; CHECK-NEXT: [[SEL2:%.*]] = select i1 [[C2]], i32 0, i32 [[SEL1]]210; CHECK-NEXT: [[ALLOCA:%.*]] = freeze <6 x i64> poison211; CHECK-NEXT: [[TMP10:%.*]] = insertelement <6 x i64> [[ALLOCA]], i64 0, i32 0212; CHECK-NEXT: [[TMP11:%.*]] = insertelement <6 x i64> [[TMP10]], i64 1, i32 1213; CHECK-NEXT: [[TMP12:%.*]] = insertelement <6 x i64> [[TMP11]], i64 2, i32 2214; CHECK-NEXT: [[TMP13:%.*]] = insertelement <6 x i64> [[TMP12]], i64 3, i32 3215; CHECK-NEXT: [[TMP14:%.*]] = insertelement <6 x i64> [[TMP13]], i64 4, i32 4216; CHECK-NEXT: [[TMP15:%.*]] = insertelement <6 x i64> [[TMP14]], i64 5, i32 5217; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[SEL2]], 3218; CHECK-NEXT: [[TMP2:%.*]] = extractelement <6 x i64> [[TMP15]], i32 [[TMP1]]219; CHECK-NEXT: [[TMP3:%.*]] = insertelement <3 x i64> poison, i64 [[TMP2]], i64 0220; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[TMP1]], 1221; CHECK-NEXT: [[TMP5:%.*]] = extractelement <6 x i64> [[TMP15]], i32 [[TMP4]]222; CHECK-NEXT: [[TMP6:%.*]] = insertelement <3 x i64> [[TMP3]], i64 [[TMP5]], i64 1223; CHECK-NEXT: [[TMP7:%.*]] = add i32 [[TMP1]], 2224; CHECK-NEXT: [[TMP8:%.*]] = extractelement <6 x i64> [[TMP15]], i32 [[TMP7]]225; CHECK-NEXT: [[TMP9:%.*]] = insertelement <3 x i64> [[TMP6]], i64 [[TMP8]], i64 2226; CHECK-NEXT: [[ELEM:%.*]] = extractelement <3 x i64> [[TMP9]], i32 2227; CHECK-NEXT: store i64 [[ELEM]], ptr [[OUT]], align 8228; CHECK-NEXT: ret void229;230 %x = tail call i32 @llvm.amdgcn.workitem.id.x()231 %y = tail call i32 @llvm.amdgcn.workitem.id.y()232 %c1 = icmp uge i32 %x, 3233 %c2 = icmp uge i32 %y, 3234 %sel1 = select i1 %c1, i32 1, i32 2235 %sel2 = select i1 %c2, i32 0, i32 %sel1236 %alloca = alloca [2 x [3 x i64]], align 16, addrspace(5)237 %gep.00 = getelementptr inbounds [2 x [3 x i64]], ptr addrspace(5) %alloca, i32 0238 %gep.01 = getelementptr inbounds [2 x [3 x i64]], ptr addrspace(5) %alloca, i32 0, i32 1, i32 0239 store <3 x i64> <i64 0, i64 1, i64 2>, ptr addrspace(5) %gep.00240 store <3 x i64> <i64 3, i64 4, i64 5>, ptr addrspace(5) %gep.01241 %gep = getelementptr inbounds [2 x [3 x i64]], ptr addrspace(5) %alloca, i32 0, i32 %sel2242 %load = load <3 x i64>, ptr addrspace(5) %gep243 %elem = extractelement <3 x i64> %load, i32 2244 store i64 %elem, ptr %out245 ret void246}247 248define amdgpu_kernel void @i64_2d_load_store_subvec_3_i64_offset(ptr %out) {249; CHECK-LABEL: define amdgpu_kernel void @i64_2d_load_store_subvec_3_i64_offset(250; CHECK-SAME: ptr [[OUT:%.*]]) {251; CHECK-NEXT: [[X:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()252; CHECK-NEXT: [[Y:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.y()253; CHECK-NEXT: [[C1:%.*]] = icmp uge i32 [[X]], 3254; CHECK-NEXT: [[C2:%.*]] = icmp uge i32 [[Y]], 3255; CHECK-NEXT: [[SEL1:%.*]] = select i1 [[C1]], i32 1, i32 2256; CHECK-NEXT: [[SEL2:%.*]] = select i1 [[C2]], i32 0, i32 [[SEL1]]257; CHECK-NEXT: [[SEL3:%.*]] = zext i32 [[SEL2]] to i64258; CHECK-NEXT: [[ALLOCA:%.*]] = freeze <6 x i64> poison259; CHECK-NEXT: [[TMP10:%.*]] = insertelement <6 x i64> [[ALLOCA]], i64 0, i32 0260; CHECK-NEXT: [[TMP11:%.*]] = insertelement <6 x i64> [[TMP10]], i64 1, i32 1261; CHECK-NEXT: [[TMP12:%.*]] = insertelement <6 x i64> [[TMP11]], i64 2, i32 2262; CHECK-NEXT: [[TMP13:%.*]] = insertelement <6 x i64> [[TMP12]], i64 3, i32 3263; CHECK-NEXT: [[TMP14:%.*]] = insertelement <6 x i64> [[TMP13]], i64 4, i32 4264; CHECK-NEXT: [[TMP15:%.*]] = insertelement <6 x i64> [[TMP14]], i64 5, i32 5265; CHECK-NEXT: [[TMP1:%.*]] = mul i64 [[SEL3]], 3266; CHECK-NEXT: [[TMP2:%.*]] = extractelement <6 x i64> [[TMP15]], i64 [[TMP1]]267; CHECK-NEXT: [[TMP3:%.*]] = insertelement <3 x i64> poison, i64 [[TMP2]], i64 0268; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[TMP1]], 1269; CHECK-NEXT: [[TMP5:%.*]] = extractelement <6 x i64> [[TMP15]], i64 [[TMP4]]270; CHECK-NEXT: [[TMP6:%.*]] = insertelement <3 x i64> [[TMP3]], i64 [[TMP5]], i64 1271; CHECK-NEXT: [[TMP7:%.*]] = add i64 [[TMP1]], 2272; CHECK-NEXT: [[TMP8:%.*]] = extractelement <6 x i64> [[TMP15]], i64 [[TMP7]]273; CHECK-NEXT: [[TMP9:%.*]] = insertelement <3 x i64> [[TMP6]], i64 [[TMP8]], i64 2274; CHECK-NEXT: [[ELEM:%.*]] = extractelement <3 x i64> [[TMP9]], i32 2275; CHECK-NEXT: store i64 [[ELEM]], ptr [[OUT]], align 8276; CHECK-NEXT: ret void277;278 %x = tail call i32 @llvm.amdgcn.workitem.id.x()279 %y = tail call i32 @llvm.amdgcn.workitem.id.y()280 %c1 = icmp uge i32 %x, 3281 %c2 = icmp uge i32 %y, 3282 %sel1 = select i1 %c1, i32 1, i32 2283 %sel2 = select i1 %c2, i32 0, i32 %sel1284 %sel3 = zext i32 %sel2 to i64285 %alloca = alloca [2 x [3 x i64]], align 16, addrspace(5)286 %gep.00 = getelementptr inbounds [2 x [3 x i64]], ptr addrspace(5) %alloca, i32 0287 %gep.01 = getelementptr inbounds [2 x [3 x i64]], ptr addrspace(5) %alloca, i32 0, i32 1, i32 0288 store <3 x i64> <i64 0, i64 1, i64 2>, ptr addrspace(5) %gep.00289 store <3 x i64> <i64 3, i64 4, i64 5>, ptr addrspace(5) %gep.01290 %gep = getelementptr inbounds [2 x [3 x i64]], ptr addrspace(5) %alloca, i64 0, i64 %sel3291 %load = load <3 x i64>, ptr addrspace(5) %gep292 %elem = extractelement <3 x i64> %load, i32 2293 store i64 %elem, ptr %out294 ret void295}296 297define amdgpu_kernel void @i64_2d_load_store_subvec_3_i64_offset_index(ptr %out) {298; CHECK-LABEL: define amdgpu_kernel void @i64_2d_load_store_subvec_3_i64_offset_index(299; CHECK-SAME: ptr [[OUT:%.*]]) {300; CHECK-NEXT: [[X:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()301; CHECK-NEXT: [[Y:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.y()302; CHECK-NEXT: [[C1:%.*]] = icmp uge i32 [[X]], 3303; CHECK-NEXT: [[C2:%.*]] = icmp uge i32 [[Y]], 3304; CHECK-NEXT: [[SEL1:%.*]] = select i1 [[C1]], i32 1, i32 2305; CHECK-NEXT: [[SEL2:%.*]] = select i1 [[C2]], i32 0, i32 [[SEL1]]306; CHECK-NEXT: [[SEL3:%.*]] = zext i32 [[SEL2]] to i64307; CHECK-NEXT: [[ALLOCA:%.*]] = freeze <6 x i64> poison308; CHECK-NEXT: [[TMP11:%.*]] = insertelement <6 x i64> [[ALLOCA]], i64 0, i32 0309; CHECK-NEXT: [[TMP12:%.*]] = insertelement <6 x i64> [[TMP11]], i64 1, i32 1310; CHECK-NEXT: [[TMP13:%.*]] = insertelement <6 x i64> [[TMP12]], i64 2, i32 2311; CHECK-NEXT: [[TMP14:%.*]] = insertelement <6 x i64> [[TMP13]], i64 3, i32 3312; CHECK-NEXT: [[TMP15:%.*]] = insertelement <6 x i64> [[TMP14]], i64 4, i32 4313; CHECK-NEXT: [[TMP16:%.*]] = insertelement <6 x i64> [[TMP15]], i64 5, i32 5314; CHECK-NEXT: [[TMP1:%.*]] = mul i64 [[SEL3]], 3315; CHECK-NEXT: [[TMP2:%.*]] = add i64 [[TMP1]], 6316; CHECK-NEXT: [[TMP3:%.*]] = extractelement <6 x i64> [[TMP16]], i64 [[TMP2]]317; CHECK-NEXT: [[TMP4:%.*]] = insertelement <3 x i64> poison, i64 [[TMP3]], i64 0318; CHECK-NEXT: [[TMP5:%.*]] = add i64 [[TMP2]], 1319; CHECK-NEXT: [[TMP6:%.*]] = extractelement <6 x i64> [[TMP16]], i64 [[TMP5]]320; CHECK-NEXT: [[TMP7:%.*]] = insertelement <3 x i64> [[TMP4]], i64 [[TMP6]], i64 1321; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[TMP2]], 2322; CHECK-NEXT: [[TMP9:%.*]] = extractelement <6 x i64> [[TMP16]], i64 [[TMP8]]323; CHECK-NEXT: [[TMP10:%.*]] = insertelement <3 x i64> [[TMP7]], i64 [[TMP9]], i64 2324; CHECK-NEXT: [[ELEM:%.*]] = extractelement <3 x i64> [[TMP10]], i32 2325; CHECK-NEXT: store i64 [[ELEM]], ptr [[OUT]], align 8326; CHECK-NEXT: ret void327;328 %x = tail call i32 @llvm.amdgcn.workitem.id.x()329 %y = tail call i32 @llvm.amdgcn.workitem.id.y()330 %c1 = icmp uge i32 %x, 3331 %c2 = icmp uge i32 %y, 3332 %sel1 = select i1 %c1, i32 1, i32 2333 %sel2 = select i1 %c2, i32 0, i32 %sel1334 %sel3 = zext i32 %sel2 to i64335 %alloca = alloca [2 x [3 x i64]], align 16, addrspace(5)336 %gep.00 = getelementptr inbounds [2 x [3 x i64]], ptr addrspace(5) %alloca, i32 0337 %gep.01 = getelementptr inbounds [2 x [3 x i64]], ptr addrspace(5) %alloca, i32 0, i32 1, i32 0338 store <3 x i64> <i64 0, i64 1, i64 2>, ptr addrspace(5) %gep.00339 store <3 x i64> <i64 3, i64 4, i64 5>, ptr addrspace(5) %gep.01340 %gep = getelementptr inbounds [2 x [3 x i64]], ptr addrspace(5) %alloca, i64 1, i64 %sel3341 %load = load <3 x i64>, ptr addrspace(5) %gep342 %elem = extractelement <3 x i64> %load, i32 2343 store i64 %elem, ptr %out344 ret void345}346 347define amdgpu_kernel void @i64_2d_load_store_subvec_4(ptr %out) {348; CHECK-LABEL: define amdgpu_kernel void @i64_2d_load_store_subvec_4(349; CHECK-SAME: ptr [[OUT:%.*]]) {350; CHECK-NEXT: [[X:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()351; CHECK-NEXT: [[Y:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.y()352; CHECK-NEXT: [[C1:%.*]] = icmp uge i32 [[X]], 3353; CHECK-NEXT: [[C2:%.*]] = icmp uge i32 [[Y]], 3354; CHECK-NEXT: [[SEL1:%.*]] = select i1 [[C1]], i32 1, i32 2355; CHECK-NEXT: [[SEL2:%.*]] = select i1 [[C2]], i32 0, i32 [[SEL1]]356; CHECK-NEXT: [[ALLOCA:%.*]] = freeze <8 x i64> poison357; CHECK-NEXT: [[TMP10:%.*]] = insertelement <8 x i64> [[ALLOCA]], i64 0, i32 0358; CHECK-NEXT: [[TMP11:%.*]] = insertelement <8 x i64> [[TMP10]], i64 1, i32 1359; CHECK-NEXT: [[TMP12:%.*]] = insertelement <8 x i64> [[TMP11]], i64 2, i32 2360; CHECK-NEXT: [[TMP13:%.*]] = insertelement <8 x i64> [[TMP12]], i64 3, i32 4361; CHECK-NEXT: [[TMP14:%.*]] = insertelement <8 x i64> [[TMP13]], i64 4, i32 5362; CHECK-NEXT: [[TMP15:%.*]] = insertelement <8 x i64> [[TMP14]], i64 5, i32 6363; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[SEL2]], 4364; CHECK-NEXT: [[TMP2:%.*]] = extractelement <8 x i64> [[TMP15]], i32 [[TMP1]]365; CHECK-NEXT: [[TMP3:%.*]] = insertelement <3 x i64> poison, i64 [[TMP2]], i64 0366; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[TMP1]], 1367; CHECK-NEXT: [[TMP5:%.*]] = extractelement <8 x i64> [[TMP15]], i32 [[TMP4]]368; CHECK-NEXT: [[TMP6:%.*]] = insertelement <3 x i64> [[TMP3]], i64 [[TMP5]], i64 1369; CHECK-NEXT: [[TMP7:%.*]] = add i32 [[TMP1]], 2370; CHECK-NEXT: [[TMP8:%.*]] = extractelement <8 x i64> [[TMP15]], i32 [[TMP7]]371; CHECK-NEXT: [[TMP9:%.*]] = insertelement <3 x i64> [[TMP6]], i64 [[TMP8]], i64 2372; CHECK-NEXT: [[ELEM:%.*]] = extractelement <3 x i64> [[TMP9]], i32 2373; CHECK-NEXT: store i64 [[ELEM]], ptr [[OUT]], align 8374; CHECK-NEXT: ret void375;376 %x = tail call i32 @llvm.amdgcn.workitem.id.x()377 %y = tail call i32 @llvm.amdgcn.workitem.id.y()378 %c1 = icmp uge i32 %x, 3379 %c2 = icmp uge i32 %y, 3380 %sel1 = select i1 %c1, i32 1, i32 2381 %sel2 = select i1 %c2, i32 0, i32 %sel1382 %alloca = alloca [2 x <3 x i64>], align 16, addrspace(5)383 %gep.00 = getelementptr inbounds [2 x <3 x i64>], ptr addrspace(5) %alloca, i32 0384 %gep.01 = getelementptr inbounds [2 x <3 x i64>], ptr addrspace(5) %alloca, i32 0, i32 1, i32 0385 store <3 x i64> <i64 0, i64 1, i64 2>, ptr addrspace(5) %gep.00386 store <3 x i64> <i64 3, i64 4, i64 5>, ptr addrspace(5) %gep.01387 %gep = getelementptr inbounds [2 x <3 x i64>], ptr addrspace(5) %alloca, i32 0, i32 %sel2388 %load = load <3 x i64>, ptr addrspace(5) %gep389 %elem = extractelement <3 x i64> %load, i32 2390 store i64 %elem, ptr %out391 ret void392}393 394define amdgpu_kernel void @i32_3d_load_store(ptr %out) {395; CHECK-LABEL: define amdgpu_kernel void @i32_3d_load_store(396; CHECK-SAME: ptr [[OUT:%.*]]) {397; CHECK-NEXT: [[X:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()398; CHECK-NEXT: [[Y:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.y()399; CHECK-NEXT: [[C1:%.*]] = icmp uge i32 [[X]], 3400; CHECK-NEXT: [[C2:%.*]] = icmp uge i32 [[Y]], 3401; CHECK-NEXT: [[SEL1:%.*]] = select i1 [[C1]], i32 1, i32 2402; CHECK-NEXT: [[SEL2:%.*]] = select i1 [[C2]], i32 0, i32 [[SEL1]]403; CHECK-NEXT: [[ALLOCA:%.*]] = freeze <12 x i32> poison404; CHECK-NEXT: [[TMP13:%.*]] = insertelement <12 x i32> [[ALLOCA]], i32 0, i32 0405; CHECK-NEXT: [[TMP2:%.*]] = insertelement <12 x i32> [[TMP13]], i32 1, i32 1406; CHECK-NEXT: [[TMP3:%.*]] = insertelement <12 x i32> [[TMP2]], i32 2, i32 2407; CHECK-NEXT: [[TMP4:%.*]] = insertelement <12 x i32> [[TMP3]], i32 3, i32 3408; CHECK-NEXT: [[TMP5:%.*]] = insertelement <12 x i32> [[TMP4]], i32 4, i32 4409; CHECK-NEXT: [[TMP6:%.*]] = insertelement <12 x i32> [[TMP5]], i32 5, i32 5410; CHECK-NEXT: [[TMP7:%.*]] = insertelement <12 x i32> [[TMP6]], i32 6, i32 6411; CHECK-NEXT: [[TMP8:%.*]] = insertelement <12 x i32> [[TMP7]], i32 7, i32 7412; CHECK-NEXT: [[TMP9:%.*]] = insertelement <12 x i32> [[TMP8]], i32 8, i32 8413; CHECK-NEXT: [[TMP10:%.*]] = insertelement <12 x i32> [[TMP9]], i32 9, i32 9414; CHECK-NEXT: [[TMP11:%.*]] = insertelement <12 x i32> [[TMP10]], i32 10, i32 10415; CHECK-NEXT: [[TMP12:%.*]] = insertelement <12 x i32> [[TMP11]], i32 11, i32 11416; CHECK-NEXT: [[TMP1:%.*]] = extractelement <12 x i32> [[TMP12]], i32 [[SEL2]]417; CHECK-NEXT: store i32 [[TMP1]], ptr [[OUT]], align 4418; CHECK-NEXT: ret void419;420 %x = tail call i32 @llvm.amdgcn.workitem.id.x()421 %y = tail call i32 @llvm.amdgcn.workitem.id.y()422 %c1 = icmp uge i32 %x, 3423 %c2 = icmp uge i32 %y, 3424 %sel1 = select i1 %c1, i32 1, i32 2425 %sel2 = select i1 %c2, i32 0, i32 %sel1426 %alloca = alloca [2 x [2 x [3 x i32]]], align 16, addrspace(5)427 %gep.000 = getelementptr inbounds [2 x [2 x [3 x i32]]], ptr addrspace(5) %alloca, i32 0, i32 0, i32 0, i32 0428 %gep.001 = getelementptr inbounds [2 x [2 x [3 x i32]]], ptr addrspace(5) %alloca, i32 0, i32 0, i32 0, i32 1429 %gep.002 = getelementptr inbounds [2 x [2 x [3 x i32]]], ptr addrspace(5) %alloca, i32 0, i32 0, i32 0, i32 2430 %gep.010 = getelementptr inbounds [2 x [2 x [3 x i32]]], ptr addrspace(5) %alloca, i32 0, i32 0, i32 1, i32 0431 %gep.011 = getelementptr inbounds [2 x [2 x [3 x i32]]], ptr addrspace(5) %alloca, i32 0, i32 0, i32 1, i32 1432 %gep.012 = getelementptr inbounds [2 x [2 x [3 x i32]]], ptr addrspace(5) %alloca, i32 0, i32 0, i32 1, i32 2433 %gep.100 = getelementptr inbounds [2 x [2 x [3 x i32]]], ptr addrspace(5) %alloca, i32 0, i32 1, i32 0, i32 0434 %gep.101 = getelementptr inbounds [2 x [2 x [3 x i32]]], ptr addrspace(5) %alloca, i32 0, i32 1, i32 0, i32 1435 %gep.102 = getelementptr inbounds [2 x [2 x [3 x i32]]], ptr addrspace(5) %alloca, i32 0, i32 1, i32 0, i32 2436 %gep.110 = getelementptr inbounds [2 x [2 x [3 x i32]]], ptr addrspace(5) %alloca, i32 0, i32 1, i32 1, i32 0437 %gep.111 = getelementptr inbounds [2 x [2 x [3 x i32]]], ptr addrspace(5) %alloca, i32 0, i32 1, i32 1, i32 1438 %gep.112 = getelementptr inbounds [2 x [2 x [3 x i32]]], ptr addrspace(5) %alloca, i32 0, i32 1, i32 1, i32 2439 store i32 0, ptr addrspace(5) %gep.000440 store i32 1, ptr addrspace(5) %gep.001441 store i32 2, ptr addrspace(5) %gep.002442 store i32 3, ptr addrspace(5) %gep.010443 store i32 4, ptr addrspace(5) %gep.011444 store i32 5, ptr addrspace(5) %gep.012445 store i32 6, ptr addrspace(5) %gep.100446 store i32 7, ptr addrspace(5) %gep.101447 store i32 8, ptr addrspace(5) %gep.102448 store i32 9, ptr addrspace(5) %gep.110449 store i32 10, ptr addrspace(5) %gep.111450 store i32 11, ptr addrspace(5) %gep.112451 %gep = getelementptr inbounds [12 x i32], ptr addrspace(5) %alloca, i32 0, i32 %sel2452 %load = load i32, ptr addrspace(5) %gep453 store i32 %load, ptr %out454 ret void455}456 457define amdgpu_kernel void @i16_2d_load_store(ptr %out, i32 %sel) {458; CHECK-LABEL: define amdgpu_kernel void @i16_2d_load_store(459; CHECK-SAME: ptr [[OUT:%.*]], i32 [[SEL:%.*]]) {460; CHECK-NEXT: [[ALLOCA:%.*]] = freeze <6 x i16> poison461; CHECK-NEXT: [[TMP7:%.*]] = insertelement <6 x i16> [[ALLOCA]], i16 0, i32 0462; CHECK-NEXT: [[TMP8:%.*]] = insertelement <6 x i16> [[TMP7]], i16 1, i32 1463; CHECK-NEXT: [[TMP3:%.*]] = insertelement <6 x i16> [[TMP8]], i16 2, i32 2464; CHECK-NEXT: [[TMP4:%.*]] = insertelement <6 x i16> [[TMP3]], i16 3, i32 3465; CHECK-NEXT: [[TMP5:%.*]] = insertelement <6 x i16> [[TMP4]], i16 4, i32 4466; CHECK-NEXT: [[TMP6:%.*]] = insertelement <6 x i16> [[TMP5]], i16 5, i32 5467; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[SEL]], 3468; CHECK-NEXT: [[TMP2:%.*]] = extractelement <6 x i16> [[TMP6]], i32 [[TMP1]]469; CHECK-NEXT: store i16 [[TMP2]], ptr [[OUT]], align 2470; CHECK-NEXT: ret void471;472 %alloca = alloca [2 x [3 x i16]], align 16, addrspace(5)473 %gep.00 = getelementptr inbounds [2 x [3 x i16]], ptr addrspace(5) %alloca, i32 0, i32 0, i32 0474 %gep.01 = getelementptr inbounds [2 x [3 x i16]], ptr addrspace(5) %alloca, i32 0, i32 0, i32 1475 %gep.02 = getelementptr inbounds [2 x [3 x i16]], ptr addrspace(5) %alloca, i32 0, i32 0, i32 2476 %gep.10 = getelementptr inbounds [2 x [3 x i16]], ptr addrspace(5) %alloca, i32 0, i32 1, i32 0477 %gep.11 = getelementptr inbounds [2 x [3 x i16]], ptr addrspace(5) %alloca, i32 0, i32 1, i32 1478 %gep.12 = getelementptr inbounds [2 x [3 x i16]], ptr addrspace(5) %alloca, i32 0, i32 1, i32 2479 store i16 0, ptr addrspace(5) %gep.00480 store i16 1, ptr addrspace(5) %gep.01481 store i16 2, ptr addrspace(5) %gep.02482 store i16 3, ptr addrspace(5) %gep.10483 store i16 4, ptr addrspace(5) %gep.11484 store i16 5, ptr addrspace(5) %gep.12485 %gep = getelementptr inbounds [2 x [3 x i16]], ptr addrspace(5) %alloca, i32 0, i32 1, i32 %sel486 %load = load i16, ptr addrspace(5) %gep487 store i16 %load, ptr %out488 ret void489}490 491define amdgpu_kernel void @float_2d_load_store(ptr %out, i32 %sel) {492; CHECK-LABEL: define amdgpu_kernel void @float_2d_load_store(493; CHECK-SAME: ptr [[OUT:%.*]], i32 [[SEL:%.*]]) {494; CHECK-NEXT: [[ALLOCA:%.*]] = freeze <6 x float> poison495; CHECK-NEXT: [[TMP7:%.*]] = insertelement <6 x float> [[ALLOCA]], float 0.000000e+00, i32 0496; CHECK-NEXT: [[TMP8:%.*]] = insertelement <6 x float> [[TMP7]], float 1.000000e+00, i32 1497; CHECK-NEXT: [[TMP3:%.*]] = insertelement <6 x float> [[TMP8]], float 2.000000e+00, i32 2498; CHECK-NEXT: [[TMP4:%.*]] = insertelement <6 x float> [[TMP3]], float 3.000000e+00, i32 3499; CHECK-NEXT: [[TMP5:%.*]] = insertelement <6 x float> [[TMP4]], float 4.000000e+00, i32 4500; CHECK-NEXT: [[TMP6:%.*]] = insertelement <6 x float> [[TMP5]], float 5.000000e+00, i32 5501; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[SEL]], 3502; CHECK-NEXT: [[TMP2:%.*]] = extractelement <6 x float> [[TMP6]], i32 [[TMP1]]503; CHECK-NEXT: store float [[TMP2]], ptr [[OUT]], align 4504; CHECK-NEXT: ret void505;506 %alloca = alloca [2 x [3 x float]], align 16, addrspace(5)507 %gep.00 = getelementptr inbounds [2 x [3 x float]], ptr addrspace(5) %alloca, i32 0, i32 0, i32 0508 %gep.01 = getelementptr inbounds [2 x [3 x float]], ptr addrspace(5) %alloca, i32 0, i32 0, i32 1509 %gep.02 = getelementptr inbounds [2 x [3 x float]], ptr addrspace(5) %alloca, i32 0, i32 0, i32 2510 %gep.10 = getelementptr inbounds [2 x [3 x float]], ptr addrspace(5) %alloca, i32 0, i32 1, i32 0511 %gep.11 = getelementptr inbounds [2 x [3 x float]], ptr addrspace(5) %alloca, i32 0, i32 1, i32 1512 %gep.12 = getelementptr inbounds [2 x [3 x float]], ptr addrspace(5) %alloca, i32 0, i32 1, i32 2513 store float 0.0, ptr addrspace(5) %gep.00514 store float 1.0, ptr addrspace(5) %gep.01515 store float 2.0, ptr addrspace(5) %gep.02516 store float 3.0, ptr addrspace(5) %gep.10517 store float 4.0, ptr addrspace(5) %gep.11518 store float 5.0, ptr addrspace(5) %gep.12519 %gep = getelementptr inbounds [2 x [3 x float]], ptr addrspace(5) %alloca, i32 0, i32 1, i32 %sel520 %load = load float, ptr addrspace(5) %gep521 store float %load, ptr %out522 ret void523}524 525define amdgpu_kernel void @ptr_2d_load_store(ptr %out, i32 %sel) {526; CHECK-LABEL: define amdgpu_kernel void @ptr_2d_load_store(527; CHECK-SAME: ptr [[OUT:%.*]], i32 [[SEL:%.*]]) {528; CHECK-NEXT: [[ALLOCA:%.*]] = freeze <6 x ptr> poison529; CHECK-NEXT: [[PTR_0:%.*]] = getelementptr inbounds ptr, ptr [[OUT]], i32 0530; CHECK-NEXT: [[PTR_1:%.*]] = getelementptr inbounds ptr, ptr [[OUT]], i32 1531; CHECK-NEXT: [[PTR_2:%.*]] = getelementptr inbounds ptr, ptr [[OUT]], i32 2532; CHECK-NEXT: [[PTR_3:%.*]] = getelementptr inbounds ptr, ptr [[OUT]], i32 3533; CHECK-NEXT: [[PTR_4:%.*]] = getelementptr inbounds ptr, ptr [[OUT]], i32 4534; CHECK-NEXT: [[PTR_5:%.*]] = getelementptr inbounds ptr, ptr [[OUT]], i32 5535; CHECK-NEXT: [[TMP1:%.*]] = insertelement <6 x ptr> [[ALLOCA]], ptr [[PTR_0]], i32 0536; CHECK-NEXT: [[TMP2:%.*]] = insertelement <6 x ptr> [[TMP1]], ptr [[PTR_1]], i32 1537; CHECK-NEXT: [[TMP3:%.*]] = insertelement <6 x ptr> [[TMP2]], ptr [[PTR_2]], i32 2538; CHECK-NEXT: [[TMP4:%.*]] = insertelement <6 x ptr> [[TMP3]], ptr [[PTR_3]], i32 3539; CHECK-NEXT: [[TMP5:%.*]] = insertelement <6 x ptr> [[TMP4]], ptr [[PTR_4]], i32 4540; CHECK-NEXT: [[TMP6:%.*]] = insertelement <6 x ptr> [[TMP5]], ptr [[PTR_5]], i32 5541; CHECK-NEXT: [[TMP7:%.*]] = add i32 [[SEL]], 3542; CHECK-NEXT: [[TMP8:%.*]] = extractelement <6 x ptr> [[TMP6]], i32 [[TMP7]]543; CHECK-NEXT: store ptr [[TMP8]], ptr [[OUT]], align 8544; CHECK-NEXT: ret void545;546 %alloca = alloca [2 x [3 x ptr]], align 16, addrspace(5)547 %gep.00 = getelementptr inbounds [2 x [3 x ptr]], ptr addrspace(5) %alloca, i32 0, i32 0, i32 0548 %gep.01 = getelementptr inbounds [2 x [3 x ptr]], ptr addrspace(5) %alloca, i32 0, i32 0, i32 1549 %gep.02 = getelementptr inbounds [2 x [3 x ptr]], ptr addrspace(5) %alloca, i32 0, i32 0, i32 2550 %gep.10 = getelementptr inbounds [2 x [3 x ptr]], ptr addrspace(5) %alloca, i32 0, i32 1, i32 0551 %gep.11 = getelementptr inbounds [2 x [3 x ptr]], ptr addrspace(5) %alloca, i32 0, i32 1, i32 1552 %gep.12 = getelementptr inbounds [2 x [3 x ptr]], ptr addrspace(5) %alloca, i32 0, i32 1, i32 2553 %ptr.0 = getelementptr inbounds ptr, ptr %out, i32 0554 %ptr.1 = getelementptr inbounds ptr, ptr %out, i32 1555 %ptr.2 = getelementptr inbounds ptr, ptr %out, i32 2556 %ptr.3 = getelementptr inbounds ptr, ptr %out, i32 3557 %ptr.4 = getelementptr inbounds ptr, ptr %out, i32 4558 %ptr.5 = getelementptr inbounds ptr, ptr %out, i32 5559 store ptr %ptr.0, ptr addrspace(5) %gep.00560 store ptr %ptr.1, ptr addrspace(5) %gep.01561 store ptr %ptr.2, ptr addrspace(5) %gep.02562 store ptr %ptr.3, ptr addrspace(5) %gep.10563 store ptr %ptr.4, ptr addrspace(5) %gep.11564 store ptr %ptr.5, ptr addrspace(5) %gep.12565 %gep = getelementptr inbounds [2 x [3 x ptr]], ptr addrspace(5) %alloca, i32 0, i32 1, i32 %sel566 %load = load ptr, ptr addrspace(5) %gep567 store ptr %load, ptr %out568 ret void569}570 571declare i32 @llvm.amdgcn.workitem.id.x()572declare i32 @llvm.amdgcn.workitem.id.y()573