205 lines · plain
1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-promote-alloca < %s | FileCheck %s3 4; Check that types where the store/allocation sizes don't match the type size5; don't crash.6 7 8define <7 x i9> @load_elem_i9_access_7xi9() {9; CHECK-LABEL: @load_elem_i9_access_7xi9(10; CHECK-NEXT: [[P:%.*]] = alloca <16 x i9>, align 1, addrspace(5)11; CHECK-NEXT: [[G:%.*]] = getelementptr i8, ptr addrspace(5) [[P]], i64 412; CHECK-NEXT: [[L:%.*]] = load <7 x i9>, ptr addrspace(5) [[G]], align 113; CHECK-NEXT: ret <7 x i9> [[L]]14;15 %p = alloca <16 x i9>, align 1, addrspace(5)16 %g = getelementptr i8, ptr addrspace(5) %p, i64 417 %l = load <7 x i9>, ptr addrspace(5) %g, align 118 ret <7 x i9> %l19}20 21define <8 x i1> @load_elem_i1_access_8xi1() {22; CHECK-LABEL: @load_elem_i1_access_8xi1(23; CHECK-NEXT: [[P:%.*]] = alloca <16 x i1>, align 1, addrspace(5)24; CHECK-NEXT: [[G:%.*]] = getelementptr i8, ptr addrspace(5) [[P]], i64 425; CHECK-NEXT: [[L:%.*]] = load <8 x i1>, ptr addrspace(5) [[G]], align 126; CHECK-NEXT: ret <8 x i1> [[L]]27;28 %p = alloca <16 x i1>, align 1, addrspace(5)29 %g = getelementptr i8, ptr addrspace(5) %p, i64 430 %l = load <8 x i1>, ptr addrspace(5) %g, align 131 ret <8 x i1> %l32}33 34define <3 x i1> @load_elem_i1_access_3xi1() {35; CHECK-LABEL: @load_elem_i1_access_3xi1(36; CHECK-NEXT: [[P:%.*]] = alloca <16 x i1>, align 1, addrspace(5)37; CHECK-NEXT: [[G:%.*]] = getelementptr i8, ptr addrspace(5) [[P]], i64 438; CHECK-NEXT: [[L:%.*]] = load <3 x i1>, ptr addrspace(5) [[G]], align 139; CHECK-NEXT: ret <3 x i1> [[L]]40;41 %p = alloca <16 x i1>, align 1, addrspace(5)42 %g = getelementptr i8, ptr addrspace(5) %p, i64 443 %l = load <3 x i1>, ptr addrspace(5) %g, align 144 ret <3 x i1> %l45}46 47define <3 x i1> @load_elem_i8_access_3xi1() {48; CHECK-LABEL: @load_elem_i8_access_3xi1(49; CHECK-NEXT: [[P:%.*]] = alloca <8 x i8>, align 1, addrspace(5)50; CHECK-NEXT: store <8 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, ptr addrspace(5) [[P]], align 151; CHECK-NEXT: [[G:%.*]] = getelementptr <4 x i8>, ptr addrspace(5) [[P]], i64 152; CHECK-NEXT: [[L:%.*]] = load <3 x i1>, ptr addrspace(5) [[G]], align 153; CHECK-NEXT: ret <3 x i1> [[L]]54;55 %p = alloca <8 x i8>, align 1, addrspace(5)56 store <8 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, ptr addrspace(5) %p, align 157 %g = getelementptr <4 x i8>, ptr addrspace(5) %p, i64 158 %l = load <3 x i1>, ptr addrspace(5) %g, align 159 ret <3 x i1> %l60}61 62; This one is actually not problematic.63define <8 x i1> @load_elem_i8_access_8xi1() {64; CHECK-LABEL: @load_elem_i8_access_8xi1(65; CHECK-NEXT: [[P:%.*]] = freeze <8 x i8> poison66; CHECK-NEXT: ret <8 x i1> <i1 true, i1 false, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false>67;68 %p = alloca <8 x i8>, align 1, addrspace(5)69 store <8 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, ptr addrspace(5) %p, align 170 %g = getelementptr <4 x i8>, ptr addrspace(5) %p, i64 171 %l = load <8 x i1>, ptr addrspace(5) %g, align 172 ret <8 x i1> %l73}74 75define <8 x i1> @storeload_elem_i1_access_8xi1() {76; CHECK-LABEL: @storeload_elem_i1_access_8xi1(77; CHECK-NEXT: [[P:%.*]] = alloca <16 x i1>, align 1, addrspace(5)78; CHECK-NEXT: [[G:%.*]] = getelementptr i8, ptr addrspace(5) [[P]], i64 479; CHECK-NEXT: store <8 x i1> <i1 true, i1 false, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false>, ptr addrspace(5) [[G]], align 180; CHECK-NEXT: [[L:%.*]] = load <8 x i1>, ptr addrspace(5) [[G]], align 181; CHECK-NEXT: ret <8 x i1> [[L]]82;83 %p = alloca <16 x i1>, align 1, addrspace(5)84 %g = getelementptr i8, ptr addrspace(5) %p, i64 485 store <8 x i1> <i1 true, i1 false, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false>, ptr addrspace(5) %g, align 186 %l = load <8 x i1>, ptr addrspace(5) %g, align 187 ret <8 x i1> %l88}89 90define <3 x i1> @storeload_elem_i1_access_3xi1() {91; CHECK-LABEL: @storeload_elem_i1_access_3xi1(92; CHECK-NEXT: [[P:%.*]] = alloca <16 x i1>, align 1, addrspace(5)93; CHECK-NEXT: [[G:%.*]] = getelementptr i8, ptr addrspace(5) [[P]], i64 494; CHECK-NEXT: store <3 x i1> <i1 true, i1 false, i1 true>, ptr addrspace(5) [[G]], align 195; CHECK-NEXT: [[L:%.*]] = load <3 x i1>, ptr addrspace(5) [[G]], align 196; CHECK-NEXT: ret <3 x i1> [[L]]97;98 %p = alloca <16 x i1>, align 1, addrspace(5)99 %g = getelementptr i8, ptr addrspace(5) %p, i64 4100 store <3 x i1> <i1 true, i1 false, i1 true>, ptr addrspace(5) %g, align 1101 %l = load <3 x i1>, ptr addrspace(5) %g, align 1102 ret <3 x i1> %l103}104 105define <3 x i1> @storeload_elem_i8_access_3xi1() {106; CHECK-LABEL: @storeload_elem_i8_access_3xi1(107; CHECK-NEXT: [[P:%.*]] = alloca <8 x i8>, align 1, addrspace(5)108; CHECK-NEXT: store <8 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, ptr addrspace(5) [[P]], align 1109; CHECK-NEXT: [[G:%.*]] = getelementptr <4 x i8>, ptr addrspace(5) [[P]], i64 1110; CHECK-NEXT: store <3 x i1> <i1 true, i1 false, i1 true>, ptr addrspace(5) [[G]], align 1111; CHECK-NEXT: [[L:%.*]] = load <3 x i1>, ptr addrspace(5) [[G]], align 1112; CHECK-NEXT: ret <3 x i1> [[L]]113;114 %p = alloca <8 x i8>, align 1, addrspace(5)115 store <8 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, ptr addrspace(5) %p, align 1116 %g = getelementptr <4 x i8>, ptr addrspace(5) %p, i64 1117 store <3 x i1> <i1 true, i1 false, i1 true>, ptr addrspace(5) %g, align 1118 %l = load <3 x i1>, ptr addrspace(5) %g, align 1119 ret <3 x i1> %l120}121 122; This one is actually not problematic.123define <8 x i1> @storeload_elem_i8_access_8xi1() {124; CHECK-LABEL: @storeload_elem_i8_access_8xi1(125; CHECK-NEXT: [[P:%.*]] = freeze <8 x i8> poison126; CHECK-NEXT: ret <8 x i1> <i1 true, i1 false, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false>127;128 %p = alloca <8 x i8>, align 1, addrspace(5)129 store <8 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, ptr addrspace(5) %p, align 1130 %g = getelementptr <4 x i8>, ptr addrspace(5) %p, i64 1131 store <8 x i1> <i1 true, i1 false, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false>, ptr addrspace(5) %g, align 1132 %l = load <8 x i1>, ptr addrspace(5) %g, align 1133 ret <8 x i1> %l134}135 136define <8 x i1> @array_of_vec_elem_i1_access_8xi1() {137; CHECK-LABEL: @array_of_vec_elem_i1_access_8xi1(138; CHECK-NEXT: [[P:%.*]] = alloca [2 x <16 x i1>], align 1, addrspace(5)139; CHECK-NEXT: [[G:%.*]] = getelementptr i8, ptr addrspace(5) [[P]], i64 4140; CHECK-NEXT: store <8 x i1> <i1 true, i1 false, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false>, ptr addrspace(5) [[G]], align 1141; CHECK-NEXT: [[L:%.*]] = load <8 x i1>, ptr addrspace(5) [[G]], align 1142; CHECK-NEXT: ret <8 x i1> [[L]]143;144 %p = alloca [2 x <16 x i1>], align 1, addrspace(5)145 %g = getelementptr i8, ptr addrspace(5) %p, i64 4146 store <8 x i1> <i1 true, i1 false, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false>, ptr addrspace(5) %g, align 1147 %l = load <8 x i1>, ptr addrspace(5) %g, align 1148 ret <8 x i1> %l149}150 151define <3 x i1> @array_of_vec_elem_i1_access_3xi1() {152; CHECK-LABEL: @array_of_vec_elem_i1_access_3xi1(153; CHECK-NEXT: [[P:%.*]] = alloca [2 x <16 x i1>], align 1, addrspace(5)154; CHECK-NEXT: [[G:%.*]] = getelementptr i8, ptr addrspace(5) [[P]], i64 4155; CHECK-NEXT: store <3 x i1> <i1 true, i1 false, i1 true>, ptr addrspace(5) [[G]], align 1156; CHECK-NEXT: [[L:%.*]] = load <3 x i1>, ptr addrspace(5) [[G]], align 1157; CHECK-NEXT: ret <3 x i1> [[L]]158;159 %p = alloca [2 x <16 x i1>], align 1, addrspace(5)160 %g = getelementptr i8, ptr addrspace(5) %p, i64 4161 store <3 x i1> <i1 true, i1 false, i1 true>, ptr addrspace(5) %g, align 1162 %l = load <3 x i1>, ptr addrspace(5) %g, align 1163 ret <3 x i1> %l164}165 166define <3 x i1> @array_of_vec_elem_i8_access_3xi1() {167; CHECK-LABEL: @array_of_vec_elem_i8_access_3xi1(168; CHECK-NEXT: [[P:%.*]] = alloca [2 x <8 x i8>], align 1, addrspace(5)169; CHECK-NEXT: store <8 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, ptr addrspace(5) [[P]], align 1170; CHECK-NEXT: [[G:%.*]] = getelementptr <4 x i8>, ptr addrspace(5) [[P]], i64 1171; CHECK-NEXT: store <3 x i1> <i1 true, i1 false, i1 true>, ptr addrspace(5) [[G]], align 1172; CHECK-NEXT: [[L:%.*]] = load <3 x i1>, ptr addrspace(5) [[G]], align 1173; CHECK-NEXT: ret <3 x i1> [[L]]174;175 %p = alloca [2 x <8 x i8>], align 1, addrspace(5)176 store <8 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, ptr addrspace(5) %p, align 1177 %g = getelementptr <4 x i8>, ptr addrspace(5) %p, i64 1178 store <3 x i1> <i1 true, i1 false, i1 true>, ptr addrspace(5) %g, align 1179 %l = load <3 x i1>, ptr addrspace(5) %g, align 1180 ret <3 x i1> %l181}182 183; This one is actually not problematic.184define <8 x i1> @array_of_vec_elem_i8_access_8xi1() {185; CHECK-LABEL: @array_of_vec_elem_i8_access_8xi1(186; CHECK-NEXT: [[P:%.*]] = freeze <16 x i8> poison187; CHECK-NEXT: [[TMP1:%.*]] = insertelement <16 x i8> [[P]], i8 1, i32 0188; CHECK-NEXT: [[TMP2:%.*]] = insertelement <16 x i8> [[TMP1]], i8 2, i32 1189; CHECK-NEXT: [[TMP3:%.*]] = insertelement <16 x i8> [[TMP2]], i8 3, i32 2190; CHECK-NEXT: [[TMP4:%.*]] = insertelement <16 x i8> [[TMP3]], i8 4, i32 3191; CHECK-NEXT: [[TMP5:%.*]] = insertelement <16 x i8> [[TMP4]], i8 5, i32 4192; CHECK-NEXT: [[TMP6:%.*]] = insertelement <16 x i8> [[TMP5]], i8 6, i32 5193; CHECK-NEXT: [[TMP7:%.*]] = insertelement <16 x i8> [[TMP6]], i8 7, i32 6194; CHECK-NEXT: [[TMP8:%.*]] = insertelement <16 x i8> [[TMP7]], i8 8, i32 7195; CHECK-NEXT: [[TMP9:%.*]] = insertelement <16 x i8> [[TMP8]], i8 5, i32 4196; CHECK-NEXT: ret <8 x i1> <i1 true, i1 false, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false>197;198 %p = alloca [2 x <8 x i8>], align 1, addrspace(5)199 store <8 x i8> <i8 1, i8 2, i8 3, i8 4, i8 5, i8 6, i8 7, i8 8>, ptr addrspace(5) %p, align 1200 %g = getelementptr <4 x i8>, ptr addrspace(5) %p, i64 1201 store <8 x i1> <i1 true, i1 false, i1 true, i1 false, i1 false, i1 false, i1 false, i1 false>, ptr addrspace(5) %g, align 1202 %l = load <8 x i1>, ptr addrspace(5) %g, align 1203 ret <8 x i1> %l204}205