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1; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri -disable-promote-alloca-to-vector -amdgpu-enable-lower-module-lds=0 < %s | FileCheck -check-prefix=GCN %s2 3; This shows that the amount LDS size estimate should try to not be4; sensitive to the order of the LDS globals. This should try to5; estimate the worst case padding behavior to avoid overallocating6; LDS.7 8; These functions use the same amount of LDS, but the total, final9; size changes depending on the visit order of first use.10 11; The one with the suboptimal order resulting in extra padding exceeds12; the desired limit13 14; The padding estimate heuristic used by the promote alloca pass15; is mostly determined by the order of the globals,16 17; Raw usage = 1060 bytes18; Rounded usage:19; 292 + (4 pad) + 256 + (8 pad) + 512 = 107220; 512 + (0 pad) + 256 + (0 pad) + 292 = 106021 22; At default occupancy guess of 7, 2340 bytes available total.23 24; 1280 need to be left to promote alloca25; optimally packed, this requires26 27 28@lds0 = internal unnamed_addr addrspace(3) global [32 x <4 x i32>] poison, align 1629@lds2 = internal unnamed_addr addrspace(3) global [32 x i64] poison, align 830@lds1 = internal unnamed_addr addrspace(3) global [73 x i32] poison, align 431 32 33; GCN-LABEL: {{^}}promote_alloca_size_order_0:34; GCN: .amdhsa_group_segment_fixed_size 106035define amdgpu_kernel void @promote_alloca_size_order_0(ptr addrspace(1) nocapture %out, ptr addrspace(1) nocapture %in, i32 %idx) #0 {36entry:37 %stack = alloca [5 x i32], align 4, addrspace(5)38 %tmp0 = load i32, ptr addrspace(1) %in, align 439 %arrayidx1 = getelementptr inbounds [5 x i32], ptr addrspace(5) %stack, i32 0, i32 %tmp040 store i32 4, ptr addrspace(5) %arrayidx1, align 441 %arrayidx2 = getelementptr inbounds i32, ptr addrspace(1) %in, i32 142 %tmp1 = load i32, ptr addrspace(1) %arrayidx2, align 443 %arrayidx3 = getelementptr inbounds [5 x i32], ptr addrspace(5) %stack, i32 0, i32 %tmp144 store i32 5, ptr addrspace(5) %arrayidx3, align 445 %tmp2 = load i32, ptr addrspace(5) %stack, align 446 store i32 %tmp2, ptr addrspace(1) %out, align 447 %arrayidx12 = getelementptr inbounds [5 x i32], ptr addrspace(5) %stack, i32 0, i32 148 %tmp3 = load i32, ptr addrspace(5) %arrayidx1249 %arrayidx13 = getelementptr inbounds i32, ptr addrspace(1) %out, i32 150 store i32 %tmp3, ptr addrspace(1) %arrayidx1351 52 %gep.lds1 = getelementptr inbounds [73 x i32], ptr addrspace(3) @lds1, i32 0, i32 %idx53 store volatile i32 0, ptr addrspace(3) %gep.lds1, align 454 55 %gep.lds2 = getelementptr inbounds [32 x i64], ptr addrspace(3) @lds2, i32 0, i32 %idx56 store volatile i64 0, ptr addrspace(3) %gep.lds2, align 857 58 %gep.lds0 = getelementptr inbounds [32 x <4 x i32>], ptr addrspace(3) @lds0, i32 0, i32 %idx59 store volatile <4 x i32> zeroinitializer, ptr addrspace(3) %gep.lds0, align 1660 61 ret void62}63 64; GCN-LABEL: {{^}}promote_alloca_size_order_1:65; GCN: .amdhsa_group_segment_fixed_size 107266define amdgpu_kernel void @promote_alloca_size_order_1(ptr addrspace(1) nocapture %out, ptr addrspace(1) nocapture %in, i32 %idx) #0 {67entry:68 %stack = alloca [5 x i32], align 4, addrspace(5)69 %tmp0 = load i32, ptr addrspace(1) %in, align 470 %arrayidx1 = getelementptr inbounds [5 x i32], ptr addrspace(5) %stack, i32 0, i32 %tmp071 store i32 4, ptr addrspace(5) %arrayidx1, align 472 %arrayidx2 = getelementptr inbounds i32, ptr addrspace(1) %in, i32 173 %tmp1 = load i32, ptr addrspace(1) %arrayidx2, align 474 %arrayidx3 = getelementptr inbounds [5 x i32], ptr addrspace(5) %stack, i32 0, i32 %tmp175 store i32 5, ptr addrspace(5) %arrayidx3, align 476 %tmp2 = load i32, ptr addrspace(5) %stack, align 477 store i32 %tmp2, ptr addrspace(1) %out, align 478 %arrayidx12 = getelementptr inbounds [5 x i32], ptr addrspace(5) %stack, i32 0, i32 179 %tmp3 = load i32, ptr addrspace(5) %arrayidx1280 %arrayidx13 = getelementptr inbounds i32, ptr addrspace(1) %out, i32 181 store i32 %tmp3, ptr addrspace(1) %arrayidx1382 83 %gep.lds0 = getelementptr inbounds [32 x <4 x i32>], ptr addrspace(3) @lds0, i32 0, i32 %idx84 store volatile <4 x i32> zeroinitializer, ptr addrspace(3) %gep.lds0, align 1685 86 %gep.lds2 = getelementptr inbounds [32 x i64], ptr addrspace(3) @lds2, i32 0, i32 %idx87 store volatile i64 0, ptr addrspace(3) %gep.lds2, align 888 89 %gep.lds1 = getelementptr inbounds [73 x i32], ptr addrspace(3) @lds1, i32 0, i32 %idx90 store volatile i32 0, ptr addrspace(3) %gep.lds1, align 491 92 ret void93}94 95@lds3 = internal unnamed_addr addrspace(3) global [13 x i32] poison, align 496@lds4 = internal unnamed_addr addrspace(3) global [63 x <4 x i32>] poison, align 1697 98; The guess from the alignment padding pushes this over the determined99; size limit, so it isn't promoted100 101; GCN-LABEL: {{^}}promote_alloca_align_pad_guess_over_limit:102; GCN: .amdhsa_group_segment_fixed_size 1060103define amdgpu_kernel void @promote_alloca_align_pad_guess_over_limit(ptr addrspace(1) nocapture %out, ptr addrspace(1) nocapture %in, i32 %idx) #0 {104entry:105 %stack = alloca [5 x i32], align 4, addrspace(5)106 %tmp0 = load i32, ptr addrspace(1) %in, align 4107 %arrayidx1 = getelementptr inbounds [5 x i32], ptr addrspace(5) %stack, i32 0, i32 %tmp0108 store i32 4, ptr addrspace(5) %arrayidx1, align 4109 %arrayidx2 = getelementptr inbounds i32, ptr addrspace(1) %in, i32 1110 %tmp1 = load i32, ptr addrspace(1) %arrayidx2, align 4111 %arrayidx3 = getelementptr inbounds [5 x i32], ptr addrspace(5) %stack, i32 0, i32 %tmp1112 store i32 5, ptr addrspace(5) %arrayidx3, align 4113 %tmp2 = load i32, ptr addrspace(5) %stack, align 4114 store i32 %tmp2, ptr addrspace(1) %out, align 4115 %arrayidx12 = getelementptr inbounds [5 x i32], ptr addrspace(5) %stack, i32 0, i32 1116 %tmp3 = load i32, ptr addrspace(5) %arrayidx12117 %arrayidx13 = getelementptr inbounds i32, ptr addrspace(1) %out, i32 1118 store i32 %tmp3, ptr addrspace(1) %arrayidx13119 120 %gep.lds3 = getelementptr inbounds [13 x i32], ptr addrspace(3) @lds3, i32 0, i32 %idx121 store volatile i32 0, ptr addrspace(3) %gep.lds3, align 4122 123 %gep.lds4 = getelementptr inbounds [63 x <4 x i32>], ptr addrspace(3) @lds4, i32 0, i32 %idx124 store volatile <4 x i32> zeroinitializer, ptr addrspace(3) %gep.lds4, align 16125 126 ret void127}128 129attributes #0 = { nounwind "amdgpu-flat-work-group-size"="64,64" "amdgpu-waves-per-eu"="1,7" }130 131!llvm.module.flags = !{!0}132!0 = !{i32 1, !"amdhsa_code_object_version", i32 400}133