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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-promote-alloca < %s | FileCheck %s3define amdgpu_ps void @scalar_alloca_ptr_with_vector_gep_of_gep(i32 %idx, ptr addrspace(1) %output) #0 {4; CHECK-LABEL: define amdgpu_ps void @scalar_alloca_ptr_with_vector_gep_of_gep(5; CHECK-SAME: i32 [[IDX:%.*]], ptr addrspace(1) [[OUTPUT:%.*]]) #[[ATTR0:[0-9]+]] {6; CHECK-NEXT: [[ENTRY:.*:]]7; CHECK-NEXT: [[BUF:%.*]] = freeze <20 x i32> poison8; CHECK-NEXT: [[TMP0:%.*]] = mul i32 [[IDX]], 29; CHECK-NEXT: [[TMP1:%.*]] = insertelement <20 x i32> [[BUF]], i32 1, i32 [[TMP0]]10; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[TMP0]], 111; CHECK-NEXT: [[TMP3:%.*]] = insertelement <20 x i32> [[TMP1]], i32 2, i32 [[TMP2]]12; CHECK-NEXT: [[TMP4:%.*]] = mul i32 [[IDX]], 213; CHECK-NEXT: [[TMP5:%.*]] = add i32 [[TMP4]], 114; CHECK-NEXT: [[TMP6:%.*]] = extractelement <20 x i32> [[TMP3]], i32 [[TMP5]]15; CHECK-NEXT: store i32 [[TMP6]], ptr addrspace(1) [[OUTPUT]], align 416; CHECK-NEXT: ret void17;18entry:19 %alloca = alloca [10 x <2 x i32>], align 8, addrspace(5)20 %row = getelementptr [10 x <2 x i32>], ptr addrspace(5) %alloca, i32 0, i32 %idx21 store <2 x i32> <i32 1, i32 2>, ptr addrspace(5) %row, align 822 %elt1 = getelementptr i8, ptr addrspace(5) %row, i32 423 %val = load i32, ptr addrspace(5) %elt1, align 424 store i32 %val, ptr addrspace(1) %output25 ret void26}27 28define amdgpu_ps void @scalar_alloca_ptr_with_vector_gep_of_gep3(i32 %idx, ptr addrspace(1) %output) #0 {29; CHECK-LABEL: define amdgpu_ps void @scalar_alloca_ptr_with_vector_gep_of_gep3(30; CHECK-SAME: i32 [[IDX:%.*]], ptr addrspace(1) [[OUTPUT:%.*]]) #[[ATTR0]] {31; CHECK-NEXT: [[ENTRY:.*:]]32; CHECK-NEXT: [[ALLOCA:%.*]] = freeze <16 x i32> poison33; CHECK-NEXT: [[TMP0:%.*]] = mul i32 [[IDX]], 234; CHECK-NEXT: [[TMP1:%.*]] = add i32 [[TMP0]], 835; CHECK-NEXT: [[TMP2:%.*]] = insertelement <16 x i32> [[ALLOCA]], i32 10, i32 [[TMP1]]36; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[TMP1]], 137; CHECK-NEXT: [[TMP4:%.*]] = insertelement <16 x i32> [[TMP2]], i32 20, i32 [[TMP3]]38; CHECK-NEXT: [[TMP5:%.*]] = mul i32 [[IDX]], 239; CHECK-NEXT: [[TMP6:%.*]] = add i32 [[TMP5]], 940; CHECK-NEXT: [[TMP7:%.*]] = extractelement <16 x i32> [[TMP4]], i32 [[TMP6]]41; CHECK-NEXT: store i32 [[TMP7]], ptr addrspace(1) [[OUTPUT]], align 442; CHECK-NEXT: ret void43;44entry:45 %alloca = alloca [2 x [4 x <2 x i32>]], align 8, addrspace(5)46 %lvl1 = getelementptr inbounds [2 x [4 x <2 x i32>]], ptr addrspace(5) %alloca, i32 0, i32 147 %lvl2 = getelementptr inbounds [4 x <2 x i32>], ptr addrspace(5) %lvl1, i32 0, i32 %idx48 store <2 x i32> <i32 10, i32 20>, ptr addrspace(5) %lvl2, align 849 %byte = getelementptr inbounds i8, ptr addrspace(5) %lvl2, i32 450 %val = load i32, ptr addrspace(5) %byte, align 451 store i32 %val, ptr addrspace(1) %output52 ret void53}54 55define amdgpu_ps void @scalar_alloca_ptr_with_vector_gep_twice_idx(i32 %idx, ptr addrspace(1) %out) #0 {56; CHECK-LABEL: define amdgpu_ps void @scalar_alloca_ptr_with_vector_gep_twice_idx(57; CHECK-SAME: i32 [[IDX:%.*]], ptr addrspace(1) [[OUT:%.*]]) #[[ATTR0]] {58; CHECK-NEXT: [[ENTRY:.*:]]59; CHECK-NEXT: [[BUF:%.*]] = freeze <20 x i32> poison60; CHECK-NEXT: [[TMP0:%.*]] = mul i32 [[IDX]], 261; CHECK-NEXT: [[TMP4:%.*]] = insertelement <20 x i32> [[BUF]], i32 1, i32 [[TMP0]]62; CHECK-NEXT: [[TMP5:%.*]] = add i32 [[TMP0]], 163; CHECK-NEXT: [[TMP3:%.*]] = insertelement <20 x i32> [[TMP4]], i32 2, i32 [[TMP5]]64; CHECK-NEXT: [[TMP1:%.*]] = mul i32 [[IDX]], 365; CHECK-NEXT: [[TMP2:%.*]] = extractelement <20 x i32> [[TMP3]], i32 [[TMP1]]66; CHECK-NEXT: store i32 [[TMP2]], ptr addrspace(1) [[OUT]], align 467; CHECK-NEXT: ret void68;69entry:70 %alloca = alloca [10 x [2 x i32]], align 8, addrspace(5)71 %row = getelementptr inbounds [10 x [2 x i32]], ptr addrspace(5) %alloca, i32 0, i32 %idx72 store <2 x i32> <i32 1, i32 2>, ptr addrspace(5) %row, align 873 %elt = getelementptr inbounds [2 x i32], ptr addrspace(5) %row, i32 0, i32 %idx74 %val = load i32, ptr addrspace(5) %elt, align 475 store i32 %val, ptr addrspace(1) %out76 ret void77}78 79attributes #0 = { "amdgpu-promote-alloca-to-vector-max-regs"="32" }80