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1; RUN: llc -mtriple=amdgcn -mcpu=fiji < %s | FileCheck -enable-var-scope -check-prefix=GCN %s2; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck -enable-var-scope -check-prefix=GCN %s3; RUN: opt -S -mtriple=amdgcn-- -data-layout=A5 -mcpu=fiji -passes=sroa,amdgpu-promote-alloca < %s | FileCheck -check-prefix=OPT %s4 5; GCN-LABEL: {{^}}float4_alloca_store4:6; OPT-LABEL: define amdgpu_kernel void @float4_alloca_store47 8; GCN-NOT: buffer_9; GCN: v_cndmask_b3210; GCN: v_cndmask_b3211; GCN: v_cndmask_b32_e32 [[RES:v[0-9]+]], 4.0,12; GCN: store_dword v{{.+}}, [[RES]]13 14; OPT: %0 = extractelement <4 x float> <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00, float 4.000000e+00>, i32 %sel215; OPT: store float %0, ptr addrspace(1) %out, align 416 17define amdgpu_kernel void @float4_alloca_store4(ptr addrspace(1) %out, ptr addrspace(3) %dummy_lds) {18entry:19 %alloca = alloca <4 x float>, align 16, addrspace(5)20 %x = tail call i32 @llvm.amdgcn.workitem.id.x()21 %y = tail call i32 @llvm.amdgcn.workitem.id.y()22 %c1 = icmp uge i32 %x, 323 %c2 = icmp uge i32 %y, 324 %sel1 = select i1 %c1, i32 1, i32 225 %sel2 = select i1 %c2, i32 0, i32 %sel126 %gep = getelementptr inbounds <4 x float>, ptr addrspace(5) %alloca, i32 0, i32 %sel227 store <4 x float> <float 1.0, float 2.0, float 3.0, float 4.0>, ptr addrspace(5) %alloca, align 428 %load = load float, ptr addrspace(5) %gep, align 429 store float %load, ptr addrspace(1) %out, align 430 ret void31}32 33; GCN-LABEL: {{^}}float4_alloca_load4:34; OPT-LABEL: define amdgpu_kernel void @float4_alloca_load435 36; GCN-NOT: v_movrel37; GCN-NOT: buffer_38; GCN-NOT: v_cmp_39; GCN-NOT: v_cndmask_40; GCN: v_mov_b32_e32 [[ONE:v[0-9]+]], 1.041; GCN: v_mov_b32_e32 v{{[0-9]+}}, [[ONE]]42; GCN: v_mov_b32_e32 v{{[0-9]+}}, [[ONE]]43; GCN: v_mov_b32_e32 v{{[0-9]+}}, [[ONE]]44; GCN: store_dwordx4 v{{.+}},45 46; OPT: %0 = insertelement <4 x float> poison, float 1.000000e+00, i32 %sel247; OPT: store <4 x float> %0, ptr addrspace(1) %out, align 448 49define amdgpu_kernel void @float4_alloca_load4(ptr addrspace(1) %out, ptr addrspace(3) %dummy_lds) {50entry:51 %alloca = alloca <4 x float>, align 16, addrspace(5)52 store <4 x float> poison, ptr addrspace(5) %alloca53 %x = tail call i32 @llvm.amdgcn.workitem.id.x()54 %y = tail call i32 @llvm.amdgcn.workitem.id.y()55 %c1 = icmp uge i32 %x, 356 %c2 = icmp uge i32 %y, 357 %sel1 = select i1 %c1, i32 1, i32 258 %sel2 = select i1 %c2, i32 0, i32 %sel159 %gep = getelementptr inbounds <4 x float>, ptr addrspace(5) %alloca, i32 0, i32 %sel260 store float 1.0, ptr addrspace(5) %gep, align 461 %load = load <4 x float>, ptr addrspace(5) %alloca, align 462 store <4 x float> %load, ptr addrspace(1) %out, align 463 ret void64}65 66; GCN-LABEL: {{^}}half4_alloca_store4:67; OPT-LABEL: define amdgpu_kernel void @half4_alloca_store468 69; GCN-NOT: buffer_70; GCN-DAG: s_mov_b32 s[[SH:[0-9]+]], 0x4400420071; GCN-DAG: s_mov_b32 s[[SL:[0-9]+]], 0x40003c0072; GCN: v_lshrrev_b64 v[{{[0-9:]+}}], v{{[0-9]+}}, s[[[SL]]:[[SH]]]73 74; OPT: %0 = extractelement <4 x half> <half 0xH3C00, half 0xH4000, half 0xH4200, half 0xH4400>, i32 %sel275; OPT: store half %0, ptr addrspace(1) %out, align 276 77define amdgpu_kernel void @half4_alloca_store4(ptr addrspace(1) %out, ptr addrspace(3) %dummy_lds) {78entry:79 %alloca = alloca <4 x half>, align 16, addrspace(5)80 %x = tail call i32 @llvm.amdgcn.workitem.id.x()81 %y = tail call i32 @llvm.amdgcn.workitem.id.y()82 %c1 = icmp uge i32 %x, 383 %c2 = icmp uge i32 %y, 384 %sel1 = select i1 %c1, i32 1, i32 285 %sel2 = select i1 %c2, i32 0, i32 %sel186 %gep = getelementptr inbounds <4 x half>, ptr addrspace(5) %alloca, i32 0, i32 %sel287 store <4 x half> <half 1.0, half 2.0, half 3.0, half 4.0>, ptr addrspace(5) %alloca, align 288 %load = load half, ptr addrspace(5) %gep, align 289 store half %load, ptr addrspace(1) %out, align 290 ret void91}92 93; GCN-LABEL: {{^}}half4_alloca_load4:94; OPT-LABEL: define amdgpu_kernel void @half4_alloca_load495 96; GCN-NOT: buffer_97; GCN: s_mov_b64 s[{{[0-9:]+}}], 0xffff98 99; OPT: %alloca = freeze <4 x half> poison100; OPT: %0 = insertelement <4 x half> %alloca, half 0xH3C00, i32 %sel2101; OPT: store <4 x half> %0, ptr addrspace(1) %out, align 2102 103define amdgpu_kernel void @half4_alloca_load4(ptr addrspace(1) %out, ptr addrspace(3) %dummy_lds) {104entry:105 %alloca = alloca <4 x half>, align 16, addrspace(5)106 %x = tail call i32 @llvm.amdgcn.workitem.id.x()107 %y = tail call i32 @llvm.amdgcn.workitem.id.y()108 %c1 = icmp uge i32 %x, 3109 %c2 = icmp uge i32 %y, 3110 %sel1 = select i1 %c1, i32 1, i32 2111 %sel2 = select i1 %c2, i32 0, i32 %sel1112 %gep = getelementptr inbounds <4 x half>, ptr addrspace(5) %alloca, i32 0, i32 %sel2113 store half 1.0, ptr addrspace(5) %gep, align 4114 %load = load <4 x half>, ptr addrspace(5) %alloca, align 2115 store <4 x half> %load, ptr addrspace(1) %out, align 2116 ret void117}118 119; GCN-LABEL: {{^}}short4_alloca_store4:120; OPT-LABEL: define amdgpu_kernel void @short4_alloca_store4121 122; GCN-NOT: buffer_123; GCN-DAG: s_mov_b32 s[[SH:[0-9]+]], 0x40003124; GCN-DAG: s_mov_b32 s[[SL:[0-9]+]], 0x20001125; GCN: v_lshrrev_b64 v[{{[0-9:]+}}], v{{[0-9]+}}, s[[[SL]]:[[SH]]]126 127; OPT: %0 = extractelement <4 x i16> <i16 1, i16 2, i16 3, i16 4>, i32 %sel2128; OPT: store i16 %0, ptr addrspace(1) %out, align 2129 130define amdgpu_kernel void @short4_alloca_store4(ptr addrspace(1) %out, ptr addrspace(3) %dummy_lds) {131entry:132 %alloca = alloca <4 x i16>, align 16, addrspace(5)133 %x = tail call i32 @llvm.amdgcn.workitem.id.x()134 %y = tail call i32 @llvm.amdgcn.workitem.id.y()135 %c1 = icmp uge i32 %x, 3136 %c2 = icmp uge i32 %y, 3137 %sel1 = select i1 %c1, i32 1, i32 2138 %sel2 = select i1 %c2, i32 0, i32 %sel1139 %gep = getelementptr inbounds <4 x i16>, ptr addrspace(5) %alloca, i32 0, i32 %sel2140 store <4 x i16> <i16 1, i16 2, i16 3, i16 4>, ptr addrspace(5) %alloca, align 2141 %load = load i16, ptr addrspace(5) %gep, align 2142 store i16 %load, ptr addrspace(1) %out, align 2143 ret void144}145 146; GCN-LABEL: {{^}}short4_alloca_load4:147; OPT-LABEL: define amdgpu_kernel void @short4_alloca_load4148 149; GCN-NOT: buffer_150; GCN: s_mov_b64 s[{{[0-9:]+}}], 0xffff151 152; OPT: %alloca = freeze <4 x i16> poison153; OPT: %0 = insertelement <4 x i16> %alloca, i16 1, i32 %sel2154; OPT: store <4 x i16> %0, ptr addrspace(1) %out, align 2155 156define amdgpu_kernel void @short4_alloca_load4(ptr addrspace(1) %out, ptr addrspace(3) %dummy_lds) {157entry:158 %alloca = alloca <4 x i16>, align 16, addrspace(5)159 %x = tail call i32 @llvm.amdgcn.workitem.id.x()160 %y = tail call i32 @llvm.amdgcn.workitem.id.y()161 %c1 = icmp uge i32 %x, 3162 %c2 = icmp uge i32 %y, 3163 %sel1 = select i1 %c1, i32 1, i32 2164 %sel2 = select i1 %c2, i32 0, i32 %sel1165 %gep = getelementptr inbounds <4 x i16>, ptr addrspace(5) %alloca, i32 0, i32 %sel2166 store i16 1, ptr addrspace(5) %gep, align 4167 %load = load <4 x i16>, ptr addrspace(5) %alloca, align 2168 store <4 x i16> %load, ptr addrspace(1) %out, align 2169 ret void170}171 172; GCN-LABEL: {{^}}ptr_alloca_bitcast:173; OPT-LABEL: define i64 @ptr_alloca_bitcast174 175; GCN-NOT: buffer_176; GCN: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)177; GCN-NEXT: s_setpc_b64178 179 180; OPT: ret i64 undef181 182define i64 @ptr_alloca_bitcast() {183entry:184 %private_iptr = alloca <2 x i32>, align 8, addrspace(5)185 %tmp1 = load i64, ptr addrspace(5) %private_iptr, align 8186 ret i64 %tmp1187}188 189declare i32 @llvm.amdgcn.workitem.id.x()190declare i32 @llvm.amdgcn.workitem.id.y()191