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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 52; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-promote-alloca -disable-promote-alloca-to-lds=1 < %s | FileCheck --check-prefix=BASE --check-prefix=DEFAULT %s3; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-promote-alloca -disable-promote-alloca-to-lds=1 -amdgpu-promote-alloca-to-vector-vgpr-ratio=2 < %s | FileCheck --check-prefix=BASE %s --check-prefix=RATIO24; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-promote-alloca -disable-promote-alloca-to-lds=1 -amdgpu-promote-alloca-to-vector-vgpr-ratio=8 < %s | FileCheck --check-prefix=BASE %s --check-prefix=RATIO85 6define amdgpu_kernel void @i32_24_elements(ptr %out) #0 {7; DEFAULT-LABEL: define amdgpu_kernel void @i32_24_elements(8; DEFAULT-SAME: ptr [[OUT:%.*]]) #[[ATTR0:[0-9]+]] {9; DEFAULT-NEXT: [[X:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()10; DEFAULT-NEXT: [[Y:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.y()11; DEFAULT-NEXT: [[C1:%.*]] = icmp uge i32 [[X]], 312; DEFAULT-NEXT: [[C2:%.*]] = icmp uge i32 [[Y]], 313; DEFAULT-NEXT: [[SEL1:%.*]] = select i1 [[C1]], i32 1, i32 214; DEFAULT-NEXT: [[SEL2:%.*]] = select i1 [[C2]], i32 0, i32 [[SEL1]]15; DEFAULT-NEXT: [[ALLOCA:%.*]] = alloca [24 x i32], align 16, addrspace(5)16; DEFAULT-NEXT: call void @llvm.memset.p5.i32(ptr addrspace(5) [[ALLOCA]], i8 0, i32 96, i1 false)17; DEFAULT-NEXT: [[GEP_0:%.*]] = getelementptr inbounds [24 x i32], ptr addrspace(5) [[ALLOCA]], i32 0, i32 018; DEFAULT-NEXT: [[GEP_1:%.*]] = getelementptr inbounds [24 x i32], ptr addrspace(5) [[ALLOCA]], i32 0, i32 2019; DEFAULT-NEXT: store i32 42, ptr addrspace(5) [[GEP_0]], align 420; DEFAULT-NEXT: store i32 43, ptr addrspace(5) [[GEP_1]], align 421; DEFAULT-NEXT: [[GEP:%.*]] = getelementptr inbounds [24 x i32], ptr addrspace(5) [[ALLOCA]], i32 0, i32 [[SEL2]]22; DEFAULT-NEXT: [[LOAD:%.*]] = load i32, ptr addrspace(5) [[GEP]], align 423; DEFAULT-NEXT: store i32 [[LOAD]], ptr [[OUT]], align 424; DEFAULT-NEXT: ret void25;26; RATIO2-LABEL: define amdgpu_kernel void @i32_24_elements(27; RATIO2-SAME: ptr [[OUT:%.*]]) #[[ATTR0:[0-9]+]] {28; RATIO2-NEXT: [[X:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()29; RATIO2-NEXT: [[Y:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.y()30; RATIO2-NEXT: [[C1:%.*]] = icmp uge i32 [[X]], 331; RATIO2-NEXT: [[C2:%.*]] = icmp uge i32 [[Y]], 332; RATIO2-NEXT: [[SEL1:%.*]] = select i1 [[C1]], i32 1, i32 233; RATIO2-NEXT: [[SEL2:%.*]] = select i1 [[C2]], i32 0, i32 [[SEL1]]34; RATIO2-NEXT: [[ALLOCA:%.*]] = freeze <24 x i32> poison35; RATIO2-NEXT: [[TMP1:%.*]] = extractelement <24 x i32> <i32 42, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 43, i32 0, i32 0, i32 0>, i32 [[SEL2]]36; RATIO2-NEXT: store i32 [[TMP1]], ptr [[OUT]], align 437; RATIO2-NEXT: ret void38;39; RATIO8-LABEL: define amdgpu_kernel void @i32_24_elements(40; RATIO8-SAME: ptr [[OUT:%.*]]) #[[ATTR0:[0-9]+]] {41; RATIO8-NEXT: [[X:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()42; RATIO8-NEXT: [[Y:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.y()43; RATIO8-NEXT: [[C1:%.*]] = icmp uge i32 [[X]], 344; RATIO8-NEXT: [[C2:%.*]] = icmp uge i32 [[Y]], 345; RATIO8-NEXT: [[SEL1:%.*]] = select i1 [[C1]], i32 1, i32 246; RATIO8-NEXT: [[SEL2:%.*]] = select i1 [[C2]], i32 0, i32 [[SEL1]]47; RATIO8-NEXT: [[ALLOCA:%.*]] = alloca [24 x i32], align 16, addrspace(5)48; RATIO8-NEXT: call void @llvm.memset.p5.i32(ptr addrspace(5) [[ALLOCA]], i8 0, i32 96, i1 false)49; RATIO8-NEXT: [[GEP_0:%.*]] = getelementptr inbounds [24 x i32], ptr addrspace(5) [[ALLOCA]], i32 0, i32 050; RATIO8-NEXT: [[GEP_1:%.*]] = getelementptr inbounds [24 x i32], ptr addrspace(5) [[ALLOCA]], i32 0, i32 2051; RATIO8-NEXT: store i32 42, ptr addrspace(5) [[GEP_0]], align 452; RATIO8-NEXT: store i32 43, ptr addrspace(5) [[GEP_1]], align 453; RATIO8-NEXT: [[GEP:%.*]] = getelementptr inbounds [24 x i32], ptr addrspace(5) [[ALLOCA]], i32 0, i32 [[SEL2]]54; RATIO8-NEXT: [[LOAD:%.*]] = load i32, ptr addrspace(5) [[GEP]], align 455; RATIO8-NEXT: store i32 [[LOAD]], ptr [[OUT]], align 456; RATIO8-NEXT: ret void57;58 %x = tail call i32 @llvm.amdgcn.workitem.id.x()59 %y = tail call i32 @llvm.amdgcn.workitem.id.y()60 %c1 = icmp uge i32 %x, 361 %c2 = icmp uge i32 %y, 362 %sel1 = select i1 %c1, i32 1, i32 263 %sel2 = select i1 %c2, i32 0, i32 %sel164 %alloca = alloca [24 x i32], align 16, addrspace(5)65 call void @llvm.memset.p5.i32(ptr addrspace(5) %alloca, i8 0, i32 96, i1 false)66 %gep.0 = getelementptr inbounds [24 x i32], ptr addrspace(5) %alloca, i32 0, i32 067 %gep.1 = getelementptr inbounds [24 x i32], ptr addrspace(5) %alloca, i32 0, i32 2068 store i32 42, ptr addrspace(5) %gep.069 store i32 43, ptr addrspace(5) %gep.170 %gep = getelementptr inbounds [24 x i32], ptr addrspace(5) %alloca, i32 0, i32 %sel271 %load = load i32, ptr addrspace(5) %gep72 store i32 %load, ptr %out73 ret void74}75 76define amdgpu_kernel void @i32_24_elements_attrib(ptr %out) #1 {77; DEFAULT-LABEL: define amdgpu_kernel void @i32_24_elements_attrib(78; DEFAULT-SAME: ptr [[OUT:%.*]]) #[[ATTR1:[0-9]+]] {79; DEFAULT-NEXT: [[X:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()80; DEFAULT-NEXT: [[Y:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.y()81; DEFAULT-NEXT: [[C1:%.*]] = icmp uge i32 [[X]], 382; DEFAULT-NEXT: [[C2:%.*]] = icmp uge i32 [[Y]], 383; DEFAULT-NEXT: [[SEL1:%.*]] = select i1 [[C1]], i32 1, i32 284; DEFAULT-NEXT: [[SEL2:%.*]] = select i1 [[C2]], i32 0, i32 [[SEL1]]85; DEFAULT-NEXT: [[ALLOCA:%.*]] = freeze <24 x i32> poison86; DEFAULT-NEXT: [[TMP1:%.*]] = extractelement <24 x i32> <i32 42, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 43, i32 0, i32 0, i32 0>, i32 [[SEL2]]87; DEFAULT-NEXT: store i32 [[TMP1]], ptr [[OUT]], align 488; DEFAULT-NEXT: ret void89;90; RATIO2-LABEL: define amdgpu_kernel void @i32_24_elements_attrib(91; RATIO2-SAME: ptr [[OUT:%.*]]) #[[ATTR1:[0-9]+]] {92; RATIO2-NEXT: [[X:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()93; RATIO2-NEXT: [[Y:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.y()94; RATIO2-NEXT: [[C1:%.*]] = icmp uge i32 [[X]], 395; RATIO2-NEXT: [[C2:%.*]] = icmp uge i32 [[Y]], 396; RATIO2-NEXT: [[SEL1:%.*]] = select i1 [[C1]], i32 1, i32 297; RATIO2-NEXT: [[SEL2:%.*]] = select i1 [[C2]], i32 0, i32 [[SEL1]]98; RATIO2-NEXT: [[ALLOCA:%.*]] = freeze <24 x i32> poison99; RATIO2-NEXT: [[TMP1:%.*]] = extractelement <24 x i32> <i32 42, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 43, i32 0, i32 0, i32 0>, i32 [[SEL2]]100; RATIO2-NEXT: store i32 [[TMP1]], ptr [[OUT]], align 4101; RATIO2-NEXT: ret void102;103; RATIO8-LABEL: define amdgpu_kernel void @i32_24_elements_attrib(104; RATIO8-SAME: ptr [[OUT:%.*]]) #[[ATTR1:[0-9]+]] {105; RATIO8-NEXT: [[X:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()106; RATIO8-NEXT: [[Y:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.y()107; RATIO8-NEXT: [[C1:%.*]] = icmp uge i32 [[X]], 3108; RATIO8-NEXT: [[C2:%.*]] = icmp uge i32 [[Y]], 3109; RATIO8-NEXT: [[SEL1:%.*]] = select i1 [[C1]], i32 1, i32 2110; RATIO8-NEXT: [[SEL2:%.*]] = select i1 [[C2]], i32 0, i32 [[SEL1]]111; RATIO8-NEXT: [[ALLOCA:%.*]] = alloca [24 x i32], align 16, addrspace(5)112; RATIO8-NEXT: call void @llvm.memset.p5.i32(ptr addrspace(5) [[ALLOCA]], i8 0, i32 96, i1 false)113; RATIO8-NEXT: [[GEP_0:%.*]] = getelementptr inbounds [24 x i32], ptr addrspace(5) [[ALLOCA]], i32 0, i32 0114; RATIO8-NEXT: [[GEP_1:%.*]] = getelementptr inbounds [24 x i32], ptr addrspace(5) [[ALLOCA]], i32 0, i32 20115; RATIO8-NEXT: store i32 42, ptr addrspace(5) [[GEP_0]], align 4116; RATIO8-NEXT: store i32 43, ptr addrspace(5) [[GEP_1]], align 4117; RATIO8-NEXT: [[GEP:%.*]] = getelementptr inbounds [24 x i32], ptr addrspace(5) [[ALLOCA]], i32 0, i32 [[SEL2]]118; RATIO8-NEXT: [[LOAD:%.*]] = load i32, ptr addrspace(5) [[GEP]], align 4119; RATIO8-NEXT: store i32 [[LOAD]], ptr [[OUT]], align 4120; RATIO8-NEXT: ret void121;122 %x = tail call i32 @llvm.amdgcn.workitem.id.x()123 %y = tail call i32 @llvm.amdgcn.workitem.id.y()124 %c1 = icmp uge i32 %x, 3125 %c2 = icmp uge i32 %y, 3126 %sel1 = select i1 %c1, i32 1, i32 2127 %sel2 = select i1 %c2, i32 0, i32 %sel1128 %alloca = alloca [24 x i32], align 16, addrspace(5)129 call void @llvm.memset.p5.i32(ptr addrspace(5) %alloca, i8 0, i32 96, i1 false)130 %gep.0 = getelementptr inbounds [24 x i32], ptr addrspace(5) %alloca, i32 0, i32 0131 %gep.1 = getelementptr inbounds [24 x i32], ptr addrspace(5) %alloca, i32 0, i32 20132 store i32 42, ptr addrspace(5) %gep.0133 store i32 43, ptr addrspace(5) %gep.1134 %gep = getelementptr inbounds [24 x i32], ptr addrspace(5) %alloca, i32 0, i32 %sel2135 %load = load i32, ptr addrspace(5) %gep136 store i32 %load, ptr %out137 ret void138}139 140define amdgpu_kernel void @i32_16_elements(ptr %out) #0 {141; DEFAULT-LABEL: define amdgpu_kernel void @i32_16_elements(142; DEFAULT-SAME: ptr [[OUT:%.*]]) #[[ATTR0]] {143; DEFAULT-NEXT: [[X:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()144; DEFAULT-NEXT: [[Y:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.y()145; DEFAULT-NEXT: [[C1:%.*]] = icmp uge i32 [[X]], 3146; DEFAULT-NEXT: [[C2:%.*]] = icmp uge i32 [[Y]], 3147; DEFAULT-NEXT: [[SEL1:%.*]] = select i1 [[C1]], i32 1, i32 2148; DEFAULT-NEXT: [[SEL2:%.*]] = select i1 [[C2]], i32 0, i32 [[SEL1]]149; DEFAULT-NEXT: [[ALLOCA:%.*]] = freeze <16 x i32> poison150; DEFAULT-NEXT: [[TMP1:%.*]] = extractelement <16 x i32> <i32 42, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 43>, i32 [[SEL2]]151; DEFAULT-NEXT: store i32 [[TMP1]], ptr [[OUT]], align 4152; DEFAULT-NEXT: ret void153;154; RATIO2-LABEL: define amdgpu_kernel void @i32_16_elements(155; RATIO2-SAME: ptr [[OUT:%.*]]) #[[ATTR0]] {156; RATIO2-NEXT: [[X:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()157; RATIO2-NEXT: [[Y:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.y()158; RATIO2-NEXT: [[C1:%.*]] = icmp uge i32 [[X]], 3159; RATIO2-NEXT: [[C2:%.*]] = icmp uge i32 [[Y]], 3160; RATIO2-NEXT: [[SEL1:%.*]] = select i1 [[C1]], i32 1, i32 2161; RATIO2-NEXT: [[SEL2:%.*]] = select i1 [[C2]], i32 0, i32 [[SEL1]]162; RATIO2-NEXT: [[ALLOCA:%.*]] = freeze <16 x i32> poison163; RATIO2-NEXT: [[TMP1:%.*]] = extractelement <16 x i32> <i32 42, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 43>, i32 [[SEL2]]164; RATIO2-NEXT: store i32 [[TMP1]], ptr [[OUT]], align 4165; RATIO2-NEXT: ret void166;167; RATIO8-LABEL: define amdgpu_kernel void @i32_16_elements(168; RATIO8-SAME: ptr [[OUT:%.*]]) #[[ATTR0]] {169; RATIO8-NEXT: [[X:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()170; RATIO8-NEXT: [[Y:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.y()171; RATIO8-NEXT: [[C1:%.*]] = icmp uge i32 [[X]], 3172; RATIO8-NEXT: [[C2:%.*]] = icmp uge i32 [[Y]], 3173; RATIO8-NEXT: [[SEL1:%.*]] = select i1 [[C1]], i32 1, i32 2174; RATIO8-NEXT: [[SEL2:%.*]] = select i1 [[C2]], i32 0, i32 [[SEL1]]175; RATIO8-NEXT: [[ALLOCA:%.*]] = alloca [16 x i32], align 16, addrspace(5)176; RATIO8-NEXT: call void @llvm.memset.p5.i32(ptr addrspace(5) [[ALLOCA]], i8 0, i32 64, i1 false)177; RATIO8-NEXT: [[GEP_0:%.*]] = getelementptr inbounds [16 x i32], ptr addrspace(5) [[ALLOCA]], i32 0, i32 0178; RATIO8-NEXT: [[GEP_1:%.*]] = getelementptr inbounds [16 x i32], ptr addrspace(5) [[ALLOCA]], i32 0, i32 15179; RATIO8-NEXT: store i32 42, ptr addrspace(5) [[GEP_0]], align 4180; RATIO8-NEXT: store i32 43, ptr addrspace(5) [[GEP_1]], align 4181; RATIO8-NEXT: [[GEP:%.*]] = getelementptr inbounds [16 x i32], ptr addrspace(5) [[ALLOCA]], i32 0, i32 [[SEL2]]182; RATIO8-NEXT: [[LOAD:%.*]] = load i32, ptr addrspace(5) [[GEP]], align 4183; RATIO8-NEXT: store i32 [[LOAD]], ptr [[OUT]], align 4184; RATIO8-NEXT: ret void185;186 %x = tail call i32 @llvm.amdgcn.workitem.id.x()187 %y = tail call i32 @llvm.amdgcn.workitem.id.y()188 %c1 = icmp uge i32 %x, 3189 %c2 = icmp uge i32 %y, 3190 %sel1 = select i1 %c1, i32 1, i32 2191 %sel2 = select i1 %c2, i32 0, i32 %sel1192 %alloca = alloca [16 x i32], align 16, addrspace(5)193 call void @llvm.memset.p5.i32(ptr addrspace(5) %alloca, i8 0, i32 64, i1 false)194 %gep.0 = getelementptr inbounds [16 x i32], ptr addrspace(5) %alloca, i32 0, i32 0195 %gep.1 = getelementptr inbounds [16 x i32], ptr addrspace(5) %alloca, i32 0, i32 15196 store i32 42, ptr addrspace(5) %gep.0197 store i32 43, ptr addrspace(5) %gep.1198 %gep = getelementptr inbounds [16 x i32], ptr addrspace(5) %alloca, i32 0, i32 %sel2199 %load = load i32, ptr addrspace(5) %gep200 store i32 %load, ptr %out201 ret void202}203 204define amdgpu_kernel void @i32_16_elements_attrib(ptr %out) #2 {205; DEFAULT-LABEL: define amdgpu_kernel void @i32_16_elements_attrib(206; DEFAULT-SAME: ptr [[OUT:%.*]]) #[[ATTR2:[0-9]+]] {207; DEFAULT-NEXT: [[X:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()208; DEFAULT-NEXT: [[Y:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.y()209; DEFAULT-NEXT: [[C1:%.*]] = icmp uge i32 [[X]], 3210; DEFAULT-NEXT: [[C2:%.*]] = icmp uge i32 [[Y]], 3211; DEFAULT-NEXT: [[SEL1:%.*]] = select i1 [[C1]], i32 1, i32 2212; DEFAULT-NEXT: [[SEL2:%.*]] = select i1 [[C2]], i32 0, i32 [[SEL1]]213; DEFAULT-NEXT: [[ALLOCA:%.*]] = alloca [16 x i32], align 16, addrspace(5)214; DEFAULT-NEXT: call void @llvm.memset.p5.i32(ptr addrspace(5) [[ALLOCA]], i8 0, i32 64, i1 false)215; DEFAULT-NEXT: [[GEP_0:%.*]] = getelementptr inbounds [16 x i32], ptr addrspace(5) [[ALLOCA]], i32 0, i32 0216; DEFAULT-NEXT: [[GEP_1:%.*]] = getelementptr inbounds [16 x i32], ptr addrspace(5) [[ALLOCA]], i32 0, i32 15217; DEFAULT-NEXT: store i32 42, ptr addrspace(5) [[GEP_0]], align 4218; DEFAULT-NEXT: store i32 43, ptr addrspace(5) [[GEP_1]], align 4219; DEFAULT-NEXT: [[GEP:%.*]] = getelementptr inbounds [16 x i32], ptr addrspace(5) [[ALLOCA]], i32 0, i32 [[SEL2]]220; DEFAULT-NEXT: [[LOAD:%.*]] = load i32, ptr addrspace(5) [[GEP]], align 4221; DEFAULT-NEXT: store i32 [[LOAD]], ptr [[OUT]], align 4222; DEFAULT-NEXT: ret void223;224; RATIO2-LABEL: define amdgpu_kernel void @i32_16_elements_attrib(225; RATIO2-SAME: ptr [[OUT:%.*]]) #[[ATTR2:[0-9]+]] {226; RATIO2-NEXT: [[X:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()227; RATIO2-NEXT: [[Y:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.y()228; RATIO2-NEXT: [[C1:%.*]] = icmp uge i32 [[X]], 3229; RATIO2-NEXT: [[C2:%.*]] = icmp uge i32 [[Y]], 3230; RATIO2-NEXT: [[SEL1:%.*]] = select i1 [[C1]], i32 1, i32 2231; RATIO2-NEXT: [[SEL2:%.*]] = select i1 [[C2]], i32 0, i32 [[SEL1]]232; RATIO2-NEXT: [[ALLOCA:%.*]] = freeze <16 x i32> poison233; RATIO2-NEXT: [[TMP1:%.*]] = extractelement <16 x i32> <i32 42, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 0, i32 43>, i32 [[SEL2]]234; RATIO2-NEXT: store i32 [[TMP1]], ptr [[OUT]], align 4235; RATIO2-NEXT: ret void236;237; RATIO8-LABEL: define amdgpu_kernel void @i32_16_elements_attrib(238; RATIO8-SAME: ptr [[OUT:%.*]]) #[[ATTR2:[0-9]+]] {239; RATIO8-NEXT: [[X:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()240; RATIO8-NEXT: [[Y:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.y()241; RATIO8-NEXT: [[C1:%.*]] = icmp uge i32 [[X]], 3242; RATIO8-NEXT: [[C2:%.*]] = icmp uge i32 [[Y]], 3243; RATIO8-NEXT: [[SEL1:%.*]] = select i1 [[C1]], i32 1, i32 2244; RATIO8-NEXT: [[SEL2:%.*]] = select i1 [[C2]], i32 0, i32 [[SEL1]]245; RATIO8-NEXT: [[ALLOCA:%.*]] = alloca [16 x i32], align 16, addrspace(5)246; RATIO8-NEXT: call void @llvm.memset.p5.i32(ptr addrspace(5) [[ALLOCA]], i8 0, i32 64, i1 false)247; RATIO8-NEXT: [[GEP_0:%.*]] = getelementptr inbounds [16 x i32], ptr addrspace(5) [[ALLOCA]], i32 0, i32 0248; RATIO8-NEXT: [[GEP_1:%.*]] = getelementptr inbounds [16 x i32], ptr addrspace(5) [[ALLOCA]], i32 0, i32 15249; RATIO8-NEXT: store i32 42, ptr addrspace(5) [[GEP_0]], align 4250; RATIO8-NEXT: store i32 43, ptr addrspace(5) [[GEP_1]], align 4251; RATIO8-NEXT: [[GEP:%.*]] = getelementptr inbounds [16 x i32], ptr addrspace(5) [[ALLOCA]], i32 0, i32 [[SEL2]]252; RATIO8-NEXT: [[LOAD:%.*]] = load i32, ptr addrspace(5) [[GEP]], align 4253; RATIO8-NEXT: store i32 [[LOAD]], ptr [[OUT]], align 4254; RATIO8-NEXT: ret void255;256 %x = tail call i32 @llvm.amdgcn.workitem.id.x()257 %y = tail call i32 @llvm.amdgcn.workitem.id.y()258 %c1 = icmp uge i32 %x, 3259 %c2 = icmp uge i32 %y, 3260 %sel1 = select i1 %c1, i32 1, i32 2261 %sel2 = select i1 %c2, i32 0, i32 %sel1262 %alloca = alloca [16 x i32], align 16, addrspace(5)263 call void @llvm.memset.p5.i32(ptr addrspace(5) %alloca, i8 0, i32 64, i1 false)264 %gep.0 = getelementptr inbounds [16 x i32], ptr addrspace(5) %alloca, i32 0, i32 0265 %gep.1 = getelementptr inbounds [16 x i32], ptr addrspace(5) %alloca, i32 0, i32 15266 store i32 42, ptr addrspace(5) %gep.0267 store i32 43, ptr addrspace(5) %gep.1268 %gep = getelementptr inbounds [16 x i32], ptr addrspace(5) %alloca, i32 0, i32 %sel2269 %load = load i32, ptr addrspace(5) %gep270 store i32 %load, ptr %out271 ret void272}273 274declare i32 @llvm.amdgcn.workitem.id.x()275declare i32 @llvm.amdgcn.workitem.id.y()276declare void @llvm.memset.p5.i32(ptr addrspace(5) nocapture writeonly, i8, i32, i1 immarg)277 278attributes #0 = { nounwind "amdgpu-promote-alloca-to-vector-max-regs"="24" "amdgpu-waves-per-eu"="4,4" }279attributes #1 = { nounwind "amdgpu-promote-alloca-to-vector-max-regs"="24" "amdgpu-waves-per-eu"="4,4" "amdgpu-promote-alloca-to-vector-vgpr-ratio"="2" }280attributes #2 = { nounwind "amdgpu-promote-alloca-to-vector-max-regs"="24" "amdgpu-waves-per-eu"="4,4" "amdgpu-promote-alloca-to-vector-vgpr-ratio"="8" }281;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:282; BASE: {{.*}}283