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1; NOTE: Assertions have been autogenerated by utils/update_test_checks.py2; RUN: opt -S -mtriple=amdgcn-amd-amdhsa < %s -amdgpu-promote-kernel-arguments -infer-address-spaces | FileCheck %s3; RUN: opt -S -mtriple=amdgcn-amd-amdhsa < %s -passes=amdgpu-promote-kernel-arguments,infer-address-spaces | FileCheck %s4; RUN: opt -S -mtriple=amdgcn-amd-amdhsa < %s -amdgpu-promote-kernel-arguments -infer-address-spaces | llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 | FileCheck -check-prefix=GCN %s5 6; GCN-LABEL: ptr_nest_3:7; GCN-COUNT-2: global_load_dwordx28; GCN: global_store_dword9define amdgpu_kernel void @ptr_nest_3(ptr addrspace(1) nocapture readonly %Arg) {10; CHECK-LABEL: @ptr_nest_3(11; CHECK-NEXT: entry:12; CHECK-NEXT: [[I:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()13; CHECK-NEXT: [[P1:%.*]] = getelementptr inbounds ptr, ptr addrspace(1) [[ARG:%.*]], i32 [[I]]14; CHECK-NEXT: [[P2:%.*]] = load ptr, ptr addrspace(1) [[P1]], align 8, !amdgpu.noclobber [[META0:![0-9]+]]15; CHECK-NEXT: [[P2_GLOBAL:%.*]] = addrspacecast ptr [[P2]] to ptr addrspace(1)16; CHECK-NEXT: [[P3:%.*]] = load ptr, ptr addrspace(1) [[P2_GLOBAL]], align 8, !amdgpu.noclobber [[META0]]17; CHECK-NEXT: [[P3_GLOBAL:%.*]] = addrspacecast ptr [[P3]] to ptr addrspace(1)18; CHECK-NEXT: store float 0.000000e+00, ptr addrspace(1) [[P3_GLOBAL]], align 419; CHECK-NEXT: ret void20;21entry:22 %i = tail call i32 @llvm.amdgcn.workitem.id.x()23 %p1 = getelementptr inbounds ptr, ptr addrspace(1) %Arg, i32 %i24 %p2 = load ptr, ptr addrspace(1) %p1, align 825 %p3 = load ptr, ptr %p2, align 826 store float 0.000000e+00, ptr %p3, align 427 ret void28}29 30; GCN-LABEL: ptr_bitcast:31; GCN: global_load_dwordx232; GCN: global_store_dword33define amdgpu_kernel void @ptr_bitcast(ptr nocapture readonly %Arg) {34; CHECK-LABEL: @ptr_bitcast(35; CHECK-NEXT: entry:36; CHECK-NEXT: [[ARG_GLOBAL:%.*]] = addrspacecast ptr [[ARG:%.*]] to ptr addrspace(1)37; CHECK-NEXT: [[I:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()38; CHECK-NEXT: [[P1:%.*]] = getelementptr inbounds ptr, ptr addrspace(1) [[ARG_GLOBAL]], i32 [[I]]39; CHECK-NEXT: [[P2:%.*]] = load ptr, ptr addrspace(1) [[P1]], align 8, !amdgpu.noclobber [[META0]]40; CHECK-NEXT: [[P2_GLOBAL:%.*]] = addrspacecast ptr [[P2]] to ptr addrspace(1)41; CHECK-NEXT: store i32 0, ptr addrspace(1) [[P2_GLOBAL]], align 442; CHECK-NEXT: ret void43;44entry:45 %i = tail call i32 @llvm.amdgcn.workitem.id.x()46 %p1 = getelementptr inbounds ptr, ptr %Arg, i32 %i47 %p2 = load ptr, ptr %p1, align 848 store i32 0, ptr %p2, align 449 ret void50}51 52%struct.S = type { ptr }53 54; GCN-LABEL: ptr_in_struct:55; GCN: s_load_dwordx256; GCN: global_store_dword57define amdgpu_kernel void @ptr_in_struct(ptr addrspace(1) nocapture readonly %Arg) {58; CHECK-LABEL: @ptr_in_struct(59; CHECK-NEXT: entry:60; CHECK-NEXT: [[P1:%.*]] = load ptr, ptr addrspace(1) [[ARG:%.*]], align 8, !amdgpu.noclobber [[META0]]61; CHECK-NEXT: [[P1_GLOBAL:%.*]] = addrspacecast ptr [[P1]] to ptr addrspace(1)62; CHECK-NEXT: [[ID:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()63; CHECK-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[P1_GLOBAL]], i32 [[ID]]64; CHECK-NEXT: store float 0.000000e+00, ptr addrspace(1) [[ARRAYIDX]], align 465; CHECK-NEXT: ret void66;67entry:68 %p1 = load ptr, ptr addrspace(1) %Arg, align 869 %id = tail call i32 @llvm.amdgcn.workitem.id.x()70 %arrayidx = getelementptr inbounds float, ptr %p1, i32 %id71 store float 0.000000e+00, ptr %arrayidx, align 472 ret void73}74 75@LDS = internal unnamed_addr addrspace(3) global [4 x float] poison, align 1676 77; GCN-LABEL: flat_ptr_arg:78; GCN-COUNT-2: global_load_dwordx279; GCN: global_load_dwordx480; GCN: global_store_dword81define amdgpu_kernel void @flat_ptr_arg(ptr nocapture readonly noalias %Arg, ptr nocapture noalias %Out, i32 %X) {82; CHECK-LABEL: @flat_ptr_arg(83; CHECK-NEXT: entry:84; CHECK-NEXT: [[OUT_GLOBAL:%.*]] = addrspacecast ptr [[OUT:%.*]] to ptr addrspace(1)85; CHECK-NEXT: [[ARG_GLOBAL:%.*]] = addrspacecast ptr [[ARG:%.*]] to ptr addrspace(1)86; CHECK-NEXT: [[I:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()87; CHECK-NEXT: [[IDXPROM:%.*]] = zext i32 [[I]] to i6488; CHECK-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds ptr, ptr addrspace(1) [[ARG_GLOBAL]], i64 [[IDXPROM]]89; CHECK-NEXT: [[I1:%.*]] = load ptr, ptr addrspace(1) [[ARRAYIDX10]], align 8, !amdgpu.noclobber [[META0]]90; CHECK-NEXT: [[I1_GLOBAL:%.*]] = addrspacecast ptr [[I1]] to ptr addrspace(1)91; CHECK-NEXT: [[I2:%.*]] = load float, ptr addrspace(1) [[I1_GLOBAL]], align 4, !amdgpu.noclobber [[META0]]92; CHECK-NEXT: [[ARRAYIDX512:%.*]] = getelementptr inbounds [4 x float], ptr addrspace(3) @LDS, i32 0, i32 [[X:%.*]]93; CHECK-NEXT: store float [[I2]], ptr addrspace(3) [[ARRAYIDX512]], align 494; CHECK-NEXT: [[ARRAYIDX3_1:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[I1_GLOBAL]], i64 195; CHECK-NEXT: [[I3:%.*]] = load float, ptr addrspace(1) [[ARRAYIDX3_1]], align 496; CHECK-NEXT: [[ADD_1:%.*]] = add nsw i32 [[X]], 197; CHECK-NEXT: [[ARRAYIDX512_1:%.*]] = getelementptr inbounds [4 x float], ptr addrspace(3) @LDS, i32 0, i32 [[ADD_1]]98; CHECK-NEXT: store float [[I3]], ptr addrspace(3) [[ARRAYIDX512_1]], align 499; CHECK-NEXT: [[ARRAYIDX3_2:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[I1_GLOBAL]], i64 2100; CHECK-NEXT: [[I4:%.*]] = load float, ptr addrspace(1) [[ARRAYIDX3_2]], align 4101; CHECK-NEXT: [[ADD_2:%.*]] = add nsw i32 [[X]], 2102; CHECK-NEXT: [[ARRAYIDX512_2:%.*]] = getelementptr inbounds [4 x float], ptr addrspace(3) @LDS, i32 0, i32 [[ADD_2]]103; CHECK-NEXT: store float [[I4]], ptr addrspace(3) [[ARRAYIDX512_2]], align 4104; CHECK-NEXT: [[ARRAYIDX3_3:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[I1_GLOBAL]], i64 3105; CHECK-NEXT: [[I5:%.*]] = load float, ptr addrspace(1) [[ARRAYIDX3_3]], align 4106; CHECK-NEXT: [[ADD_3:%.*]] = add nsw i32 [[X]], 3107; CHECK-NEXT: [[ARRAYIDX512_3:%.*]] = getelementptr inbounds [4 x float], ptr addrspace(3) @LDS, i32 0, i32 [[ADD_3]]108; CHECK-NEXT: store float [[I5]], ptr addrspace(3) [[ARRAYIDX512_3]], align 4109; CHECK-NEXT: [[SUB:%.*]] = add nsw i32 [[X]], -1110; CHECK-NEXT: [[ARRAYIDX711:%.*]] = getelementptr inbounds [4 x float], ptr addrspace(3) @LDS, i32 0, i32 [[SUB]]111; CHECK-NEXT: [[I6:%.*]] = load float, ptr addrspace(3) [[ARRAYIDX711]], align 4112; CHECK-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds ptr, ptr addrspace(1) [[OUT_GLOBAL]], i64 [[IDXPROM]]113; CHECK-NEXT: [[I7:%.*]] = load ptr, ptr addrspace(1) [[ARRAYIDX11]], align 8, !amdgpu.noclobber [[META0]]114; CHECK-NEXT: [[I7_GLOBAL:%.*]] = addrspacecast ptr [[I7]] to ptr addrspace(1)115; CHECK-NEXT: [[IDXPROM8:%.*]] = sext i32 [[X]] to i64116; CHECK-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[I7_GLOBAL]], i64 [[IDXPROM8]]117; CHECK-NEXT: store float [[I6]], ptr addrspace(1) [[ARRAYIDX9]], align 4118; CHECK-NEXT: ret void119;120entry:121 %i = tail call i32 @llvm.amdgcn.workitem.id.x()122 %idxprom = zext i32 %i to i64123 %arrayidx10 = getelementptr inbounds ptr, ptr %Arg, i64 %idxprom124 %i1 = load ptr, ptr %arrayidx10, align 8125 %i2 = load float, ptr %i1, align 4126 %arrayidx512 = getelementptr inbounds [4 x float], ptr addrspace(3) @LDS, i32 0, i32 %X127 store float %i2, ptr addrspace(3) %arrayidx512, align 4128 %arrayidx3.1 = getelementptr inbounds float, ptr %i1, i64 1129 %i3 = load float, ptr %arrayidx3.1, align 4130 %add.1 = add nsw i32 %X, 1131 %arrayidx512.1 = getelementptr inbounds [4 x float], ptr addrspace(3) @LDS, i32 0, i32 %add.1132 store float %i3, ptr addrspace(3) %arrayidx512.1, align 4133 %arrayidx3.2 = getelementptr inbounds float, ptr %i1, i64 2134 %i4 = load float, ptr %arrayidx3.2, align 4135 %add.2 = add nsw i32 %X, 2136 %arrayidx512.2 = getelementptr inbounds [4 x float], ptr addrspace(3) @LDS, i32 0, i32 %add.2137 store float %i4, ptr addrspace(3) %arrayidx512.2, align 4138 %arrayidx3.3 = getelementptr inbounds float, ptr %i1, i64 3139 %i5 = load float, ptr %arrayidx3.3, align 4140 %add.3 = add nsw i32 %X, 3141 %arrayidx512.3 = getelementptr inbounds [4 x float], ptr addrspace(3) @LDS, i32 0, i32 %add.3142 store float %i5, ptr addrspace(3) %arrayidx512.3, align 4143 %sub = add nsw i32 %X, -1144 %arrayidx711 = getelementptr inbounds [4 x float], ptr addrspace(3) @LDS, i32 0, i32 %sub145 %i6 = load float, ptr addrspace(3) %arrayidx711, align 4146 %arrayidx11 = getelementptr inbounds ptr, ptr %Out, i64 %idxprom147 %i7 = load ptr, ptr %arrayidx11, align 8148 %idxprom8 = sext i32 %X to i64149 %arrayidx9 = getelementptr inbounds float, ptr %i7, i64 %idxprom8150 store float %i6, ptr %arrayidx9, align 4151 ret void152}153 154; GCN-LABEL: global_ptr_arg:155; GCN: global_load_dwordx2156; GCN: global_load_dwordx4157; GCN: global_store_dword158define amdgpu_kernel void @global_ptr_arg(ptr addrspace(1) nocapture readonly %Arg, i32 %X) {159; CHECK-LABEL: @global_ptr_arg(160; CHECK-NEXT: entry:161; CHECK-NEXT: [[I:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()162; CHECK-NEXT: [[IDXPROM:%.*]] = zext i32 [[I]] to i64163; CHECK-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds ptr, ptr addrspace(1) [[ARG:%.*]], i64 [[IDXPROM]]164; CHECK-NEXT: [[I1:%.*]] = load ptr, ptr addrspace(1) [[ARRAYIDX10]], align 8, !amdgpu.noclobber [[META0]]165; CHECK-NEXT: [[I1_GLOBAL:%.*]] = addrspacecast ptr [[I1]] to ptr addrspace(1)166; CHECK-NEXT: [[I2:%.*]] = load float, ptr addrspace(1) [[I1_GLOBAL]], align 4, !amdgpu.noclobber [[META0]]167; CHECK-NEXT: [[ARRAYIDX512:%.*]] = getelementptr inbounds [4 x float], ptr addrspace(3) @LDS, i32 0, i32 [[X:%.*]]168; CHECK-NEXT: store float [[I2]], ptr addrspace(3) [[ARRAYIDX512]], align 4169; CHECK-NEXT: [[ARRAYIDX3_1:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[I1_GLOBAL]], i64 1170; CHECK-NEXT: [[I3:%.*]] = load float, ptr addrspace(1) [[ARRAYIDX3_1]], align 4171; CHECK-NEXT: [[ADD_1:%.*]] = add nsw i32 [[X]], 1172; CHECK-NEXT: [[ARRAYIDX512_1:%.*]] = getelementptr inbounds [4 x float], ptr addrspace(3) @LDS, i32 0, i32 [[ADD_1]]173; CHECK-NEXT: store float [[I3]], ptr addrspace(3) [[ARRAYIDX512_1]], align 4174; CHECK-NEXT: [[ARRAYIDX3_2:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[I1_GLOBAL]], i64 2175; CHECK-NEXT: [[I4:%.*]] = load float, ptr addrspace(1) [[ARRAYIDX3_2]], align 4176; CHECK-NEXT: [[ADD_2:%.*]] = add nsw i32 [[X]], 2177; CHECK-NEXT: [[ARRAYIDX512_2:%.*]] = getelementptr inbounds [4 x float], ptr addrspace(3) @LDS, i32 0, i32 [[ADD_2]]178; CHECK-NEXT: store float [[I4]], ptr addrspace(3) [[ARRAYIDX512_2]], align 4179; CHECK-NEXT: [[ARRAYIDX3_3:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[I1_GLOBAL]], i64 3180; CHECK-NEXT: [[I5:%.*]] = load float, ptr addrspace(1) [[ARRAYIDX3_3]], align 4181; CHECK-NEXT: [[ADD_3:%.*]] = add nsw i32 [[X]], 3182; CHECK-NEXT: [[ARRAYIDX512_3:%.*]] = getelementptr inbounds [4 x float], ptr addrspace(3) @LDS, i32 0, i32 [[ADD_3]]183; CHECK-NEXT: store float [[I5]], ptr addrspace(3) [[ARRAYIDX512_3]], align 4184; CHECK-NEXT: [[SUB:%.*]] = add nsw i32 [[X]], -1185; CHECK-NEXT: [[ARRAYIDX711:%.*]] = getelementptr inbounds [4 x float], ptr addrspace(3) @LDS, i32 0, i32 [[SUB]]186; CHECK-NEXT: [[I6:%.*]] = load float, ptr addrspace(3) [[ARRAYIDX711]], align 4187; CHECK-NEXT: [[IDXPROM8:%.*]] = sext i32 [[X]] to i64188; CHECK-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[I1_GLOBAL]], i64 [[IDXPROM8]]189; CHECK-NEXT: store float [[I6]], ptr addrspace(1) [[ARRAYIDX9]], align 4190; CHECK-NEXT: ret void191;192entry:193 %i = tail call i32 @llvm.amdgcn.workitem.id.x()194 %idxprom = zext i32 %i to i64195 %arrayidx10 = getelementptr inbounds ptr, ptr addrspace(1) %Arg, i64 %idxprom196 %i1 = load ptr, ptr addrspace(1) %arrayidx10, align 8197 %i2 = load float, ptr %i1, align 4198 %arrayidx512 = getelementptr inbounds [4 x float], ptr addrspace(3) @LDS, i32 0, i32 %X199 store float %i2, ptr addrspace(3) %arrayidx512, align 4200 %arrayidx3.1 = getelementptr inbounds float, ptr %i1, i64 1201 %i3 = load float, ptr %arrayidx3.1, align 4202 %add.1 = add nsw i32 %X, 1203 %arrayidx512.1 = getelementptr inbounds [4 x float], ptr addrspace(3) @LDS, i32 0, i32 %add.1204 store float %i3, ptr addrspace(3) %arrayidx512.1, align 4205 %arrayidx3.2 = getelementptr inbounds float, ptr %i1, i64 2206 %i4 = load float, ptr %arrayidx3.2, align 4207 %add.2 = add nsw i32 %X, 2208 %arrayidx512.2 = getelementptr inbounds [4 x float], ptr addrspace(3) @LDS, i32 0, i32 %add.2209 store float %i4, ptr addrspace(3) %arrayidx512.2, align 4210 %arrayidx3.3 = getelementptr inbounds float, ptr %i1, i64 3211 %i5 = load float, ptr %arrayidx3.3, align 4212 %add.3 = add nsw i32 %X, 3213 %arrayidx512.3 = getelementptr inbounds [4 x float], ptr addrspace(3) @LDS, i32 0, i32 %add.3214 store float %i5, ptr addrspace(3) %arrayidx512.3, align 4215 %sub = add nsw i32 %X, -1216 %arrayidx711 = getelementptr inbounds [4 x float], ptr addrspace(3) @LDS, i32 0, i32 %sub217 %i6 = load float, ptr addrspace(3) %arrayidx711, align 4218 %idxprom8 = sext i32 %X to i64219 %arrayidx9 = getelementptr inbounds float, ptr %i1, i64 %idxprom8220 store float %i6, ptr %arrayidx9, align 4221 ret void222}223 224; GCN-LABEL: global_ptr_arg_clobbered:225; GCN: global_store_dwordx2226; GCN: global_load_dwordx2227; GCN: flat_load_dword228; GCN: flat_store_dword229define amdgpu_kernel void @global_ptr_arg_clobbered(ptr addrspace(1) nocapture readonly %Arg, i32 %X) {230; CHECK-LABEL: @global_ptr_arg_clobbered(231; CHECK-NEXT: entry:232; CHECK-NEXT: [[I:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()233; CHECK-NEXT: [[IDXPROM:%.*]] = zext i32 [[I]] to i64234; CHECK-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds ptr, ptr addrspace(1) [[ARG:%.*]], i64 [[IDXPROM]]235; CHECK-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds ptr, ptr addrspace(1) [[ARRAYIDX10]], i32 [[X:%.*]]236; CHECK-NEXT: store ptr null, ptr addrspace(1) [[ARRAYIDX11]], align 4237; CHECK-NEXT: [[I1:%.*]] = load ptr, ptr addrspace(1) [[ARRAYIDX10]], align 8238; CHECK-NEXT: [[I2:%.*]] = load float, ptr [[I1]], align 4239; CHECK-NEXT: [[ARRAYIDX512:%.*]] = getelementptr inbounds [4 x float], ptr addrspace(3) @LDS, i32 0, i32 [[X]]240; CHECK-NEXT: store float [[I2]], ptr addrspace(3) [[ARRAYIDX512]], align 4241; CHECK-NEXT: [[SUB:%.*]] = add nsw i32 [[X]], -1242; CHECK-NEXT: [[ARRAYIDX711:%.*]] = getelementptr inbounds [4 x float], ptr addrspace(3) @LDS, i32 0, i32 [[SUB]]243; CHECK-NEXT: [[I6:%.*]] = load float, ptr addrspace(3) [[ARRAYIDX711]], align 4244; CHECK-NEXT: [[IDXPROM8:%.*]] = sext i32 [[X]] to i64245; CHECK-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr [[I1]], i64 [[IDXPROM8]]246; CHECK-NEXT: store float [[I6]], ptr [[ARRAYIDX9]], align 4247; CHECK-NEXT: ret void248;249entry:250 %i = tail call i32 @llvm.amdgcn.workitem.id.x()251 %idxprom = zext i32 %i to i64252 %arrayidx10 = getelementptr inbounds ptr, ptr addrspace(1) %Arg, i64 %idxprom253 %arrayidx11 = getelementptr inbounds ptr, ptr addrspace(1) %arrayidx10, i32 %X254 store ptr null, ptr addrspace(1) %arrayidx11, align 4255 %i1 = load ptr, ptr addrspace(1) %arrayidx10, align 8256 %i2 = load float, ptr %i1, align 4257 %arrayidx512 = getelementptr inbounds [4 x float], ptr addrspace(3) @LDS, i32 0, i32 %X258 store float %i2, ptr addrspace(3) %arrayidx512, align 4259 %sub = add nsw i32 %X, -1260 %arrayidx711 = getelementptr inbounds [4 x float], ptr addrspace(3) @LDS, i32 0, i32 %sub261 %i6 = load float, ptr addrspace(3) %arrayidx711, align 4262 %idxprom8 = sext i32 %X to i64263 %arrayidx9 = getelementptr inbounds float, ptr %i1, i64 %idxprom8264 store float %i6, ptr %arrayidx9, align 4265 ret void266}267 268; GCN-LABEL: global_ptr_arg_clobbered_after_load:269; GCN: global_load_dwordx2270; GCN: global_store_dwordx2271; GCN: global_load_dword272; GCN: global_store_dword273define amdgpu_kernel void @global_ptr_arg_clobbered_after_load(ptr addrspace(1) nocapture readonly %Arg, i32 %X) {274; CHECK-LABEL: @global_ptr_arg_clobbered_after_load(275; CHECK-NEXT: entry:276; CHECK-NEXT: [[I:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()277; CHECK-NEXT: [[IDXPROM:%.*]] = zext i32 [[I]] to i64278; CHECK-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds ptr, ptr addrspace(1) [[ARG:%.*]], i64 [[IDXPROM]]279; CHECK-NEXT: [[I1:%.*]] = load ptr, ptr addrspace(1) [[ARRAYIDX10]], align 8, !amdgpu.noclobber [[META0]]280; CHECK-NEXT: [[I1_GLOBAL:%.*]] = addrspacecast ptr [[I1]] to ptr addrspace(1)281; CHECK-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds ptr, ptr addrspace(1) [[ARRAYIDX10]], i32 [[X:%.*]]282; CHECK-NEXT: store ptr null, ptr addrspace(1) [[ARRAYIDX11]], align 4283; CHECK-NEXT: [[I2:%.*]] = load float, ptr addrspace(1) [[I1_GLOBAL]], align 4284; CHECK-NEXT: [[ARRAYIDX512:%.*]] = getelementptr inbounds [4 x float], ptr addrspace(3) @LDS, i32 0, i32 [[X]]285; CHECK-NEXT: store float [[I2]], ptr addrspace(3) [[ARRAYIDX512]], align 4286; CHECK-NEXT: [[SUB:%.*]] = add nsw i32 [[X]], -1287; CHECK-NEXT: [[ARRAYIDX711:%.*]] = getelementptr inbounds [4 x float], ptr addrspace(3) @LDS, i32 0, i32 [[SUB]]288; CHECK-NEXT: [[I6:%.*]] = load float, ptr addrspace(3) [[ARRAYIDX711]], align 4289; CHECK-NEXT: [[IDXPROM8:%.*]] = sext i32 [[X]] to i64290; CHECK-NEXT: [[ARRAYIDX9:%.*]] = getelementptr inbounds float, ptr addrspace(1) [[I1_GLOBAL]], i64 [[IDXPROM8]]291; CHECK-NEXT: store float [[I6]], ptr addrspace(1) [[ARRAYIDX9]], align 4292; CHECK-NEXT: ret void293;294entry:295 %i = tail call i32 @llvm.amdgcn.workitem.id.x()296 %idxprom = zext i32 %i to i64297 %arrayidx10 = getelementptr inbounds ptr, ptr addrspace(1) %Arg, i64 %idxprom298 %i1 = load ptr, ptr addrspace(1) %arrayidx10, align 8299 %arrayidx11 = getelementptr inbounds ptr, ptr addrspace(1) %arrayidx10, i32 %X300 store ptr null, ptr addrspace(1) %arrayidx11, align 4301 %i2 = load float, ptr %i1, align 4302 %arrayidx512 = getelementptr inbounds [4 x float], ptr addrspace(3) @LDS, i32 0, i32 %X303 store float %i2, ptr addrspace(3) %arrayidx512, align 4304 %sub = add nsw i32 %X, -1305 %arrayidx711 = getelementptr inbounds [4 x float], ptr addrspace(3) @LDS, i32 0, i32 %sub306 %i6 = load float, ptr addrspace(3) %arrayidx711, align 4307 %idxprom8 = sext i32 %X to i64308 %arrayidx9 = getelementptr inbounds float, ptr %i1, i64 %idxprom8309 store float %i6, ptr %arrayidx9, align 4310 ret void311}312 313; GCN-LABEL: ptr_nest_3_barrier:314; GCN-COUNT-2: global_load_dwordx2315; GCN: global_store_dword316define amdgpu_kernel void @ptr_nest_3_barrier(ptr addrspace(1) nocapture readonly %Arg) {317; CHECK-LABEL: @ptr_nest_3_barrier(318; CHECK-NEXT: entry:319; CHECK-NEXT: [[I:%.*]] = tail call i32 @llvm.amdgcn.workitem.id.x()320; CHECK-NEXT: [[P1:%.*]] = getelementptr inbounds ptr, ptr addrspace(1) [[ARG:%.*]], i32 [[I]]321; CHECK-NEXT: tail call void @llvm.amdgcn.s.barrier()322; CHECK-NEXT: [[P2:%.*]] = load ptr, ptr addrspace(1) [[P1]], align 8, !amdgpu.noclobber [[META0]]323; CHECK-NEXT: [[P2_GLOBAL:%.*]] = addrspacecast ptr [[P2]] to ptr addrspace(1)324; CHECK-NEXT: [[P3:%.*]] = load ptr, ptr addrspace(1) [[P2_GLOBAL]], align 8, !amdgpu.noclobber [[META0]]325; CHECK-NEXT: [[P3_GLOBAL:%.*]] = addrspacecast ptr [[P3]] to ptr addrspace(1)326; CHECK-NEXT: store float 0.000000e+00, ptr addrspace(1) [[P3_GLOBAL]], align 4327; CHECK-NEXT: ret void328;329entry:330 %i = tail call i32 @llvm.amdgcn.workitem.id.x()331 %p1 = getelementptr inbounds ptr, ptr addrspace(1) %Arg, i32 %i332 tail call void @llvm.amdgcn.s.barrier()333 %p2 = load ptr, ptr addrspace(1) %p1, align 8334 %p3 = load ptr, ptr %p2, align 8335 store float 0.000000e+00, ptr %p3, align 4336 ret void337}338 339; GCN-LABEL: flat_ptr_nest_2:340; GCN: s_lshl_b64341; GCN: s_load_dwordx2342; GCN: global_store_dword343define amdgpu_kernel void @flat_ptr_nest_2(ptr nocapture readonly %Arg, i32 %i) {344; CHECK-LABEL: @flat_ptr_nest_2(345; CHECK-NEXT: entry:346; CHECK-NEXT: [[ARG_GLOBAL:%.*]] = addrspacecast ptr [[ARG:%.*]] to ptr addrspace(1)347; CHECK-NEXT: [[P1:%.*]] = getelementptr inbounds ptr, ptr addrspace(1) [[ARG_GLOBAL]], i32 [[I:%.*]]348; CHECK-NEXT: [[P2:%.*]] = load ptr, ptr addrspace(1) [[P1]], align 8, !amdgpu.noclobber [[META0]]349; CHECK-NEXT: [[P2_GLOBAL:%.*]] = addrspacecast ptr [[P2]] to ptr addrspace(1)350; CHECK-NEXT: store float 0.000000e+00, ptr addrspace(1) [[P2_GLOBAL]], align 4351; CHECK-NEXT: ret void352;353entry:354 %p1 = getelementptr inbounds ptr, ptr %Arg, i32 %i355 %p2 = load ptr, ptr %p1, align 8356 store float 0.000000e+00, ptr %p2, align 4357 ret void358}359 360; GCN-LABEL: const_ptr_nest_3:361; GCN: s_lshl_b64362; GCN: s_load_dwordx2363; GCN: s_load_dwordx2364; GCN: global_store_dword365define amdgpu_kernel void @const_ptr_nest_3(ptr addrspace(4) nocapture readonly %Arg, i32 %i) {366; CHECK-LABEL: @const_ptr_nest_3(367; CHECK-NEXT: entry:368; CHECK-NEXT: [[P1:%.*]] = getelementptr inbounds ptr addrspace(4), ptr addrspace(4) [[ARG:%.*]], i32 [[I:%.*]]369; CHECK-NEXT: [[P2:%.*]] = load ptr addrspace(4), ptr addrspace(4) [[P1]], align 8, !amdgpu.noclobber [[META0]]370; CHECK-NEXT: [[P3:%.*]] = load ptr, ptr addrspace(4) [[P2]], align 8, !amdgpu.noclobber [[META0]]371; CHECK-NEXT: [[TMP0:%.*]] = addrspacecast ptr [[P3]] to ptr addrspace(1)372; CHECK-NEXT: store float 0.000000e+00, ptr addrspace(1) [[TMP0]], align 4373; CHECK-NEXT: ret void374;375entry:376 %p1 = getelementptr inbounds ptr addrspace(4), ptr addrspace(4) %Arg, i32 %i377 %p2 = load ptr addrspace(4), ptr addrspace(4) %p1, align 8378 %p3 = load ptr, ptr addrspace(4) %p2, align 8379 store float 0.000000e+00, ptr %p3, align 4380 ret void381}382 383; GCN-LABEL: cast_from_const_const_ptr_nest_3:384; GCN: s_lshl_b64385; GCN: s_load_dwordx2386; GCN: s_load_dwordx2387; GCN: global_store_dword388define amdgpu_kernel void @cast_from_const_const_ptr_nest_3(ptr addrspace(4) nocapture readonly %Arg, i32 %i) {389; CHECK-LABEL: @cast_from_const_const_ptr_nest_3(390; CHECK-NEXT: entry:391; CHECK-NEXT: [[P1:%.*]] = getelementptr inbounds ptr addrspace(4), ptr addrspace(4) [[ARG:%.*]], i32 [[I:%.*]]392; CHECK-NEXT: [[P2:%.*]] = load ptr addrspace(4), ptr addrspace(4) [[P1]], align 8, !amdgpu.noclobber [[META0]]393; CHECK-NEXT: [[P3:%.*]] = load ptr, ptr addrspace(4) [[P2]], align 8, !amdgpu.noclobber [[META0]]394; CHECK-NEXT: [[P3_GLOBAL:%.*]] = addrspacecast ptr [[P3]] to ptr addrspace(1)395; CHECK-NEXT: store float 0.000000e+00, ptr addrspace(1) [[P3_GLOBAL]], align 4396; CHECK-NEXT: ret void397;398entry:399 %p1 = getelementptr inbounds ptr addrspace(4), ptr addrspace(4) %Arg, i32 %i400 %a1 = addrspacecast ptr addrspace(4) %p1 to ptr401 %p2 = load ptr addrspace(4), ptr %a1, align 8402 %a2 = addrspacecast ptr addrspace(4) %p2 to ptr403 %p3 = load ptr, ptr %a2, align 8404 store float 0.000000e+00, ptr %p3, align 4405 ret void406}407 408; GCN-LABEL: flat_ptr_volatile_load:409; GCN: s_lshl_b64410; GCN: flat_load_dwordx2411; GCN: global_store_dword412define amdgpu_kernel void @flat_ptr_volatile_load(ptr nocapture readonly %Arg, i32 %i) {413; CHECK-LABEL: @flat_ptr_volatile_load(414; CHECK-NEXT: entry:415; CHECK-NEXT: [[ARG_GLOBAL:%.*]] = addrspacecast ptr [[ARG:%.*]] to ptr addrspace(1)416; CHECK-NEXT: [[P1:%.*]] = getelementptr inbounds ptr, ptr addrspace(1) [[ARG_GLOBAL]], i32 [[I:%.*]]417; CHECK-NEXT: [[TMP0:%.*]] = addrspacecast ptr addrspace(1) [[P1]] to ptr418; CHECK-NEXT: [[P2:%.*]] = load volatile ptr, ptr [[TMP0]], align 8419; CHECK-NEXT: [[P2_GLOBAL:%.*]] = addrspacecast ptr [[P2]] to ptr addrspace(1)420; CHECK-NEXT: store float 0.000000e+00, ptr addrspace(1) [[P2_GLOBAL]], align 4421; CHECK-NEXT: ret void422;423entry:424 %p1 = getelementptr inbounds ptr, ptr %Arg, i32 %i425 %p2 = load volatile ptr, ptr %p1, align 8426 store float 0.000000e+00, ptr %p2, align 4427 ret void428}429 430; GCN-LABEL: flat_ptr_atomic_load:431; GCN: s_lshl_b64432; GCN: global_load_dwordx2433; GCN: global_store_dword434define amdgpu_kernel void @flat_ptr_atomic_load(ptr nocapture readonly %Arg, i32 %i) {435; CHECK-LABEL: @flat_ptr_atomic_load(436; CHECK-NEXT: entry:437; CHECK-NEXT: [[ARG_GLOBAL:%.*]] = addrspacecast ptr [[ARG:%.*]] to ptr addrspace(1)438; CHECK-NEXT: [[P1:%.*]] = getelementptr inbounds ptr, ptr addrspace(1) [[ARG_GLOBAL]], i32 [[I:%.*]]439; CHECK-NEXT: [[P2:%.*]] = load atomic ptr, ptr addrspace(1) [[P1]] monotonic, align 8440; CHECK-NEXT: [[P2_GLOBAL:%.*]] = addrspacecast ptr [[P2]] to ptr addrspace(1)441; CHECK-NEXT: store float 0.000000e+00, ptr addrspace(1) [[P2_GLOBAL]], align 4442; CHECK-NEXT: ret void443;444entry:445 %p1 = getelementptr inbounds ptr, ptr %Arg, i32 %i446 %p2 = load atomic ptr, ptr %p1 monotonic, align 8447 store float 0.000000e+00, ptr %p2, align 4448 ret void449}450 451; GCN-LABEL: cast_changing_pointee_type:452; GCN: s_lshl_b64453; GCN: s_load_dwordx2454; GCN: s_load_dwordx2455; GCN: global_store_dword456define amdgpu_kernel void @cast_changing_pointee_type(ptr addrspace(1) nocapture readonly %Arg, i32 %i) {457; CHECK-LABEL: @cast_changing_pointee_type(458; CHECK-NEXT: entry:459; CHECK-NEXT: [[P1:%.*]] = getelementptr inbounds ptr addrspace(1), ptr addrspace(1) [[ARG:%.*]], i32 [[I:%.*]]460; CHECK-NEXT: [[P2:%.*]] = load ptr addrspace(1), ptr addrspace(1) [[P1]], align 8, !amdgpu.noclobber [[META0]]461; CHECK-NEXT: [[P3:%.*]] = load ptr, ptr addrspace(1) [[P2]], align 8, !amdgpu.noclobber [[META0]]462; CHECK-NEXT: [[P3_GLOBAL:%.*]] = addrspacecast ptr [[P3]] to ptr addrspace(1)463; CHECK-NEXT: store float 0.000000e+00, ptr addrspace(1) [[P3_GLOBAL]], align 4464; CHECK-NEXT: ret void465;466entry:467 %p1 = getelementptr inbounds ptr addrspace(1), ptr addrspace(1) %Arg, i32 %i468 %a1 = addrspacecast ptr addrspace(1) %p1 to ptr469 %p2 = load ptr addrspace(1), ptr %a1, align 8470 %a2 = addrspacecast ptr addrspace(1) %p2 to ptr471 %p3 = load ptr, ptr %a2, align 8472 store float 0.000000e+00, ptr %p3, align 4473 ret void474}475 476declare i32 @llvm.amdgcn.workitem.id.x()477declare void @llvm.amdgcn.s.barrier()478