72 lines · plain
1; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefixes=GCN %s2 3; The type promotion for the vector loads v3i32/v3f32 into v4i32/v4f32 is enabled4; only when the alignment is 8-byte or higher.5; Otherwise, split the load into two separate loads (dwordx2 + dword).6; This type promotion on smaller aligned loads can cause a page fault error7; while accessing one extra dword beyond the buffer.8 9define protected amdgpu_kernel void @load_v3i32_align4(ptr addrspace(1) %arg) #0 {10; GCN-LABEL: load_v3i32_align4:11; GCN: ; %bb.0:12; GCN: s_waitcnt lgkmcnt(0)13; GCN-NEXT: s_load_dwordx2 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x014; GCN-NEXT: s_load_dword s{{[0-9]+}}, s[0:1], 0x815 %vec = load <3 x i32>, ptr addrspace(1) %arg, align 416 store <3 x i32> %vec, ptr addrspace(1) poison, align 417 ret void18}19 20define protected amdgpu_kernel void @load_v3i32_align8(ptr addrspace(1) %arg) #0 {21; GCN-LABEL: load_v3i32_align8:22; GCN: ; %bb.0:23; GCN: s_waitcnt lgkmcnt(0)24; GCN-NEXT: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[4:5], 0x025 %vec = load <3 x i32>, ptr addrspace(1) %arg, align 826 store <3 x i32> %vec, ptr addrspace(1) poison, align 827 ret void28}29 30define protected amdgpu_kernel void @load_v3i32_align16(ptr addrspace(1) %arg) #0 {31; GCN-LABEL: load_v3i32_align16:32; GCN: ; %bb.0:33; GCN: s_waitcnt lgkmcnt(0)34; GCN-NEXT: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x035 %vec = load <3 x i32>, ptr addrspace(1) %arg, align 1636 store <3 x i32> %vec, ptr addrspace(1) poison, align 1637 ret void38}39 40define protected amdgpu_kernel void @load_v3f32_align4(ptr addrspace(1) %arg) #0 {41; GCN-LABEL: load_v3f32_align4:42; GCN: ; %bb.0:43; GCN: s_waitcnt lgkmcnt(0)44; GCN-NEXT: s_load_dwordx2 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x045; GCN-NEXT: s_load_dword s{{[0-9]+}}, s[0:1], 0x846 %vec = load <3 x float>, ptr addrspace(1) %arg, align 447 store <3 x float> %vec, ptr addrspace(1) poison, align 448 ret void49}50 51define protected amdgpu_kernel void @load_v3f32_align8(ptr addrspace(1) %arg) #0 {52; GCN-LABEL: load_v3f32_align8:53; GCN: ; %bb.0:54; GCN: s_waitcnt lgkmcnt(0)55; GCN-NEXT: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[4:5], 0x056 %vec = load <3 x float>, ptr addrspace(1) %arg, align 857 store <3 x float> %vec, ptr addrspace(1) poison, align 858 ret void59}60 61define protected amdgpu_kernel void @load_v3f32_align16(ptr addrspace(1) %arg) #0 {62; GCN-LABEL: load_v3f32_align16:63; GCN: ; %bb.0:64; GCN: s_waitcnt lgkmcnt(0)65; GCN-NEXT: s_load_dwordx4 s{{\[[0-9]:[0-9]+\]}}, s[0:1], 0x066 %vec = load <3 x float>, ptr addrspace(1) %arg, align 1667 store <3 x float> %vec, ptr addrspace(1) poison, align 1668 ret void69}70 71attributes #0 = { nounwind noinline }72