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1# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 52# RUN: llc -mtriple=amdgcn-amd-amdpal -mcpu=gfx1200 -run-pass=si-fold-operands -verify-machineinstrs -o - %s | FileCheck --check-prefix=GCN %s3 4# Do not use inline constants for f16 pseudo scalar transcendentals.5# But allow literal constants.6 7---8name: exp_f16_imm9tracksRegLiveness: true10body: |11  bb.0:12    ; GCN-LABEL: name: exp_f16_imm13    ; GCN: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 1536014    ; GCN-NEXT: [[V_S_EXP_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_EXP_F16_e64 1, [[S_MOV_B32_]], 0, 0, implicit $mode, implicit $exec15    %0:sgpr_32 = S_MOV_B32 1536016    %1:sgpr_32 = V_S_EXP_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec17...18 19---20name: exp_f16_literal21tracksRegLiveness: true22body: |23  bb.0:24    ; GCN-LABEL: name: exp_f16_literal25    ; GCN: [[V_S_EXP_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_EXP_F16_e64 1, 16960, 0, 0, implicit $mode, implicit $exec26    %0:sgpr_32 = S_MOV_B32 1696027    %1:sgpr_32 = V_S_EXP_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec28...29 30---31name: log_f16_imm32tracksRegLiveness: true33body: |34  bb.0:35    ; GCN-LABEL: name: log_f16_imm36    ; GCN: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 1536037    ; GCN-NEXT: [[V_S_LOG_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_LOG_F16_e64 1, [[S_MOV_B32_]], 0, 0, implicit $mode, implicit $exec38    %0:sgpr_32 = S_MOV_B32 1536039    %1:sgpr_32 = V_S_LOG_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec40...41 42---43name: log_f16_literal44tracksRegLiveness: true45body: |46  bb.0:47    ; GCN-LABEL: name: log_f16_literal48    ; GCN: [[V_S_LOG_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_LOG_F16_e64 1, 16960, 0, 0, implicit $mode, implicit $exec49    %0:sgpr_32 = S_MOV_B32 1696050    %1:sgpr_32 = V_S_LOG_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec51...52 53---54name: rcp_f16_imm55tracksRegLiveness: true56body: |57  bb.0:58    ; GCN-LABEL: name: rcp_f16_imm59    ; GCN: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 1536060    ; GCN-NEXT: [[V_S_RCP_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_RCP_F16_e64 1, [[S_MOV_B32_]], 0, 0, implicit $mode, implicit $exec61    %0:sgpr_32 = S_MOV_B32 1536062    %1:sgpr_32 = V_S_RCP_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec63...64 65---66name: rcp_f16_literal67tracksRegLiveness: true68body: |69  bb.0:70    ; GCN-LABEL: name: rcp_f16_literal71    ; GCN: [[V_S_RCP_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_RCP_F16_e64 1, 16960, 0, 0, implicit $mode, implicit $exec72    %0:sgpr_32 = S_MOV_B32 1696073    %1:sgpr_32 = V_S_RCP_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec74...75 76---77name: rsq_f16_imm78tracksRegLiveness: true79body: |80  bb.0:81    ; GCN-LABEL: name: rsq_f16_imm82    ; GCN: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 1536083    ; GCN-NEXT: [[V_S_RSQ_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_RSQ_F16_e64 1, [[S_MOV_B32_]], 0, 0, implicit $mode, implicit $exec84    %0:sgpr_32 = S_MOV_B32 1536085    %1:sgpr_32 = V_S_RSQ_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec86...87 88---89name: rsq_f16_literal90tracksRegLiveness: true91body: |92  bb.0:93    ; GCN-LABEL: name: rsq_f16_literal94    ; GCN: [[V_S_RSQ_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_RSQ_F16_e64 1, 16960, 0, 0, implicit $mode, implicit $exec95    %0:sgpr_32 = S_MOV_B32 1696096    %1:sgpr_32 = V_S_RSQ_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec97...98 99---100name: sqrt_f16_imm101tracksRegLiveness: true102body: |103  bb.0:104    ; GCN-LABEL: name: sqrt_f16_imm105    ; GCN: [[S_MOV_B32_:%[0-9]+]]:sgpr_32 = S_MOV_B32 15360106    ; GCN-NEXT: [[V_S_SQRT_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_SQRT_F16_e64 1, [[S_MOV_B32_]], 0, 0, implicit $mode, implicit $exec107    %0:sgpr_32 = S_MOV_B32 15360108    %1:sgpr_32 = V_S_SQRT_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec109...110 111---112name: sqrt_f16_literal113tracksRegLiveness: true114body: |115  bb.0:116    ; GCN-LABEL: name: sqrt_f16_literal117    ; GCN: [[V_S_SQRT_F16_e64_:%[0-9]+]]:sgpr_32 = V_S_SQRT_F16_e64 1, 16960, 0, 0, implicit $mode, implicit $exec118    %0:sgpr_32 = S_MOV_B32 16960119    %1:sgpr_32 = V_S_SQRT_F16_e64 1, %0:sgpr_32, 0, 0, implicit $mode, implicit $exec120...121