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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx942 -disable-separate-const-offset-from-gep=1 < %s | FileCheck --check-prefixes=GFX942 %s3 4; Tests for DAG combines and folds related to the ISD::PTRADD SelectionDAG5; opcode. The RUN lines uses -disable-separate-const-offset-from-gep to disable6; similar transformations in that pass.7 8; Tests reassociation (ptradd N0:(ptradd p, c1), z) where N0 has only one use.9define i64 @global_load_ZTwoUses(ptr addrspace(1) %base, i64 %voffset) {10; GFX942-LABEL: global_load_ZTwoUses:11; GFX942: ; %bb.0:12; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)13; GFX942-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, v[2:3]14; GFX942-NEXT: global_load_dwordx2 v[0:1], v[0:1], off offset:2415; GFX942-NEXT: s_waitcnt vmcnt(0)16; GFX942-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, v[2:3]17; GFX942-NEXT: s_setpc_b64 s[30:31]18 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %base, i64 2419 %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 %voffset20 %l = load i64, ptr addrspace(1) %gep1, align 821 %r = add i64 %l, %voffset22 ret i64 %r23}24 25define i64 @global_load_gep_add_reassoc(ptr addrspace(1) %base, i64 %voffset) {26; GFX942-LABEL: global_load_gep_add_reassoc:27; GFX942: ; %bb.0:28; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)29; GFX942-NEXT: v_lshl_add_u64 v[0:1], v[0:1], 0, v[2:3]30; GFX942-NEXT: global_load_dwordx2 v[0:1], v[0:1], off offset:2431; GFX942-NEXT: s_waitcnt vmcnt(0)32; GFX942-NEXT: s_setpc_b64 s[30:31]33 %add0 = add nuw nsw i64 %voffset, 2434 %gep0 = getelementptr nuw inbounds i8, ptr addrspace(1) %base, i64 %add035 %l = load i64, ptr addrspace(1) %gep0, align 836 ret i64 %l37}38 39; Tests reassociation (ptradd (ptradd p, c1), c2) with two constants. These40; would be folded away in most cases, but the index computation introduced by41; the legalization of wide vector stores can for example introduce them.42define amdgpu_kernel void @store_v16i32(ptr addrspace(1) %out, <16 x i32> %a) {43; GFX942-LABEL: store_v16i32:44; GFX942: ; %bb.0: ; %entry45; GFX942-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x4046; GFX942-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x047; GFX942-NEXT: v_mov_b32_e32 v0, 048; GFX942-NEXT: s_waitcnt lgkmcnt(0)49; GFX942-NEXT: v_mov_b32_e32 v2, s2050; GFX942-NEXT: v_mov_b32_e32 v3, s2151; GFX942-NEXT: v_mov_b32_e32 v4, s2252; GFX942-NEXT: v_mov_b32_e32 v5, s2353; GFX942-NEXT: global_store_dwordx4 v0, v[2:5], s[0:1] offset:4854; GFX942-NEXT: s_nop 155; GFX942-NEXT: v_mov_b32_e32 v2, s1656; GFX942-NEXT: v_mov_b32_e32 v3, s1757; GFX942-NEXT: v_mov_b32_e32 v4, s1858; GFX942-NEXT: v_mov_b32_e32 v5, s1959; GFX942-NEXT: global_store_dwordx4 v0, v[2:5], s[0:1] offset:3260; GFX942-NEXT: s_nop 161; GFX942-NEXT: v_mov_b32_e32 v2, s1262; GFX942-NEXT: v_mov_b32_e32 v3, s1363; GFX942-NEXT: v_mov_b32_e32 v4, s1464; GFX942-NEXT: v_mov_b32_e32 v5, s1565; GFX942-NEXT: global_store_dwordx4 v0, v[2:5], s[0:1] offset:1666; GFX942-NEXT: s_nop 167; GFX942-NEXT: v_mov_b32_e32 v2, s868; GFX942-NEXT: v_mov_b32_e32 v3, s969; GFX942-NEXT: v_mov_b32_e32 v4, s1070; GFX942-NEXT: v_mov_b32_e32 v5, s1171; GFX942-NEXT: global_store_dwordx4 v0, v[2:5], s[0:1]72; GFX942-NEXT: s_endpgm73entry:74 store <16 x i32> %a, ptr addrspace(1) %out75 ret void76}77 78 79; Tests the (ptradd 0, x) -> x DAG combine.80define void @baseptr_null(i64 %offset, i8 %v) {81; GFX942-LABEL: baseptr_null:82; GFX942: ; %bb.0:83; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)84; GFX942-NEXT: flat_store_byte v[0:1], v285; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)86; GFX942-NEXT: s_setpc_b64 s[30:31]87 %gep = getelementptr i8, ptr null, i64 %offset88 store i8 %v, ptr %gep, align 189 ret void90}91 92; Taken from implicit-kernarg-backend-usage.ll, tests the PTRADD handling in the93; assertalign DAG combine.94define amdgpu_kernel void @llvm_amdgcn_queue_ptr(ptr addrspace(1) %ptr) {95; GFX942-LABEL: llvm_amdgcn_queue_ptr:96; GFX942: ; %bb.0:97; GFX942-NEXT: v_mov_b32_e32 v0, 098; GFX942-NEXT: global_load_ubyte v1, v0, s[2:3] sc0 sc199; GFX942-NEXT: global_load_ubyte v1, v0, s[4:5] offset:8 sc0 sc1100; GFX942-NEXT: global_load_ubyte v1, v0, s[0:1] sc0 sc1101; GFX942-NEXT: ; kill: killed $sgpr0_sgpr1102; GFX942-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0103; GFX942-NEXT: v_mov_b64_e32 v[2:3], s[6:7]104; GFX942-NEXT: ; kill: killed $sgpr2_sgpr3105; GFX942-NEXT: s_waitcnt lgkmcnt(0)106; GFX942-NEXT: global_store_dwordx2 v0, v[2:3], s[0:1] sc0 sc1107; GFX942-NEXT: s_waitcnt vmcnt(0)108; GFX942-NEXT: s_endpgm109 %queue.ptr = call ptr addrspace(4) @llvm.amdgcn.queue.ptr()110 %implicitarg.ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()111 %dispatch.ptr = call ptr addrspace(4) @llvm.amdgcn.dispatch.ptr()112 %dispatch.id = call i64 @llvm.amdgcn.dispatch.id()113 %queue.load = load volatile i8, ptr addrspace(4) %queue.ptr114 %implicitarg.load = load volatile i8, ptr addrspace(4) %implicitarg.ptr115 %dispatch.load = load volatile i8, ptr addrspace(4) %dispatch.ptr116 store volatile i64 %dispatch.id, ptr addrspace(1) %ptr117 ret void118}119 120; Taken from memcpy-param-combinations.ll, tests PTRADD handling in121; SelectionDAGAddressAnalysis.122define void @memcpy_p1_p4_sz16_align_1_1(ptr addrspace(1) align 1 %dst, ptr addrspace(4) align 1 readonly %src) {123; GFX942-LABEL: memcpy_p1_p4_sz16_align_1_1:124; GFX942: ; %bb.0: ; %entry125; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)126; GFX942-NEXT: global_load_dwordx4 v[2:5], v[2:3], off127; GFX942-NEXT: s_waitcnt vmcnt(0)128; GFX942-NEXT: global_store_dwordx4 v[0:1], v[2:5], off129; GFX942-NEXT: s_waitcnt vmcnt(0)130; GFX942-NEXT: s_setpc_b64 s[30:31]131entry:132 tail call void @llvm.memcpy.p1.p4.i64(ptr addrspace(1) noundef nonnull align 1 %dst, ptr addrspace(4) noundef nonnull align 1 %src, i64 16, i1 false)133 ret void134}135 136; Test skipping the lower-32-bit addition if it is unnecessary.137define ptr @huge_offset_low_32_unused(ptr %p) {138; GFX942-LABEL: huge_offset_low_32_unused:139; GFX942: ; %bb.0:140; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)141; GFX942-NEXT: v_add_u32_e32 v1, 1, v1142; GFX942-NEXT: s_setpc_b64 s[30:31]143 %gep = getelementptr inbounds i8, ptr %p, i64 u0x100000000144 ret ptr %gep145}146 147; Reassociate address computation if it leads to more scalar operations.148define amdgpu_kernel void @reassoc_scalar_r(ptr addrspace(1) %out, ptr addrspace(1) %p, i64 %soffset) {149; GFX942-LABEL: reassoc_scalar_r:150; GFX942: ; %bb.0: ; %entry151; GFX942-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0152; GFX942-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x10153; GFX942-NEXT: v_mov_b32_e32 v1, 0154; GFX942-NEXT: v_and_b32_e32 v0, 0x3ff, v0155; GFX942-NEXT: s_waitcnt lgkmcnt(0)156; GFX942-NEXT: s_add_u32 s2, s2, s6157; GFX942-NEXT: s_addc_u32 s3, s3, s7158; GFX942-NEXT: v_lshl_add_u64 v[2:3], s[2:3], 0, v[0:1]159; GFX942-NEXT: global_store_dwordx2 v1, v[2:3], s[0:1]160; GFX942-NEXT: s_endpgm161entry:162 %voffset32 = call i32 @llvm.amdgcn.workitem.id.x()163 %voffset = zext i32 %voffset32 to i64164 %offset = add nuw nsw i64 %voffset, %soffset165 %gep = getelementptr i8, ptr addrspace(1) %p, i64 %offset166 store ptr addrspace(1) %gep, ptr addrspace(1) %out167 ret void168}169 170define amdgpu_kernel void @reassoc_scalar_l(ptr addrspace(1) %out, ptr addrspace(1) %p, i64 %soffset) {171; GFX942-LABEL: reassoc_scalar_l:172; GFX942: ; %bb.0: ; %entry173; GFX942-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x0174; GFX942-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x10175; GFX942-NEXT: v_mov_b32_e32 v1, 0176; GFX942-NEXT: v_and_b32_e32 v0, 0x3ff, v0177; GFX942-NEXT: s_waitcnt lgkmcnt(0)178; GFX942-NEXT: s_add_u32 s2, s2, s6179; GFX942-NEXT: s_addc_u32 s3, s3, s7180; GFX942-NEXT: v_lshl_add_u64 v[2:3], s[2:3], 0, v[0:1]181; GFX942-NEXT: global_store_dwordx2 v1, v[2:3], s[0:1]182; GFX942-NEXT: s_endpgm183entry:184 %voffset32 = call i32 @llvm.amdgcn.workitem.id.x()185 %voffset = zext i32 %voffset32 to i64186 %offset = add nuw nsw i64 %soffset, %voffset187 %gep = getelementptr i8, ptr addrspace(1) %p, i64 %offset188 store ptr addrspace(1) %gep, ptr addrspace(1) %out189 ret void190}191 192; Tests the target-specific (ptradd x, shl(0 - y, k)) -> sub(x, shl(y, k)) fold193define ptr addrspace(1) @shl_neg_offset(ptr addrspace(1) %p, i64 %noffset, i64 %shift) {194; GFX942-LABEL: shl_neg_offset:195; GFX942: ; %bb.0:196; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)197; GFX942-NEXT: v_lshlrev_b64 v[2:3], v4, v[2:3]198; GFX942-NEXT: v_sub_co_u32_e32 v0, vcc, v0, v2199; GFX942-NEXT: s_nop 1200; GFX942-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v3, vcc201; GFX942-NEXT: s_setpc_b64 s[30:31]202 %offset = sub i64 0, %noffset203 %x = shl i64 %offset, %shift204 %gep = getelementptr inbounds i8, ptr addrspace(1) %p, i64 %x205 ret ptr addrspace(1) %gep206}207 208%complextype = type { i64, [10 x i8], float }209 210@v0 = dso_local addrspace(1) global %complextype zeroinitializer211 212; Check that offsets are folded into global addresses if possible. For example,213; this is relevant when using --amdgpu-lower-module-lds-strategy=table.214define ptr addrspace(1) @complextype_global_gep(i64 %offset) {215; GFX942-LABEL: complextype_global_gep:216; GFX942: ; %bb.0:217; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)218; GFX942-NEXT: s_getpc_b64 s[0:1]219; GFX942-NEXT: s_add_u32 s0, s0, v0@rel32@lo+14220; GFX942-NEXT: s_addc_u32 s1, s1, v0@rel32@hi+22221; GFX942-NEXT: v_lshl_add_u64 v[0:1], s[0:1], 0, v[0:1]222; GFX942-NEXT: s_setpc_b64 s[30:31]223 %gep0 = getelementptr inbounds %complextype, ptr addrspace(1) @v0, i64 0, i32 1, i64 %offset224 %gep1 = getelementptr inbounds i8, ptr addrspace(1) %gep0, i64 2225 ret ptr addrspace(1) %gep1226}227 228%S = type <{ float, double }>229 230; Tests the tryFoldToMad64_32 PTRADD combine.231define amdgpu_kernel void @fold_mad64(ptr addrspace(1) %p) {232; GFX942-LABEL: fold_mad64:233; GFX942: ; %bb.0:234; GFX942-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0235; GFX942-NEXT: v_and_b32_e32 v0, 0x3ff, v0236; GFX942-NEXT: v_mov_b32_e32 v2, 1.0237; GFX942-NEXT: s_waitcnt lgkmcnt(0)238; GFX942-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v0, 12, s[0:1]239; GFX942-NEXT: global_store_dword v[0:1], v2, off240; GFX942-NEXT: s_endpgm241 %voffset32 = call i32 @llvm.amdgcn.workitem.id.x()242 %voffset = zext i32 %voffset32 to i64243 %p1 = getelementptr inbounds %S, ptr addrspace(1) %p, i64 %voffset, i32 0244 store float 1.0, ptr addrspace(1) %p1245 ret void246}247 248; Use non-zero shift amounts in v_lshl_add_u64.249define ptr @select_v_lshl_add_u64(ptr %base, i64 %voffset) {250; GFX942-LABEL: select_v_lshl_add_u64:251; GFX942: ; %bb.0:252; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)253; GFX942-NEXT: v_lshl_add_u64 v[0:1], v[2:3], 3, v[0:1]254; GFX942-NEXT: s_setpc_b64 s[30:31]255 %gep = getelementptr inbounds i64, ptr %base, i64 %voffset256 ret ptr %gep257}258 259; Fold mul and add into v_mad, even if amdgpu-codegenprepare-mul24 turned the260; mul into a mul24.261define ptr @fold_mul24_into_mad(ptr %base, i64 %a, i64 %b) {262; GFX942-LABEL: fold_mul24_into_mad:263; GFX942: ; %bb.0:264; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)265; GFX942-NEXT: v_and_b32_e32 v2, 0xfffff, v2266; GFX942-NEXT: v_and_b32_e32 v3, 0xfffff, v4267; GFX942-NEXT: v_mad_u64_u32 v[0:1], s[0:1], v2, v3, v[0:1]268; GFX942-NEXT: s_setpc_b64 s[30:31]269 %a_masked = and i64 %a, u0xfffff270 %b_masked = and i64 %b, u0xfffff271 %mul = mul i64 %a_masked, %b_masked272 %gep = getelementptr inbounds i8, ptr %base, i64 %mul273 ret ptr %gep274}275 276; Test PTRADD handling in AMDGPUDAGToDAGISel::SelectGlobalSAddr.277define amdgpu_kernel void @uniform_base_varying_offset_imm(ptr addrspace(1) %p) {278; GFX942-LABEL: uniform_base_varying_offset_imm:279; GFX942: ; %bb.0: ; %entry280; GFX942-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0281; GFX942-NEXT: v_and_b32_e32 v0, 0x3ff, v0282; GFX942-NEXT: v_lshlrev_b32_e32 v0, 2, v0283; GFX942-NEXT: v_mov_b32_e32 v1, 1284; GFX942-NEXT: s_waitcnt lgkmcnt(0)285; GFX942-NEXT: global_store_dword v0, v1, s[0:1] offset:16286; GFX942-NEXT: s_endpgm287entry:288 %tid = call i32 @llvm.amdgcn.workitem.id.x()289 %shift = shl i32 %tid, 2290 %voffset = zext i32 %shift to i64291 %gep1 = getelementptr inbounds i8, ptr addrspace(1) %p, i64 %voffset292 %gep2 = getelementptr inbounds i8, ptr addrspace(1) %gep1, i64 16293 store i32 1, ptr addrspace(1) %gep2294 ret void295}296 297; Adjusted from global-saddr-load.ll. Tests PTRADD handling in298; AMDGPUDAGToDAGISel::SelectSMRDBaseOffset.299define amdgpu_kernel void @global_load_saddr_i32_uniform_offset(ptr addrspace(1) %sbase, i32 %soffset, ptr addrspace(1) %r) {300; GFX942-LABEL: global_load_saddr_i32_uniform_offset:301; GFX942: ; %bb.0:302; GFX942-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x0303; GFX942-NEXT: s_load_dword s6, s[4:5], 0x8304; GFX942-NEXT: s_load_dwordx2 s[2:3], s[4:5], 0x10305; GFX942-NEXT: v_mov_b32_e32 v0, 0306; GFX942-NEXT: s_waitcnt lgkmcnt(0)307; GFX942-NEXT: s_load_dword s0, s[0:1], s6 offset:0x0308; GFX942-NEXT: s_waitcnt lgkmcnt(0)309; GFX942-NEXT: v_mov_b32_e32 v1, s0310; GFX942-NEXT: global_store_dword v0, v1, s[2:3]311; GFX942-NEXT: s_endpgm312 %zext.offset = zext i32 %soffset to i64313 %gep0 = getelementptr inbounds i8, ptr addrspace(1) %sbase, i64 %zext.offset314 %load = load i32, ptr addrspace(1) %gep0315 %to.vgpr = bitcast i32 %load to float316 store float %to.vgpr, ptr addrspace(1) %r317 ret void318}319 320; Adjusted from llvm.amdgcn.global.load.lds.ll, tests the offset lowering for321; Intrinsic::amdgcn_global_load_lds.322define void @global_load_lds_dword_saddr_and_vaddr(ptr addrspace(1) nocapture inreg %gptr, ptr addrspace(3) nocapture %lptr, i32 %voffset) {323; GFX942-LABEL: global_load_lds_dword_saddr_and_vaddr:324; GFX942: ; %bb.0: ; %main_body325; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)326; GFX942-NEXT: v_readfirstlane_b32 s2, v0327; GFX942-NEXT: s_mov_b32 m0, s2328; GFX942-NEXT: s_nop 0329; GFX942-NEXT: global_load_lds_dword v1, s[0:1] offset:48 sc1330; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)331; GFX942-NEXT: s_setpc_b64 s[30:31]332main_body:333 %voffset.64 = zext i32 %voffset to i64334 %gep = getelementptr i8, ptr addrspace(1) %gptr, i64 %voffset.64335 call void @llvm.amdgcn.global.load.lds(ptr addrspace(1) %gep, ptr addrspace(3) %lptr, i32 4, i32 48, i32 16)336 ret void337}338 339; Taken from shl_add_ptr_global.ll, tests PTRADD handling in340; SITargetLowering::performSHLPtrCombine.341define void @shl_base_global_ptr_global_atomic_fadd(ptr addrspace(1) %out, ptr addrspace(1) %extra.use, ptr addrspace(1) %ptr) {342; GFX942-LABEL: shl_base_global_ptr_global_atomic_fadd:343; GFX942: ; %bb.0:344; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)345; GFX942-NEXT: v_lshlrev_b64 v[0:1], 2, v[4:5]346; GFX942-NEXT: v_mov_b32_e32 v6, 0x42c80000347; GFX942-NEXT: global_atomic_add_f32 v[0:1], v6, off offset:512348; GFX942-NEXT: s_mov_b64 s[0:1], 0x80349; GFX942-NEXT: v_lshl_add_u64 v[0:1], v[4:5], 0, s[0:1]350; GFX942-NEXT: global_store_dwordx2 v[2:3], v[0:1], off sc0 sc1351; GFX942-NEXT: s_waitcnt vmcnt(0)352; GFX942-NEXT: s_setpc_b64 s[30:31]353 %arrayidx0 = getelementptr inbounds [512 x i32], ptr addrspace(1) %ptr, i64 0, i64 32354 %cast = ptrtoint ptr addrspace(1) %arrayidx0 to i64355 %shl = shl i64 %cast, 2356 %castback = inttoptr i64 %shl to ptr addrspace(1)357 %unused = atomicrmw fadd ptr addrspace(1) %castback, float 100.0 syncscope("agent") monotonic, align 4, !amdgpu.no.fine.grained.memory !0, !amdgpu.ignore.denormal.mode !0358 store volatile i64 %cast, ptr addrspace(1) %extra.use, align 4359 ret void360}361 362; Test PTRADD handling in TargetLowering::SimplifyDemandedBits and363; TargetLowering::ShrinkDemandedOp.364define i32 @gep_in_const_as_cast_to_const32_as(ptr addrspace(4) %src, i64 %offset) {365; GFX942-LABEL: gep_in_const_as_cast_to_const32_as:366; GFX942: ; %bb.0: ; %entry367; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)368; GFX942-NEXT: v_add_u32_e32 v0, v0, v2369; GFX942-NEXT: s_mov_b32 s1, 0370; GFX942-NEXT: v_readfirstlane_b32 s0, v0371; GFX942-NEXT: s_load_dword s0, s[0:1], 0x0372; GFX942-NEXT: s_waitcnt lgkmcnt(0)373; GFX942-NEXT: v_mov_b32_e32 v0, s0374; GFX942-NEXT: s_setpc_b64 s[30:31]375entry:376 %gep = getelementptr i8, ptr addrspace(4) %src, i64 %offset377 %gep.cast = addrspacecast ptr addrspace(4) %gep to ptr addrspace(6)378 %l = load i32, ptr addrspace(6) %gep.cast379 ret i32 %l380}381 382@CG = addrspace(4) constant [16 x i32] zeroinitializer, align 4383 384; Test PTRADD handling in isMemSrcFromConstant.385define void @replace_const0_memcpy_by_memset(ptr align 4 %dst) {386; GFX942-LABEL: replace_const0_memcpy_by_memset:387; GFX942: ; %bb.0: ; %entry388; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)389; GFX942-NEXT: v_mov_b32_e32 v2, 0390; GFX942-NEXT: v_mov_b32_e32 v3, v2391; GFX942-NEXT: flat_store_dwordx2 v[0:1], v[2:3]392; GFX942-NEXT: s_waitcnt vmcnt(0) lgkmcnt(0)393; GFX942-NEXT: s_setpc_b64 s[30:31]394entry:395 %gep = getelementptr i8, ptr addrspace(4) @CG, i64 4396 tail call void @llvm.memcpy.p0.p4.i64(ptr noundef nonnull align 4 %dst, ptr addrspace(4) noundef nonnull align 4 %gep, i64 8, i1 false)397 ret void398}399 400; Check that ptradds can be lowered to disjoint ORs.401define ptr @gep_disjoint_or(ptr %base) {402; GFX942-LABEL: gep_disjoint_or:403; GFX942: ; %bb.0:404; GFX942-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)405; GFX942-NEXT: v_and_or_b32 v0, v0, -16, 4406; GFX942-NEXT: s_setpc_b64 s[30:31]407 %p = call ptr @llvm.ptrmask(ptr %base, i64 s0xf0)408 %gep = getelementptr nuw inbounds i8, ptr %p, i64 4409 ret ptr %gep410}411 412; Check that AssertAlign nodes between ptradd nodes don't block offset folding,413; taken from preload-implicit-kernargs.ll414define amdgpu_kernel void @random_incorrect_offset(ptr addrspace(1) inreg %out) {415; GFX942-LABEL: random_incorrect_offset:416; GFX942: ; %bb.1:417; GFX942-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0x0418; GFX942-NEXT: s_waitcnt lgkmcnt(0)419; GFX942-NEXT: s_branch .LBB21_0420; GFX942-NEXT: .p2align 8421; GFX942-NEXT: ; %bb.2:422; GFX942-NEXT: .LBB21_0:423; GFX942-NEXT: s_load_dword s0, s[4:5], 0xa424; GFX942-NEXT: v_mov_b32_e32 v0, 0425; GFX942-NEXT: s_waitcnt lgkmcnt(0)426; GFX942-NEXT: v_mov_b32_e32 v1, s0427; GFX942-NEXT: global_store_dword v0, v1, s[8:9]428; GFX942-NEXT: s_endpgm429 %imp_arg_ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()430 %gep = getelementptr i8, ptr addrspace(4) %imp_arg_ptr, i32 2431 %load = load i32, ptr addrspace(4) %gep432 store i32 %load, ptr addrspace(1) %out433 ret void434}435 436declare void @llvm.memcpy.p0.p4.i64(ptr noalias nocapture writeonly, ptr addrspace(4) noalias nocapture readonly, i64, i1 immarg)437 438!0 = !{}439