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1; RUN: llc < %s -mtriple=r600 -show-mc-encoding -mcpu=redwood | FileCheck --check-prefix=EG %s2; RUN: llc < %s -mtriple=r600 -show-mc-encoding -mcpu=rs880 | FileCheck --check-prefix=R600 %s3 4; The earliest R600 GPUs have a slightly different encoding than the rest of5; the VLIW4/5 GPUs.6 7; EG: {{^}}test:8; EG: MUL_IEEE {{[ *TXYZWPVxyzw.,0-9]+}} ; encoding: [{{0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x10,0x01,0x[0-9a-f]+,0x[0-9a-f]+}}]9 10; R600: {{^}}test:11; R600: MUL_IEEE {{[ *TXYZWPVxyzw.,0-9]+}} ; encoding: [{{0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x[0-9a-f]+,0x10,0x02,0x[0-9a-f]+,0x[0-9a-f]+}}]12 13define amdgpu_ps void @test(<4 x float> inreg %reg0) {14entry:15 %r0 = extractelement <4 x float> %reg0, i32 016 %r1 = extractelement <4 x float> %reg0, i32 117 %r2 = fmul float %r0, %r118 %vec = insertelement <4 x float> poison, float %r2, i32 019 call void @llvm.r600.store.swizzle(<4 x float> %vec, i32 0, i32 0)20 ret void21}22 23declare void @llvm.r600.store.swizzle(<4 x float>, i32, i32)24