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1; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck -enable-var-scope -check-prefix=EG -check-prefix=FUNC %s2 3; FUNC-LABEL: {{^}}s_add_i32:4; EG: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}5define amdgpu_kernel void @s_add_i32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {6 %b_ptr = getelementptr i32, ptr addrspace(1) %in, i32 17 %a = load i32, ptr addrspace(1) %in8 %b = load i32, ptr addrspace(1) %b_ptr9 %result = add i32 %a, %b10 store i32 %result, ptr addrspace(1) %out11 ret void12}13 14; FUNC-LABEL: {{^}}s_add_v2i32:15; EG: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}16; EG: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}17define amdgpu_kernel void @s_add_v2i32(ptr addrspace(1) %out, ptr addrspace(1) %in) {18 %b_ptr = getelementptr <2 x i32>, ptr addrspace(1) %in, i32 119 %a = load <2 x i32>, ptr addrspace(1) %in20 %b = load <2 x i32>, ptr addrspace(1) %b_ptr21 %result = add <2 x i32> %a, %b22 store <2 x i32> %result, ptr addrspace(1) %out23 ret void24}25 26; FUNC-LABEL: {{^}}s_add_v4i32:27; EG: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}28; EG: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}29; EG: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}30; EG: ADD_INT {{[* ]*}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}31define amdgpu_kernel void @s_add_v4i32(ptr addrspace(1) %out, ptr addrspace(1) %in) {32 %b_ptr = getelementptr <4 x i32>, ptr addrspace(1) %in, i32 133 %a = load <4 x i32>, ptr addrspace(1) %in34 %b = load <4 x i32>, ptr addrspace(1) %b_ptr35 %result = add <4 x i32> %a, %b36 store <4 x i32> %result, ptr addrspace(1) %out37 ret void38}39 40; FUNC-LABEL: {{^}}s_add_v8i32:41; EG: ADD_INT42; EG: ADD_INT43; EG: ADD_INT44; EG: ADD_INT45; EG: ADD_INT46; EG: ADD_INT47; EG: ADD_INT48; EG: ADD_INT49define amdgpu_kernel void @s_add_v8i32(ptr addrspace(1) %out, <8 x i32> %a, <8 x i32> %b) {50entry:51 %0 = add <8 x i32> %a, %b52 store <8 x i32> %0, ptr addrspace(1) %out53 ret void54}55 56; FUNC-LABEL: {{^}}s_add_v16i32:57; EG: ADD_INT58; EG: ADD_INT59; EG: ADD_INT60; EG: ADD_INT61; EG: ADD_INT62; EG: ADD_INT63; EG: ADD_INT64; EG: ADD_INT65; EG: ADD_INT66; EG: ADD_INT67; EG: ADD_INT68; EG: ADD_INT69; EG: ADD_INT70; EG: ADD_INT71; EG: ADD_INT72; EG: ADD_INT73define amdgpu_kernel void @s_add_v16i32(ptr addrspace(1) %out, <16 x i32> %a, <16 x i32> %b) {74entry:75 %0 = add <16 x i32> %a, %b76 store <16 x i32> %0, ptr addrspace(1) %out77 ret void78}79 80; FUNC-LABEL: {{^}}v_add_i32:81define amdgpu_kernel void @v_add_i32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {82 %tid = call i32 @llvm.r600.read.tidig.x()83 %gep = getelementptr inbounds i32, ptr addrspace(1) %in, i32 %tid84 %b_ptr = getelementptr i32, ptr addrspace(1) %gep, i32 185 %a = load volatile i32, ptr addrspace(1) %gep86 %b = load volatile i32, ptr addrspace(1) %b_ptr87 %result = add i32 %a, %b88 store i32 %result, ptr addrspace(1) %out89 ret void90}91 92; FUNC-LABEL: {{^}}v_add_imm_i32:93define amdgpu_kernel void @v_add_imm_i32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {94 %tid = call i32 @llvm.r600.read.tidig.x()95 %gep = getelementptr inbounds i32, ptr addrspace(1) %in, i32 %tid96 %b_ptr = getelementptr i32, ptr addrspace(1) %gep, i32 197 %a = load volatile i32, ptr addrspace(1) %gep98 %result = add i32 %a, 12399 store i32 %result, ptr addrspace(1) %out100 ret void101}102 103; FUNC-LABEL: {{^}}add64:104; EG: MEM_RAT_CACHELESS STORE_RAW [[LO:T[0-9]+\.XY]]105; EG-DAG: ADD_INT {{[* ]*}}106; EG-DAG: ADDC_UINT107; EG-DAG: ADD_INT108; EG-DAG: ADD_INT {{[* ]*}}109; EG-NOT: SUB110define amdgpu_kernel void @add64(ptr addrspace(1) %out, i64 %a, i64 %b) {111entry:112 %add = add i64 %a, %b113 store i64 %add, ptr addrspace(1) %out114 ret void115}116 117; The v_addc_u32 and v_add_i32 instruction can't read SGPRs, because they118; use VCC. The test is designed so that %a will be stored in an SGPR and119; %0 will be stored in a VGPR, so the comiler will be forced to copy %a120; to a VGPR before doing the add.121 122; FUNC-LABEL: {{^}}add64_sgpr_vgpr:123; EG: MEM_RAT_CACHELESS STORE_RAW [[LO:T[0-9]+\.XY]]124; EG-DAG: ADD_INT {{[* ]*}}125; EG-DAG: ADDC_UINT126; EG-DAG: ADD_INT127; EG-DAG: ADD_INT {{[* ]*}}128; EG-NOT: SUB129define amdgpu_kernel void @add64_sgpr_vgpr(ptr addrspace(1) %out, i64 %a, ptr addrspace(1) %in) {130entry:131 %0 = load i64, ptr addrspace(1) %in132 %1 = add i64 %a, %0133 store i64 %1, ptr addrspace(1) %out134 ret void135}136 137; Test i64 add inside a branch.138; FUNC-LABEL: {{^}}add64_in_branch:139; EG: MEM_RAT_CACHELESS STORE_RAW [[LO:T[0-9]+\.XY]]140; EG-DAG: ADD_INT {{[* ]*}}141; EG-DAG: ADDC_UINT142; EG-DAG: ADD_INT143; EG-DAG: ADD_INT {{[* ]*}}144; EG-NOT: SUB145define amdgpu_kernel void @add64_in_branch(ptr addrspace(1) %out, ptr addrspace(1) %in, i64 %a, i64 %b, i64 %c) {146entry:147 %0 = icmp eq i64 %a, 0148 br i1 %0, label %if, label %else149 150if:151 %1 = load i64, ptr addrspace(1) %in152 br label %endif153 154else:155 %2 = add i64 %a, %b156 br label %endif157 158endif:159 %3 = phi i64 [%1, %if], [%2, %else]160 store i64 %3, ptr addrspace(1) %out161 ret void162}163 164declare i32 @llvm.r600.read.tidig.x() #1165 166attributes #0 = { nounwind }167attributes #1 = { nounwind readnone speculatable }168