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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py2; RUN: llc -mtriple=r600-- -mcpu=cypress < %s | FileCheck -check-prefix=EG %s3; RUN: llc -mtriple=r600-- -mcpu=cayman < %s | FileCheck -check-prefix=CM %s4 5; Loosely based on test/CodeGen/{X86,AArch64}/extract-lowbits.ll,6; but with all 64-bit tests, and tests with loads dropped.7 8; Patterns:9; a) x & (1 << nbits) - 110; b) x & ~(-1 << nbits)11; c) x & (-1 >> (32 - y))12; d) x << (32 - y) >> (32 - y)13; are equivalent.14 15; ---------------------------------------------------------------------------- ;16; Pattern a. 32-bit17; ---------------------------------------------------------------------------- ;18 19define amdgpu_kernel void @bzhi32_a0(i32 %val, i32 %numlowbits, ptr addrspace(1) %out) {20; EG-LABEL: bzhi32_a0:21; EG: ; %bb.0:22; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]23; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 124; EG-NEXT: CF_END25; EG-NEXT: PAD26; EG-NEXT: ALU clause starting at 4:27; EG-NEXT: LSHR * T0.X, KC0[2].W, literal.x,28; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)29; EG-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z,30;31; CM-LABEL: bzhi32_a0:32; CM: ; %bb.0:33; CM-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]34; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X35; CM-NEXT: CF_END36; CM-NEXT: PAD37; CM-NEXT: ALU clause starting at 4:38; CM-NEXT: LSHR * T0.X, KC0[2].W, literal.x,39; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)40; CM-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z,41 %onebit = shl i32 1, %numlowbits42 %mask = add nsw i32 %onebit, -143 %masked = and i32 %mask, %val44 store i32 %masked, ptr addrspace(1) %out45 ret void46}47 48define amdgpu_kernel void @bzhi32_a1_indexzext(i32 %val, i8 zeroext %numlowbits, ptr addrspace(1) %out) {49; EG-LABEL: bzhi32_a1_indexzext:50; EG: ; %bb.0:51; EG-NEXT: ALU 0, @8, KC0[], KC1[]52; EG-NEXT: TEX 0 @653; EG-NEXT: ALU 4, @9, KC0[CB0:0-32], KC1[]54; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 155; EG-NEXT: CF_END56; EG-NEXT: PAD57; EG-NEXT: Fetch clause starting at 6:58; EG-NEXT: VTX_READ_8 T0.X, T0.X, 40, #359; EG-NEXT: ALU clause starting at 8:60; EG-NEXT: MOV * T0.X, 0.0,61; EG-NEXT: ALU clause starting at 9:62; EG-NEXT: BFE_INT * T0.W, T0.X, 0.0, literal.x,63; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)64; EG-NEXT: BFE_UINT T0.X, KC0[2].Y, 0.0, PV.W,65; EG-NEXT: LSHR * T1.X, KC0[2].W, literal.x,66; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)67;68; CM-LABEL: bzhi32_a1_indexzext:69; CM: ; %bb.0:70; CM-NEXT: ALU 0, @8, KC0[], KC1[]71; CM-NEXT: TEX 0 @672; CM-NEXT: ALU 4, @9, KC0[CB0:0-32], KC1[]73; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X74; CM-NEXT: CF_END75; CM-NEXT: PAD76; CM-NEXT: Fetch clause starting at 6:77; CM-NEXT: VTX_READ_8 T0.X, T0.X, 40, #378; CM-NEXT: ALU clause starting at 8:79; CM-NEXT: MOV * T0.X, 0.0,80; CM-NEXT: ALU clause starting at 9:81; CM-NEXT: BFE_INT * T0.W, T0.X, 0.0, literal.x,82; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)83; CM-NEXT: BFE_UINT * T0.X, KC0[2].Y, 0.0, PV.W,84; CM-NEXT: LSHR * T1.X, KC0[2].W, literal.x,85; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)86 %conv = zext i8 %numlowbits to i3287 %onebit = shl i32 1, %conv88 %mask = add nsw i32 %onebit, -189 %masked = and i32 %mask, %val90 store i32 %masked, ptr addrspace(1) %out91 ret void92}93 94define amdgpu_kernel void @bzhi32_a4_commutative(i32 %val, i32 %numlowbits, ptr addrspace(1) %out) {95; EG-LABEL: bzhi32_a4_commutative:96; EG: ; %bb.0:97; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]98; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 199; EG-NEXT: CF_END100; EG-NEXT: PAD101; EG-NEXT: ALU clause starting at 4:102; EG-NEXT: LSHR * T0.X, KC0[2].W, literal.x,103; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)104; EG-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z,105;106; CM-LABEL: bzhi32_a4_commutative:107; CM: ; %bb.0:108; CM-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]109; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X110; CM-NEXT: CF_END111; CM-NEXT: PAD112; CM-NEXT: ALU clause starting at 4:113; CM-NEXT: LSHR * T0.X, KC0[2].W, literal.x,114; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)115; CM-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z,116 %onebit = shl i32 1, %numlowbits117 %mask = add nsw i32 %onebit, -1118 %masked = and i32 %val, %mask ; swapped order119 store i32 %masked, ptr addrspace(1) %out120 ret void121}122 123; ---------------------------------------------------------------------------- ;124; Pattern b. 32-bit125; ---------------------------------------------------------------------------- ;126 127define amdgpu_kernel void @bzhi32_b0(i32 %val, i32 %numlowbits, ptr addrspace(1) %out) {128; EG-LABEL: bzhi32_b0:129; EG: ; %bb.0:130; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]131; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1132; EG-NEXT: CF_END133; EG-NEXT: PAD134; EG-NEXT: ALU clause starting at 4:135; EG-NEXT: LSHR * T0.X, KC0[2].W, literal.x,136; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)137; EG-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z,138;139; CM-LABEL: bzhi32_b0:140; CM: ; %bb.0:141; CM-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]142; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X143; CM-NEXT: CF_END144; CM-NEXT: PAD145; CM-NEXT: ALU clause starting at 4:146; CM-NEXT: LSHR * T0.X, KC0[2].W, literal.x,147; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)148; CM-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z,149 %notmask = shl i32 -1, %numlowbits150 %mask = xor i32 %notmask, -1151 %masked = and i32 %mask, %val152 store i32 %masked, ptr addrspace(1) %out153 ret void154}155 156define amdgpu_kernel void @bzhi32_b1_indexzext(i32 %val, i8 zeroext %numlowbits, ptr addrspace(1) %out) {157; EG-LABEL: bzhi32_b1_indexzext:158; EG: ; %bb.0:159; EG-NEXT: ALU 0, @8, KC0[], KC1[]160; EG-NEXT: TEX 0 @6161; EG-NEXT: ALU 4, @9, KC0[CB0:0-32], KC1[]162; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1163; EG-NEXT: CF_END164; EG-NEXT: PAD165; EG-NEXT: Fetch clause starting at 6:166; EG-NEXT: VTX_READ_8 T0.X, T0.X, 40, #3167; EG-NEXT: ALU clause starting at 8:168; EG-NEXT: MOV * T0.X, 0.0,169; EG-NEXT: ALU clause starting at 9:170; EG-NEXT: BFE_INT * T0.W, T0.X, 0.0, literal.x,171; EG-NEXT: 8(1.121039e-44), 0(0.000000e+00)172; EG-NEXT: BFE_UINT T0.X, KC0[2].Y, 0.0, PV.W,173; EG-NEXT: LSHR * T1.X, KC0[2].W, literal.x,174; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)175;176; CM-LABEL: bzhi32_b1_indexzext:177; CM: ; %bb.0:178; CM-NEXT: ALU 0, @8, KC0[], KC1[]179; CM-NEXT: TEX 0 @6180; CM-NEXT: ALU 4, @9, KC0[CB0:0-32], KC1[]181; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X182; CM-NEXT: CF_END183; CM-NEXT: PAD184; CM-NEXT: Fetch clause starting at 6:185; CM-NEXT: VTX_READ_8 T0.X, T0.X, 40, #3186; CM-NEXT: ALU clause starting at 8:187; CM-NEXT: MOV * T0.X, 0.0,188; CM-NEXT: ALU clause starting at 9:189; CM-NEXT: BFE_INT * T0.W, T0.X, 0.0, literal.x,190; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)191; CM-NEXT: BFE_UINT * T0.X, KC0[2].Y, 0.0, PV.W,192; CM-NEXT: LSHR * T1.X, KC0[2].W, literal.x,193; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)194 %conv = zext i8 %numlowbits to i32195 %notmask = shl i32 -1, %conv196 %mask = xor i32 %notmask, -1197 %masked = and i32 %mask, %val198 store i32 %masked, ptr addrspace(1) %out199 ret void200}201 202define amdgpu_kernel void @bzhi32_b4_commutative(i32 %val, i32 %numlowbits, ptr addrspace(1) %out) {203; EG-LABEL: bzhi32_b4_commutative:204; EG: ; %bb.0:205; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]206; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1207; EG-NEXT: CF_END208; EG-NEXT: PAD209; EG-NEXT: ALU clause starting at 4:210; EG-NEXT: LSHR * T0.X, KC0[2].W, literal.x,211; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)212; EG-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z,213;214; CM-LABEL: bzhi32_b4_commutative:215; CM: ; %bb.0:216; CM-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]217; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X218; CM-NEXT: CF_END219; CM-NEXT: PAD220; CM-NEXT: ALU clause starting at 4:221; CM-NEXT: LSHR * T0.X, KC0[2].W, literal.x,222; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)223; CM-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z,224 %notmask = shl i32 -1, %numlowbits225 %mask = xor i32 %notmask, -1226 %masked = and i32 %val, %mask ; swapped order227 store i32 %masked, ptr addrspace(1) %out228 ret void229}230 231; ---------------------------------------------------------------------------- ;232; Pattern c. 32-bit233; ---------------------------------------------------------------------------- ;234 235define amdgpu_kernel void @bzhi32_c0(i32 %val, i32 %numlowbits, ptr addrspace(1) %out) {236; EG-LABEL: bzhi32_c0:237; EG: ; %bb.0:238; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]239; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1240; EG-NEXT: CF_END241; EG-NEXT: PAD242; EG-NEXT: ALU clause starting at 4:243; EG-NEXT: LSHR * T0.X, KC0[2].W, literal.x,244; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)245; EG-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z,246;247; CM-LABEL: bzhi32_c0:248; CM: ; %bb.0:249; CM-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]250; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X251; CM-NEXT: CF_END252; CM-NEXT: PAD253; CM-NEXT: ALU clause starting at 4:254; CM-NEXT: LSHR * T0.X, KC0[2].W, literal.x,255; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)256; CM-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z,257 %numhighbits = sub i32 32, %numlowbits258 %mask = lshr i32 -1, %numhighbits259 %masked = and i32 %mask, %val260 store i32 %masked, ptr addrspace(1) %out261 ret void262}263 264define amdgpu_kernel void @bzhi32_c1_indexzext(i32 %val, i8 %numlowbits, ptr addrspace(1) %out) {265; EG-LABEL: bzhi32_c1_indexzext:266; EG: ; %bb.0:267; EG-NEXT: ALU 0, @8, KC0[], KC1[]268; EG-NEXT: TEX 0 @6269; EG-NEXT: ALU 8, @9, KC0[CB0:0-32], KC1[]270; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1271; EG-NEXT: CF_END272; EG-NEXT: PAD273; EG-NEXT: Fetch clause starting at 6:274; EG-NEXT: VTX_READ_8 T0.X, T0.X, 40, #3275; EG-NEXT: ALU clause starting at 8:276; EG-NEXT: MOV * T0.X, 0.0,277; EG-NEXT: ALU clause starting at 9:278; EG-NEXT: SUB_INT * T0.W, literal.x, T0.X,279; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)280; EG-NEXT: AND_INT * T0.W, PV.W, literal.x,281; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)282; EG-NEXT: LSHR * T0.W, literal.x, PV.W,283; EG-NEXT: -1(nan), 0(0.000000e+00)284; EG-NEXT: AND_INT T0.X, PV.W, KC0[2].Y,285; EG-NEXT: LSHR * T1.X, KC0[2].W, literal.x,286; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)287;288; CM-LABEL: bzhi32_c1_indexzext:289; CM: ; %bb.0:290; CM-NEXT: ALU 0, @8, KC0[], KC1[]291; CM-NEXT: TEX 0 @6292; CM-NEXT: ALU 8, @9, KC0[CB0:0-32], KC1[]293; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X294; CM-NEXT: CF_END295; CM-NEXT: PAD296; CM-NEXT: Fetch clause starting at 6:297; CM-NEXT: VTX_READ_8 T0.X, T0.X, 40, #3298; CM-NEXT: ALU clause starting at 8:299; CM-NEXT: MOV * T0.X, 0.0,300; CM-NEXT: ALU clause starting at 9:301; CM-NEXT: SUB_INT * T0.W, literal.x, T0.X,302; CM-NEXT: 32(4.484155e-44), 0(0.000000e+00)303; CM-NEXT: AND_INT * T0.W, PV.W, literal.x,304; CM-NEXT: 255(3.573311e-43), 0(0.000000e+00)305; CM-NEXT: LSHR * T0.W, literal.x, PV.W,306; CM-NEXT: -1(nan), 0(0.000000e+00)307; CM-NEXT: AND_INT * T0.X, PV.W, KC0[2].Y,308; CM-NEXT: LSHR * T1.X, KC0[2].W, literal.x,309; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)310 %numhighbits = sub i8 32, %numlowbits311 %sh_prom = zext i8 %numhighbits to i32312 %mask = lshr i32 -1, %sh_prom313 %masked = and i32 %mask, %val314 store i32 %masked, ptr addrspace(1) %out315 ret void316}317 318define amdgpu_kernel void @bzhi32_c4_commutative(i32 %val, i32 %numlowbits, ptr addrspace(1) %out) {319; EG-LABEL: bzhi32_c4_commutative:320; EG: ; %bb.0:321; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]322; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1323; EG-NEXT: CF_END324; EG-NEXT: PAD325; EG-NEXT: ALU clause starting at 4:326; EG-NEXT: LSHR * T0.X, KC0[2].W, literal.x,327; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)328; EG-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z,329;330; CM-LABEL: bzhi32_c4_commutative:331; CM: ; %bb.0:332; CM-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]333; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X334; CM-NEXT: CF_END335; CM-NEXT: PAD336; CM-NEXT: ALU clause starting at 4:337; CM-NEXT: LSHR * T0.X, KC0[2].W, literal.x,338; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)339; CM-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z,340 %numhighbits = sub i32 32, %numlowbits341 %mask = lshr i32 -1, %numhighbits342 %masked = and i32 %val, %mask ; swapped order343 store i32 %masked, ptr addrspace(1) %out344 ret void345}346 347; ---------------------------------------------------------------------------- ;348; Pattern d. 32-bit.349; ---------------------------------------------------------------------------- ;350 351define amdgpu_kernel void @bzhi32_d0(i32 %val, i32 %numlowbits, ptr addrspace(1) %out) {352; EG-LABEL: bzhi32_d0:353; EG: ; %bb.0:354; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]355; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1356; EG-NEXT: CF_END357; EG-NEXT: PAD358; EG-NEXT: ALU clause starting at 4:359; EG-NEXT: LSHR * T0.X, KC0[2].W, literal.x,360; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)361; EG-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z,362;363; CM-LABEL: bzhi32_d0:364; CM: ; %bb.0:365; CM-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]366; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X367; CM-NEXT: CF_END368; CM-NEXT: PAD369; CM-NEXT: ALU clause starting at 4:370; CM-NEXT: LSHR * T0.X, KC0[2].W, literal.x,371; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)372; CM-NEXT: BFE_UINT * T1.X, KC0[2].Y, 0.0, KC0[2].Z,373 %numhighbits = sub i32 32, %numlowbits374 %highbitscleared = shl i32 %val, %numhighbits375 %masked = lshr i32 %highbitscleared, %numhighbits376 store i32 %masked, ptr addrspace(1) %out377 ret void378}379 380define amdgpu_kernel void @bzhi32_d1_indexzext(i32 %val, i8 %numlowbits, ptr addrspace(1) %out) {381; EG-LABEL: bzhi32_d1_indexzext:382; EG: ; %bb.0:383; EG-NEXT: ALU 0, @8, KC0[], KC1[]384; EG-NEXT: TEX 0 @6385; EG-NEXT: ALU 7, @9, KC0[CB0:0-32], KC1[]386; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1387; EG-NEXT: CF_END388; EG-NEXT: PAD389; EG-NEXT: Fetch clause starting at 6:390; EG-NEXT: VTX_READ_8 T0.X, T0.X, 40, #3391; EG-NEXT: ALU clause starting at 8:392; EG-NEXT: MOV * T0.X, 0.0,393; EG-NEXT: ALU clause starting at 9:394; EG-NEXT: SUB_INT * T0.W, literal.x, T0.X,395; EG-NEXT: 32(4.484155e-44), 0(0.000000e+00)396; EG-NEXT: AND_INT * T0.W, PV.W, literal.x,397; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)398; EG-NEXT: LSHL * T1.W, KC0[2].Y, PV.W,399; EG-NEXT: LSHR T0.X, PV.W, T0.W,400; EG-NEXT: LSHR * T1.X, KC0[2].W, literal.x,401; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)402;403; CM-LABEL: bzhi32_d1_indexzext:404; CM: ; %bb.0:405; CM-NEXT: ALU 0, @8, KC0[], KC1[]406; CM-NEXT: TEX 0 @6407; CM-NEXT: ALU 7, @9, KC0[CB0:0-32], KC1[]408; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X409; CM-NEXT: CF_END410; CM-NEXT: PAD411; CM-NEXT: Fetch clause starting at 6:412; CM-NEXT: VTX_READ_8 T0.X, T0.X, 40, #3413; CM-NEXT: ALU clause starting at 8:414; CM-NEXT: MOV * T0.X, 0.0,415; CM-NEXT: ALU clause starting at 9:416; CM-NEXT: SUB_INT * T0.W, literal.x, T0.X,417; CM-NEXT: 32(4.484155e-44), 0(0.000000e+00)418; CM-NEXT: AND_INT * T0.W, PV.W, literal.x,419; CM-NEXT: 255(3.573311e-43), 0(0.000000e+00)420; CM-NEXT: LSHL * T1.W, KC0[2].Y, PV.W,421; CM-NEXT: LSHR * T0.X, PV.W, T0.W,422; CM-NEXT: LSHR * T1.X, KC0[2].W, literal.x,423; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)424 %numhighbits = sub i8 32, %numlowbits425 %sh_prom = zext i8 %numhighbits to i32426 %highbitscleared = shl i32 %val, %sh_prom427 %masked = lshr i32 %highbitscleared, %sh_prom428 store i32 %masked, ptr addrspace(1) %out429 ret void430}431