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1; RUN: llc -mtriple=r600 -mcpu=cypress < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s2; RUN: llc -mtriple=r600 -mcpu=cayman < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s3 4; TODO: Add _RTN versions and merge with the GCN test5 6; FUNC-LABEL: {{^}}atomic_add_i32_offset:7; EG: MEM_RAT ATOMIC_ADD [[REG:T[0-9]+]]8; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z9define amdgpu_kernel void @atomic_add_i32_offset(ptr addrspace(1) %out, i32 %in) {10entry:11 %gep = getelementptr i32, ptr addrspace(1) %out, i64 412 %val = atomicrmw volatile add ptr addrspace(1) %gep, i32 %in seq_cst13 ret void14}15 16; FUNC-LABEL: {{^}}atomic_add_i32_soffset:17; EG: MEM_RAT ATOMIC_ADD [[REG:T[0-9]+]]18; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z19define amdgpu_kernel void @atomic_add_i32_soffset(ptr addrspace(1) %out, i32 %in) {20entry:21 %gep = getelementptr i32, ptr addrspace(1) %out, i64 900022 %val = atomicrmw volatile add ptr addrspace(1) %gep, i32 %in seq_cst23 ret void24}25 26; FUNC-LABEL: {{^}}atomic_add_i32_huge_offset:27; FIXME: looks like the offset is wrong28; EG: MEM_RAT ATOMIC_ADD [[REG:T[0-9]+]]29; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z30define amdgpu_kernel void @atomic_add_i32_huge_offset(ptr addrspace(1) %out, i32 %in) {31entry:32 %gep = getelementptr i32, ptr addrspace(1) %out, i64 4722423917559533 34 %val = atomicrmw volatile add ptr addrspace(1) %gep, i32 %in seq_cst35 ret void36}37 38; FUNC-LABEL: {{^}}atomic_add_i32_addr64_offset:39; EG: MEM_RAT ATOMIC_ADD [[REG:T[0-9]+]]40; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z41define amdgpu_kernel void @atomic_add_i32_addr64_offset(ptr addrspace(1) %out, i32 %in, i64 %index) {42entry:43 %ptr = getelementptr i32, ptr addrspace(1) %out, i64 %index44 %gep = getelementptr i32, ptr addrspace(1) %ptr, i64 445 %val = atomicrmw volatile add ptr addrspace(1) %gep, i32 %in seq_cst46 ret void47}48 49; FUNC-LABEL: {{^}}atomic_add_i32:50; EG: MEM_RAT ATOMIC_ADD [[REG:T[0-9]+]]51; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z52define amdgpu_kernel void @atomic_add_i32(ptr addrspace(1) %out, i32 %in) {53entry:54 %val = atomicrmw volatile add ptr addrspace(1) %out, i32 %in seq_cst55 ret void56}57 58; FUNC-LABEL: {{^}}atomic_add_i32_addr64:59; EG: MEM_RAT ATOMIC_ADD [[REG:T[0-9]+]]60; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z61define amdgpu_kernel void @atomic_add_i32_addr64(ptr addrspace(1) %out, i32 %in, i64 %index) {62entry:63 %ptr = getelementptr i32, ptr addrspace(1) %out, i64 %index64 %val = atomicrmw volatile add ptr addrspace(1) %ptr, i32 %in seq_cst65 ret void66}67 68; FUNC-LABEL: {{^}}atomic_and_i32_offset:69; EG: MEM_RAT ATOMIC_AND [[REG:T[0-9]+]]70; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z71define amdgpu_kernel void @atomic_and_i32_offset(ptr addrspace(1) %out, i32 %in) {72entry:73 %gep = getelementptr i32, ptr addrspace(1) %out, i64 474 %val = atomicrmw volatile and ptr addrspace(1) %gep, i32 %in seq_cst75 ret void76}77 78; FUNC-LABEL: {{^}}atomic_and_i32_addr64_offset:79; EG: MEM_RAT ATOMIC_AND [[REG:T[0-9]+]]80; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z81define amdgpu_kernel void @atomic_and_i32_addr64_offset(ptr addrspace(1) %out, i32 %in, i64 %index) {82entry:83 %ptr = getelementptr i32, ptr addrspace(1) %out, i64 %index84 %gep = getelementptr i32, ptr addrspace(1) %ptr, i64 485 %val = atomicrmw volatile and ptr addrspace(1) %gep, i32 %in seq_cst86 ret void87}88 89; FUNC-LABEL: {{^}}atomic_and_i32:90; EG: MEM_RAT ATOMIC_AND [[REG:T[0-9]+]]91; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z92define amdgpu_kernel void @atomic_and_i32(ptr addrspace(1) %out, i32 %in) {93entry:94 %val = atomicrmw volatile and ptr addrspace(1) %out, i32 %in seq_cst95 ret void96}97 98; FUNC-LABEL: {{^}}atomic_and_i32_addr64:99; EG: MEM_RAT ATOMIC_AND [[REG:T[0-9]+]]100; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z101define amdgpu_kernel void @atomic_and_i32_addr64(ptr addrspace(1) %out, i32 %in, i64 %index) {102entry:103 %ptr = getelementptr i32, ptr addrspace(1) %out, i64 %index104 %val = atomicrmw volatile and ptr addrspace(1) %ptr, i32 %in seq_cst105 ret void106}107 108; FUNC-LABEL: {{^}}atomic_sub_i32_offset:109; EG: MEM_RAT ATOMIC_SUB [[REG:T[0-9]+]]110; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z111define amdgpu_kernel void @atomic_sub_i32_offset(ptr addrspace(1) %out, i32 %in) {112entry:113 %gep = getelementptr i32, ptr addrspace(1) %out, i64 4114 %val = atomicrmw volatile sub ptr addrspace(1) %gep, i32 %in seq_cst115 ret void116}117 118; FUNC-LABEL: {{^}}atomic_sub_i32_addr64_offset:119; EG: MEM_RAT ATOMIC_SUB [[REG:T[0-9]+]]120; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z121define amdgpu_kernel void @atomic_sub_i32_addr64_offset(ptr addrspace(1) %out, i32 %in, i64 %index) {122entry:123 %ptr = getelementptr i32, ptr addrspace(1) %out, i64 %index124 %gep = getelementptr i32, ptr addrspace(1) %ptr, i64 4125 %val = atomicrmw volatile sub ptr addrspace(1) %gep, i32 %in seq_cst126 ret void127}128 129; FUNC-LABEL: {{^}}atomic_sub_i32:130; EG: MEM_RAT ATOMIC_SUB [[REG:T[0-9]+]]131; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z132define amdgpu_kernel void @atomic_sub_i32(ptr addrspace(1) %out, i32 %in) {133entry:134 %val = atomicrmw volatile sub ptr addrspace(1) %out, i32 %in seq_cst135 ret void136}137 138; FUNC-LABEL: {{^}}atomic_sub_i32_addr64:139; EG: MEM_RAT ATOMIC_SUB [[REG:T[0-9]+]]140; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z141define amdgpu_kernel void @atomic_sub_i32_addr64(ptr addrspace(1) %out, i32 %in, i64 %index) {142entry:143 %ptr = getelementptr i32, ptr addrspace(1) %out, i64 %index144 %val = atomicrmw volatile sub ptr addrspace(1) %ptr, i32 %in seq_cst145 ret void146}147 148; FUNC-LABEL: {{^}}atomic_max_i32_offset:149; EG: MEM_RAT ATOMIC_MAX_INT [[REG:T[0-9]+]]150; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z151define amdgpu_kernel void @atomic_max_i32_offset(ptr addrspace(1) %out, i32 %in) {152entry:153 %gep = getelementptr i32, ptr addrspace(1) %out, i64 4154 %val = atomicrmw volatile max ptr addrspace(1) %gep, i32 %in seq_cst155 ret void156}157 158; FUNC-LABEL: {{^}}atomic_max_i32_addr64_offset:159; EG: MEM_RAT ATOMIC_MAX_INT [[REG:T[0-9]+]]160; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z161define amdgpu_kernel void @atomic_max_i32_addr64_offset(ptr addrspace(1) %out, i32 %in, i64 %index) {162entry:163 %ptr = getelementptr i32, ptr addrspace(1) %out, i64 %index164 %gep = getelementptr i32, ptr addrspace(1) %ptr, i64 4165 %val = atomicrmw volatile max ptr addrspace(1) %gep, i32 %in seq_cst166 ret void167}168 169; FUNC-LABEL: {{^}}atomic_max_i32:170; EG: MEM_RAT ATOMIC_MAX_INT [[REG:T[0-9]+]]171; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z172define amdgpu_kernel void @atomic_max_i32(ptr addrspace(1) %out, i32 %in) {173entry:174 %val = atomicrmw volatile max ptr addrspace(1) %out, i32 %in seq_cst175 ret void176}177 178; FUNC-LABEL: {{^}}atomic_max_i32_addr64:179; EG: MEM_RAT ATOMIC_MAX_INT [[REG:T[0-9]+]]180; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z181define amdgpu_kernel void @atomic_max_i32_addr64(ptr addrspace(1) %out, i32 %in, i64 %index) {182entry:183 %ptr = getelementptr i32, ptr addrspace(1) %out, i64 %index184 %val = atomicrmw volatile max ptr addrspace(1) %ptr, i32 %in seq_cst185 ret void186}187 188; FUNC-LABEL: {{^}}atomic_umax_i32_offset:189; EG: MEM_RAT ATOMIC_MAX_UINT [[REG:T[0-9]+]]190; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z191define amdgpu_kernel void @atomic_umax_i32_offset(ptr addrspace(1) %out, i32 %in) {192entry:193 %gep = getelementptr i32, ptr addrspace(1) %out, i64 4194 %val = atomicrmw volatile umax ptr addrspace(1) %gep, i32 %in seq_cst195 ret void196}197 198; FUNC-LABEL: {{^}}atomic_umax_i32_addr64_offset:199; EG: MEM_RAT ATOMIC_MAX_UINT [[REG:T[0-9]+]]200; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z201define amdgpu_kernel void @atomic_umax_i32_addr64_offset(ptr addrspace(1) %out, i32 %in, i64 %index) {202entry:203 %ptr = getelementptr i32, ptr addrspace(1) %out, i64 %index204 %gep = getelementptr i32, ptr addrspace(1) %ptr, i64 4205 %val = atomicrmw volatile umax ptr addrspace(1) %gep, i32 %in seq_cst206 ret void207}208 209; FUNC-LABEL: {{^}}atomic_umax_i32:210; EG: MEM_RAT ATOMIC_MAX_UINT [[REG:T[0-9]+]]211; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z212define amdgpu_kernel void @atomic_umax_i32(ptr addrspace(1) %out, i32 %in) {213entry:214 %val = atomicrmw volatile umax ptr addrspace(1) %out, i32 %in seq_cst215 ret void216}217 218; FUNC-LABEL: {{^}}atomic_umax_i32_addr64:219; EG: MEM_RAT ATOMIC_MAX_UINT [[REG:T[0-9]+]]220; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z221define amdgpu_kernel void @atomic_umax_i32_addr64(ptr addrspace(1) %out, i32 %in, i64 %index) {222entry:223 %ptr = getelementptr i32, ptr addrspace(1) %out, i64 %index224 %val = atomicrmw volatile umax ptr addrspace(1) %ptr, i32 %in seq_cst225 ret void226}227 228; FUNC-LABEL: {{^}}atomic_min_i32_offset:229; EG: MEM_RAT ATOMIC_MIN_INT [[REG:T[0-9]+]]230; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z231define amdgpu_kernel void @atomic_min_i32_offset(ptr addrspace(1) %out, i32 %in) {232entry:233 %gep = getelementptr i32, ptr addrspace(1) %out, i64 4234 %val = atomicrmw volatile min ptr addrspace(1) %gep, i32 %in seq_cst235 ret void236}237 238; FUNC-LABEL: {{^}}atomic_min_i32_addr64_offset:239; EG: MEM_RAT ATOMIC_MIN_INT [[REG:T[0-9]+]]240; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z241define amdgpu_kernel void @atomic_min_i32_addr64_offset(ptr addrspace(1) %out, i32 %in, i64 %index) {242entry:243 %ptr = getelementptr i32, ptr addrspace(1) %out, i64 %index244 %gep = getelementptr i32, ptr addrspace(1) %ptr, i64 4245 %val = atomicrmw volatile min ptr addrspace(1) %gep, i32 %in seq_cst246 ret void247}248 249; FUNC-LABEL: {{^}}atomic_min_i32:250; EG: MEM_RAT ATOMIC_MIN_INT [[REG:T[0-9]+]]251; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z252define amdgpu_kernel void @atomic_min_i32(ptr addrspace(1) %out, i32 %in) {253entry:254 %val = atomicrmw volatile min ptr addrspace(1) %out, i32 %in seq_cst255 ret void256}257 258; FUNC-LABEL: {{^}}atomic_min_i32_addr64:259; EG: MEM_RAT ATOMIC_MIN_INT [[REG:T[0-9]+]]260; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z261define amdgpu_kernel void @atomic_min_i32_addr64(ptr addrspace(1) %out, i32 %in, i64 %index) {262entry:263 %ptr = getelementptr i32, ptr addrspace(1) %out, i64 %index264 %val = atomicrmw volatile min ptr addrspace(1) %ptr, i32 %in seq_cst265 ret void266}267 268; FUNC-LABEL: {{^}}atomic_umin_i32_offset:269; EG: MEM_RAT ATOMIC_MIN_UINT [[REG:T[0-9]+]]270; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z271define amdgpu_kernel void @atomic_umin_i32_offset(ptr addrspace(1) %out, i32 %in) {272entry:273 %gep = getelementptr i32, ptr addrspace(1) %out, i64 4274 %val = atomicrmw volatile umin ptr addrspace(1) %gep, i32 %in seq_cst275 ret void276}277 278; FUNC-LABEL: {{^}}atomic_umin_i32_addr64_offset:279; EG: MEM_RAT ATOMIC_MIN_UINT [[REG:T[0-9]+]]280; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z281define amdgpu_kernel void @atomic_umin_i32_addr64_offset(ptr addrspace(1) %out, i32 %in, i64 %index) {282entry:283 %ptr = getelementptr i32, ptr addrspace(1) %out, i64 %index284 %gep = getelementptr i32, ptr addrspace(1) %ptr, i64 4285 %val = atomicrmw volatile umin ptr addrspace(1) %gep, i32 %in seq_cst286 ret void287}288 289; FUNC-LABEL: {{^}}atomic_umin_i32:290; EG: MEM_RAT ATOMIC_MIN_UINT [[REG:T[0-9]+]]291; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z292define amdgpu_kernel void @atomic_umin_i32(ptr addrspace(1) %out, i32 %in) {293entry:294 %val = atomicrmw volatile umin ptr addrspace(1) %out, i32 %in seq_cst295 ret void296}297 298; FUNC-LABEL: {{^}}atomic_umin_i32_addr64:299; EG: MEM_RAT ATOMIC_MIN_UINT [[REG:T[0-9]+]]300; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z301define amdgpu_kernel void @atomic_umin_i32_addr64(ptr addrspace(1) %out, i32 %in, i64 %index) {302entry:303 %ptr = getelementptr i32, ptr addrspace(1) %out, i64 %index304 %val = atomicrmw volatile umin ptr addrspace(1) %ptr, i32 %in seq_cst305 ret void306}307 308; FUNC-LABEL: {{^}}atomic_or_i32_offset:309; EG: MEM_RAT ATOMIC_OR [[REG:T[0-9]+]]310; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z311define amdgpu_kernel void @atomic_or_i32_offset(ptr addrspace(1) %out, i32 %in) {312entry:313 %gep = getelementptr i32, ptr addrspace(1) %out, i64 4314 %val = atomicrmw volatile or ptr addrspace(1) %gep, i32 %in seq_cst315 ret void316}317 318; FUNC-LABEL: {{^}}atomic_or_i32_addr64_offset:319; EG: MEM_RAT ATOMIC_OR [[REG:T[0-9]+]]320; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z321define amdgpu_kernel void @atomic_or_i32_addr64_offset(ptr addrspace(1) %out, i32 %in, i64 %index) {322entry:323 %ptr = getelementptr i32, ptr addrspace(1) %out, i64 %index324 %gep = getelementptr i32, ptr addrspace(1) %ptr, i64 4325 %val = atomicrmw volatile or ptr addrspace(1) %gep, i32 %in seq_cst326 ret void327}328 329; FUNC-LABEL: {{^}}atomic_or_i32:330; EG: MEM_RAT ATOMIC_OR [[REG:T[0-9]+]]331; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z332define amdgpu_kernel void @atomic_or_i32(ptr addrspace(1) %out, i32 %in) {333entry:334 %val = atomicrmw volatile or ptr addrspace(1) %out, i32 %in seq_cst335 ret void336}337 338; FUNC-LABEL: {{^}}atomic_or_i32_addr64:339; EG: MEM_RAT ATOMIC_OR [[REG:T[0-9]+]]340; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z341define amdgpu_kernel void @atomic_or_i32_addr64(ptr addrspace(1) %out, i32 %in, i64 %index) {342entry:343 %ptr = getelementptr i32, ptr addrspace(1) %out, i64 %index344 %val = atomicrmw volatile or ptr addrspace(1) %ptr, i32 %in seq_cst345 ret void346}347 348; FUNC-LABEL: {{^}}atomic_xchg_i32_offset:349; EG: MEM_RAT ATOMIC_XCHG_INT [[REG:T[0-9]+]]350; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z351define amdgpu_kernel void @atomic_xchg_i32_offset(ptr addrspace(1) %out, i32 %in) {352entry:353 %gep = getelementptr i32, ptr addrspace(1) %out, i64 4354 %val = atomicrmw volatile xchg ptr addrspace(1) %gep, i32 %in seq_cst355 ret void356}357 358; FUNC-LABEL: {{^}}atomic_xchg_i32_addr64_offset:359; EG: MEM_RAT ATOMIC_XCHG_INT [[REG:T[0-9]+]]360; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z361define amdgpu_kernel void @atomic_xchg_i32_addr64_offset(ptr addrspace(1) %out, i32 %in, i64 %index) {362entry:363 %ptr = getelementptr i32, ptr addrspace(1) %out, i64 %index364 %gep = getelementptr i32, ptr addrspace(1) %ptr, i64 4365 %val = atomicrmw volatile xchg ptr addrspace(1) %gep, i32 %in seq_cst366 ret void367}368 369; FUNC-LABEL: {{^}}atomic_xchg_i32:370; EG: MEM_RAT ATOMIC_XCHG_INT [[REG:T[0-9]+]]371; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z372define amdgpu_kernel void @atomic_xchg_i32(ptr addrspace(1) %out, i32 %in) {373entry:374 %val = atomicrmw volatile xchg ptr addrspace(1) %out, i32 %in seq_cst375 ret void376}377 378; FUNC-LABEL: {{^}}atomic_xchg_i32_addr64:379; EG: MEM_RAT ATOMIC_XCHG_INT [[REG:T[0-9]+]]380; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z381define amdgpu_kernel void @atomic_xchg_i32_addr64(ptr addrspace(1) %out, i32 %in, i64 %index) {382entry:383 %ptr = getelementptr i32, ptr addrspace(1) %out, i64 %index384 %val = atomicrmw volatile xchg ptr addrspace(1) %ptr, i32 %in seq_cst385 ret void386}387 388; FUNC-LABEL: {{^}}atomic_cmpxchg_i32_offset:389; EG: MEM_RAT ATOMIC_CMPXCHG_INT [[REG:T[0-9]+]]390; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z391define amdgpu_kernel void @atomic_cmpxchg_i32_offset(ptr addrspace(1) %out, i32 %in, i32 %old) {392entry:393 %gep = getelementptr i32, ptr addrspace(1) %out, i64 4394 %val = cmpxchg volatile ptr addrspace(1) %gep, i32 %old, i32 %in seq_cst seq_cst395 ret void396}397 398; FUNC-LABEL: {{^}}atomic_cmpxchg_i32_addr64_offset:399; EG: MEM_RAT ATOMIC_CMPXCHG_INT [[REG:T[0-9]+]]400; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z401define amdgpu_kernel void @atomic_cmpxchg_i32_addr64_offset(ptr addrspace(1) %out, i32 %in, i64 %index, i32 %old) {402entry:403 %ptr = getelementptr i32, ptr addrspace(1) %out, i64 %index404 %gep = getelementptr i32, ptr addrspace(1) %ptr, i64 4405 %val = cmpxchg volatile ptr addrspace(1) %gep, i32 %old, i32 %in seq_cst seq_cst406 ret void407}408 409; FUNC-LABEL: {{^}}atomic_cmpxchg_i32:410; EG: MEM_RAT ATOMIC_CMPXCHG_INT [[REG:T[0-9]+]]411; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z412define amdgpu_kernel void @atomic_cmpxchg_i32(ptr addrspace(1) %out, i32 %in, i32 %old) {413entry:414 %val = cmpxchg volatile ptr addrspace(1) %out, i32 %old, i32 %in seq_cst seq_cst415 ret void416}417 418; FUNC-LABEL: {{^}}atomic_cmpxchg_i32_addr64:419; EG: MEM_RAT ATOMIC_CMPXCHG_INT [[REG:T[0-9]+]]420; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z421define amdgpu_kernel void @atomic_cmpxchg_i32_addr64(ptr addrspace(1) %out, i32 %in, i64 %index, i32 %old) {422entry:423 %ptr = getelementptr i32, ptr addrspace(1) %out, i64 %index424 %val = cmpxchg volatile ptr addrspace(1) %ptr, i32 %old, i32 %in seq_cst seq_cst425 ret void426}427 428; FUNC-LABEL: {{^}}atomic_xor_i32_offset:429; EG: MEM_RAT ATOMIC_XOR [[REG:T[0-9]+]]430; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z431define amdgpu_kernel void @atomic_xor_i32_offset(ptr addrspace(1) %out, i32 %in) {432entry:433 %gep = getelementptr i32, ptr addrspace(1) %out, i64 4434 %val = atomicrmw volatile xor ptr addrspace(1) %gep, i32 %in seq_cst435 ret void436}437 438; FUNC-LABEL: {{^}}atomic_xor_i32_addr64_offset:439; EG: MEM_RAT ATOMIC_XOR [[REG:T[0-9]+]]440; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z441define amdgpu_kernel void @atomic_xor_i32_addr64_offset(ptr addrspace(1) %out, i32 %in, i64 %index) {442entry:443 %ptr = getelementptr i32, ptr addrspace(1) %out, i64 %index444 %gep = getelementptr i32, ptr addrspace(1) %ptr, i64 4445 %val = atomicrmw volatile xor ptr addrspace(1) %gep, i32 %in seq_cst446 ret void447}448 449; FUNC-LABEL: {{^}}atomic_xor_i32:450; EG: MEM_RAT ATOMIC_XOR [[REG:T[0-9]+]]451; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z452define amdgpu_kernel void @atomic_xor_i32(ptr addrspace(1) %out, i32 %in) {453entry:454 %val = atomicrmw volatile xor ptr addrspace(1) %out, i32 %in seq_cst455 ret void456}457 458; FUNC-LABEL: {{^}}atomic_xor_i32_addr64:459; EG: MEM_RAT ATOMIC_XOR [[REG:T[0-9]+]]460; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Z461define amdgpu_kernel void @atomic_xor_i32_addr64(ptr addrspace(1) %out, i32 %in, i64 %index) {462entry:463 %ptr = getelementptr i32, ptr addrspace(1) %out, i64 %index464 %val = atomicrmw volatile xor ptr addrspace(1) %ptr, i32 %in seq_cst465 ret void466}467 468; FUNC-LABEL: {{^}}atomic_store_i32_offset:469; EG: MEM_RAT ATOMIC_XCHG_INT [[REG:T[0-9]+]]470; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Y471define amdgpu_kernel void @atomic_store_i32_offset(i32 %in, ptr addrspace(1) %out) {472entry:473 %gep = getelementptr i32, ptr addrspace(1) %out, i64 4474 store atomic i32 %in, ptr addrspace(1) %gep seq_cst, align 4475 ret void476}477 478; FUNC-LABEL: {{^}}atomic_store_i32:479; EG: MEM_RAT ATOMIC_XCHG_INT [[REG:T[0-9]+]]480; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Y481define amdgpu_kernel void @atomic_store_i32(i32 %in, ptr addrspace(1) %out) {482entry:483 store atomic i32 %in, ptr addrspace(1) %out seq_cst, align 4484 ret void485}486 487; FUNC-LABEL: {{^}}atomic_store_i32_addr64_offset:488; EG: MEM_RAT ATOMIC_XCHG_INT [[REG:T[0-9]+]]489; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Y490define amdgpu_kernel void @atomic_store_i32_addr64_offset(i32 %in, ptr addrspace(1) %out, i64 %index) {491entry:492 %ptr = getelementptr i32, ptr addrspace(1) %out, i64 %index493 %gep = getelementptr i32, ptr addrspace(1) %ptr, i64 4494 store atomic i32 %in, ptr addrspace(1) %gep seq_cst, align 4495 ret void496}497 498; FUNC-LABEL: {{^}}atomic_store_i32_addr64:499; EG: MEM_RAT ATOMIC_XCHG_INT [[REG:T[0-9]+]]500; EG: MOV{{[ *]*}}[[REG]].X, KC0[2].Y501define amdgpu_kernel void @atomic_store_i32_addr64(i32 %in, ptr addrspace(1) %out, i64 %index) {502entry:503 %ptr = getelementptr i32, ptr addrspace(1) %out, i64 %index504 store atomic i32 %in, ptr addrspace(1) %ptr seq_cst, align 4505 ret void506}507 508; FUNC-LABEL: {{^}}atomic_add_1509; EG: MEM_RAT ATOMIC_ADD510define amdgpu_kernel void @atomic_add_1(ptr addrspace(1) %out) {511entry:512 %gep = getelementptr i32, ptr addrspace(1) %out, i64 4513 %val = atomicrmw volatile add ptr addrspace(1) %gep, i32 1 seq_cst514 ret void515}516 517; FUNC-LABEL: {{^}}atomic_add_neg1518; EG: MEM_RAT ATOMIC_ADD519define amdgpu_kernel void @atomic_add_neg1(ptr addrspace(1) %out) {520entry:521 %gep = getelementptr i32, ptr addrspace(1) %out, i64 4522 %val = atomicrmw volatile add ptr addrspace(1) %gep, i32 -1 seq_cst523 ret void524}525 526; FUNC-LABEL: {{^}}atomic_sub_neg1527; EG: MEM_RAT ATOMIC_SUB528define amdgpu_kernel void @atomic_sub_neg1(ptr addrspace(1) %out) {529entry:530 %gep = getelementptr i32, ptr addrspace(1) %out, i64 4531 %val = atomicrmw volatile sub ptr addrspace(1) %gep, i32 -1 seq_cst532 ret void533}534 535; FUNC-LABEL: {{^}}atomic_sub_1536; EG: MEM_RAT ATOMIC_SUB537define amdgpu_kernel void @atomic_sub_1(ptr addrspace(1) %out) {538entry:539 %gep = getelementptr i32, ptr addrspace(1) %out, i64 4540 %val = atomicrmw volatile sub ptr addrspace(1) %gep, i32 1 seq_cst541 ret void542}543