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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 52; RUN: llc -mtriple=r600-- -mcpu=cayman < %s | FileCheck -check-prefix=CM %s3 4define amdgpu_kernel void @isnan_f32(ptr addrspace(1) %out, float %x) {5; CM-LABEL: isnan_f32:6; CM: ; %bb.0:7; CM-NEXT: ALU 6, @4, KC0[CB0:0-32], KC1[]8; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X9; CM-NEXT: CF_END10; CM-NEXT: PAD11; CM-NEXT: ALU clause starting at 4:12; CM-NEXT: AND_INT * T0.W, KC0[2].Z, literal.x,13; CM-NEXT: 2147483647(nan), 0(0.000000e+00)14; CM-NEXT: SETGT_INT * T0.W, PV.W, literal.x,15; CM-NEXT: 2139095040(INF), 0(0.000000e+00)16; CM-NEXT: AND_INT * T0.X, PV.W, 1,17; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,18; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)19 %result = call i1 @llvm.is.fpclass.f32(float %x, i32 3) ; nan20 %zext = zext i1 %result to i3221 store i32 %zext, ptr addrspace(1) %out, align 422 ret void23}24 25define amdgpu_kernel void @issue135083_f32(ptr addrspace(1) %out, float %x) {26; CM-LABEL: issue135083_f32:27; CM: ; %bb.0:28; CM-NEXT: ALU 6, @4, KC0[CB0:0-32], KC1[]29; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X30; CM-NEXT: CF_END31; CM-NEXT: PAD32; CM-NEXT: ALU clause starting at 4:33; CM-NEXT: AND_INT * T0.W, KC0[2].Z, literal.x,34; CM-NEXT: 2147483647(nan), 0(0.000000e+00)35; CM-NEXT: SETGT_INT * T0.W, literal.x, PV.W,36; CM-NEXT: 2139095040(INF), 0(0.000000e+00)37; CM-NEXT: AND_INT * T0.X, PV.W, 1,38; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,39; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)40 %result = call i1 @llvm.is.fpclass.f32(float %x, i32 504)41 %zext = zext i1 %result to i3242 store i32 %zext, ptr addrspace(1) %out, align 443 ret void44}45 46define amdgpu_kernel void @issue135083_v2f32(ptr addrspace(1) %out, <2 x float> %x) {47; CM-LABEL: issue135083_v2f32:48; CM: ; %bb.0:49; CM-NEXT: ALU 10, @4, KC0[CB0:0-32], KC1[]50; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T1.X51; CM-NEXT: CF_END52; CM-NEXT: PAD53; CM-NEXT: ALU clause starting at 4:54; CM-NEXT: AND_INT * T0.W, KC0[3].X, literal.x,55; CM-NEXT: 2147483647(nan), 0(0.000000e+00)56; CM-NEXT: AND_INT T0.Z, KC0[2].W, literal.x,57; CM-NEXT: SETGT_INT * T0.W, PV.W, literal.y,58; CM-NEXT: 2147483647(nan), 2139095039(3.402823e+38)59; CM-NEXT: CNDE_INT T0.Y, PV.W, 1, 0.0,60; CM-NEXT: SETGT_INT * T0.W, PV.Z, literal.x,61; CM-NEXT: 2139095039(3.402823e+38), 0(0.000000e+00)62; CM-NEXT: CNDE_INT * T0.X, PV.W, 1, 0.0,63; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,64; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)65 %result = call <2 x i1> @llvm.is.fpclass.v2f32(<2 x float> %x, i32 504)66 %zext = zext <2 x i1> %result to <2 x i32>67 store <2 x i32> %zext, ptr addrspace(1) %out, align 868 ret void69}70 71define amdgpu_kernel void @issue135083_v3f32(ptr addrspace(1) %out, <3 x float> %x) {72; CM-LABEL: issue135083_v3f32:73; CM: ; %bb.0:74; CM-NEXT: ALU 17, @4, KC0[CB0:0-32], KC1[]75; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T2, T3.X76; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X77; CM-NEXT: CF_END78; CM-NEXT: ALU clause starting at 4:79; CM-NEXT: AND_INT * T0.W, KC0[3].W, literal.x,80; CM-NEXT: 2147483647(nan), 0(0.000000e+00)81; CM-NEXT: AND_INT T0.Z, KC0[3].Z, literal.x,82; CM-NEXT: SETGT_INT * T0.W, PV.W, literal.y,83; CM-NEXT: 2147483647(nan), 2139095039(3.402823e+38)84; CM-NEXT: CNDE_INT T0.X, PV.W, 1, 0.0,85; CM-NEXT: AND_INT T0.Y, KC0[3].Y, literal.x,86; CM-NEXT: SETGT_INT T0.Z, PV.Z, literal.y,87; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.z,88; CM-NEXT: 2147483647(nan), 2139095039(3.402823e+38)89; CM-NEXT: 8(1.121039e-44), 0(0.000000e+00)90; CM-NEXT: LSHR T1.X, PV.W, literal.x,91; CM-NEXT: CNDE_INT T2.Y, PV.Z, 1, 0.0,92; CM-NEXT: SETGT_INT * T0.W, PV.Y, literal.y,93; CM-NEXT: 2(2.802597e-45), 2139095039(3.402823e+38)94; CM-NEXT: CNDE_INT * T2.X, PV.W, 1, 0.0,95; CM-NEXT: LSHR * T3.X, KC0[2].Y, literal.x,96; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)97 %result = call <3 x i1> @llvm.is.fpclass.v3f32(<3 x float> %x, i32 504)98 %zext = zext <3 x i1> %result to <3 x i32>99 store <3 x i32> %zext, ptr addrspace(1) %out, align 16100 ret void101}102 103define amdgpu_kernel void @issue135083_v4f32(ptr addrspace(1) %out, <4 x float> %x) {104; CM-LABEL: issue135083_v4f32:105; CM: ; %bb.0:106; CM-NEXT: ALU 18, @4, KC0[CB0:0-32], KC1[]107; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T1.X108; CM-NEXT: CF_END109; CM-NEXT: PAD110; CM-NEXT: ALU clause starting at 4:111; CM-NEXT: AND_INT * T0.W, KC0[4].X, literal.x,112; CM-NEXT: 2147483647(nan), 0(0.000000e+00)113; CM-NEXT: SETGT_INT T0.Z, PV.W, literal.x,114; CM-NEXT: AND_INT * T0.W, KC0[3].W, literal.y,115; CM-NEXT: 2139095039(3.402823e+38), 2147483647(nan)116; CM-NEXT: AND_INT T0.Y, KC0[3].Z, literal.x,117; CM-NEXT: SETGT_INT T1.Z, PV.W, literal.y,118; CM-NEXT: CNDE_INT * T0.W, PV.Z, 1, 0.0,119; CM-NEXT: 2147483647(nan), 2139095039(3.402823e+38)120; CM-NEXT: AND_INT T1.Y, KC0[3].Y, literal.x,121; CM-NEXT: CNDE_INT T0.Z, PV.Z, 1, 0.0,122; CM-NEXT: SETGT_INT * T1.W, PV.Y, literal.y,123; CM-NEXT: 2147483647(nan), 2139095039(3.402823e+38)124; CM-NEXT: CNDE_INT T0.Y, PV.W, 1, 0.0,125; CM-NEXT: SETGT_INT * T1.W, PV.Y, literal.x,126; CM-NEXT: 2139095039(3.402823e+38), 0(0.000000e+00)127; CM-NEXT: CNDE_INT * T0.X, PV.W, 1, 0.0,128; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,129; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)130 %result = call <4 x i1> @llvm.is.fpclass.v4f32(<4 x float> %x, i32 504)131 %zext = zext <4 x i1> %result to <4 x i32>132 store <4 x i32> %zext, ptr addrspace(1) %out, align 16133 ret void134}135 136define amdgpu_kernel void @issue135083_v5f32(ptr addrspace(1) %out, <5 x float> %x) {137; CM-LABEL: issue135083_v5f32:138; CM: ; %bb.0:139; CM-NEXT: ALU 23, @4, KC0[CB0:0-32], KC1[]140; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1, T3.X141; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T2.X, T0.X142; CM-NEXT: CF_END143; CM-NEXT: ALU clause starting at 4:144; CM-NEXT: AND_INT T0.Z, KC0[4].Y, literal.x,145; CM-NEXT: AND_INT * T0.W, KC0[5].X, literal.x,146; CM-NEXT: 2147483647(nan), 0(0.000000e+00)147; CM-NEXT: SETGT_INT T0.Y, PV.W, literal.x,148; CM-NEXT: AND_INT T1.Z, KC0[5].Y, literal.y,149; CM-NEXT: AND_INT * T0.W, KC0[4].W, literal.y,150; CM-NEXT: 2139095039(3.402823e+38), 2147483647(nan)151; CM-NEXT: SETGT_INT T0.X, PV.W, literal.x,152; CM-NEXT: AND_INT T1.Y, KC0[4].Z, literal.y,153; CM-NEXT: SETGT_INT T1.Z, PV.Z, literal.x,154; CM-NEXT: CNDE_INT * T1.W, PV.Y, 1, 0.0,155; CM-NEXT: 2139095039(3.402823e+38), 2147483647(nan)156; CM-NEXT: CNDE_INT T2.X, PV.Z, 1, 0.0,157; CM-NEXT: SETGT_INT T0.Y, PV.Y, literal.x,158; CM-NEXT: CNDE_INT T1.Z, PV.X, 1, 0.0,159; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,160; CM-NEXT: 2139095039(3.402823e+38), 16(2.242078e-44)161; CM-NEXT: LSHR T0.X, PV.W, literal.x,162; CM-NEXT: CNDE_INT T1.Y, PV.Y, 1, 0.0,163; CM-NEXT: SETGT_INT * T0.W, T0.Z, literal.y,164; CM-NEXT: 2(2.802597e-45), 2139095039(3.402823e+38)165; CM-NEXT: CNDE_INT * T1.X, PV.W, 1, 0.0,166; CM-NEXT: LSHR * T3.X, KC0[2].Y, literal.x,167; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)168 %result = call <5 x i1> @llvm.is.fpclass.v5f32(<5 x float> %x, i32 504)169 %zext = zext <5 x i1> %result to <5 x i32>170 store <5 x i32> %zext, ptr addrspace(1) %out, align 32171 ret void172}173 174define amdgpu_kernel void @issue135083_v6f32(ptr addrspace(1) %out, <6 x float> %x) {175; CM-LABEL: issue135083_v6f32:176; CM: ; %bb.0:177; CM-NEXT: ALU 27, @4, KC0[CB0:0-32], KC1[]178; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1, T3.X179; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T2, T0.X180; CM-NEXT: CF_END181; CM-NEXT: ALU clause starting at 4:182; CM-NEXT: AND_INT T0.Z, KC0[4].Y, literal.x,183; CM-NEXT: AND_INT * T0.W, KC0[5].Z, literal.x,184; CM-NEXT: 2147483647(nan), 0(0.000000e+00)185; CM-NEXT: AND_INT T1.Z, KC0[5].X, literal.x,186; CM-NEXT: AND_INT * T1.W, KC0[4].W, literal.x,187; CM-NEXT: 2147483647(nan), 0(0.000000e+00)188; CM-NEXT: SETGT_INT T0.X, PV.W, literal.x,189; CM-NEXT: SETGT_INT T0.Y, PV.Z, literal.x,190; CM-NEXT: AND_INT T1.Z, KC0[5].Y, literal.y,191; CM-NEXT: SETGT_INT * T0.W, T0.W, literal.x,192; CM-NEXT: 2139095039(3.402823e+38), 2147483647(nan)193; CM-NEXT: AND_INT T1.X, KC0[4].Z, literal.x,194; CM-NEXT: CNDE_INT T2.Y, PV.W, 1, 0.0,195; CM-NEXT: SETGT_INT T1.Z, PV.Z, literal.y,196; CM-NEXT: CNDE_INT * T1.W, PV.Y, 1, 0.0,197; CM-NEXT: 2147483647(nan), 2139095039(3.402823e+38)198; CM-NEXT: CNDE_INT T2.X, PV.Z, 1, 0.0,199; CM-NEXT: SETGT_INT T0.Y, PV.X, literal.x,200; CM-NEXT: CNDE_INT T1.Z, T0.X, 1, 0.0,201; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,202; CM-NEXT: 2139095039(3.402823e+38), 16(2.242078e-44)203; CM-NEXT: LSHR T0.X, PV.W, literal.x,204; CM-NEXT: CNDE_INT T1.Y, PV.Y, 1, 0.0,205; CM-NEXT: SETGT_INT * T0.W, T0.Z, literal.y,206; CM-NEXT: 2(2.802597e-45), 2139095039(3.402823e+38)207; CM-NEXT: CNDE_INT * T1.X, PV.W, 1, 0.0,208; CM-NEXT: LSHR * T3.X, KC0[2].Y, literal.x,209; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)210 %result = call <6 x i1> @llvm.is.fpclass.v6f32(<6 x float> %x, i32 504)211 %zext = zext <6 x i1> %result to <6 x i32>212 store <6 x i32> %zext, ptr addrspace(1) %out, align 32213 ret void214}215 216define amdgpu_kernel void @issue135083_v7f32(ptr addrspace(1) %out, <7 x float> %x) {217; CM-LABEL: issue135083_v7f32:218; CM: ; %bb.0:219; CM-NEXT: ALU 34, @6, KC0[CB0:0-32], KC1[]220; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T4, T5.X221; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T3, T0.X222; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T2.X223; CM-NEXT: CF_END224; CM-NEXT: PAD225; CM-NEXT: ALU clause starting at 6:226; CM-NEXT: AND_INT T0.Z, KC0[4].Y, literal.x,227; CM-NEXT: AND_INT * T0.W, KC0[4].W, literal.x,228; CM-NEXT: 2147483647(nan), 0(0.000000e+00)229; CM-NEXT: SETGT_INT T0.Y, PV.W, literal.x,230; CM-NEXT: AND_INT T1.Z, KC0[5].W, literal.y,231; CM-NEXT: AND_INT * T0.W, KC0[5].X, literal.y,232; CM-NEXT: 2139095039(3.402823e+38), 2147483647(nan)233; CM-NEXT: AND_INT T0.X, KC0[4].Z, literal.x,234; CM-NEXT: SETGT_INT T1.Y, PV.W, literal.y,235; CM-NEXT: AND_INT T2.Z, KC0[5].Z, literal.x,236; CM-NEXT: SETGT_INT * T0.W, PV.Z, literal.y,237; CM-NEXT: 2147483647(nan), 2139095039(3.402823e+38)238; CM-NEXT: CNDE_INT T1.X, PV.W, 1, 0.0,239; CM-NEXT: AND_INT T2.Y, KC0[5].Y, literal.x,240; CM-NEXT: SETGT_INT T1.Z, PV.Z, literal.y,241; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.z,242; CM-NEXT: 2147483647(nan), 2139095039(3.402823e+38)243; CM-NEXT: 24(3.363116e-44), 0(0.000000e+00)244; CM-NEXT: LSHR T2.X, PV.W, literal.x,245; CM-NEXT: CNDE_INT T3.Y, PV.Z, 1, 0.0,246; CM-NEXT: SETGT_INT T1.Z, PV.Y, literal.y,247; CM-NEXT: CNDE_INT * T4.W, T1.Y, 1, 0.0,248; CM-NEXT: 2(2.802597e-45), 2139095039(3.402823e+38)249; CM-NEXT: CNDE_INT T3.X, PV.Z, 1, 0.0,250; CM-NEXT: SETGT_INT T1.Y, T0.X, literal.x,251; CM-NEXT: CNDE_INT T4.Z, T0.Y, 1, 0.0,252; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,253; CM-NEXT: 2139095039(3.402823e+38), 16(2.242078e-44)254; CM-NEXT: LSHR T0.X, PV.W, literal.x,255; CM-NEXT: CNDE_INT T4.Y, PV.Y, 1, 0.0,256; CM-NEXT: SETGT_INT * T0.W, T0.Z, literal.y,257; CM-NEXT: 2(2.802597e-45), 2139095039(3.402823e+38)258; CM-NEXT: CNDE_INT * T4.X, PV.W, 1, 0.0,259; CM-NEXT: LSHR * T5.X, KC0[2].Y, literal.x,260; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)261 %result = call <7 x i1> @llvm.is.fpclass.v7f32(<7 x float> %x, i32 504)262 %zext = zext <7 x i1> %result to <7 x i32>263 store <7 x i32> %zext, ptr addrspace(1) %out, align 32264 ret void265}266 267define amdgpu_kernel void @issue135083_v8f32(ptr addrspace(1) %out, <8 x float> %x) {268; CM-LABEL: issue135083_v8f32:269; CM: ; %bb.0:270; CM-NEXT: ALU 34, @4, KC0[CB0:0-32], KC1[]271; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0, T3.X272; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1, T2.X273; CM-NEXT: CF_END274; CM-NEXT: ALU clause starting at 4:275; CM-NEXT: AND_INT T0.Z, KC0[6].X, literal.x,276; CM-NEXT: AND_INT * T0.W, KC0[4].W, literal.x,277; CM-NEXT: 2147483647(nan), 0(0.000000e+00)278; CM-NEXT: AND_INT T0.X, KC0[4].Y, literal.x,279; CM-NEXT: SETGT_INT T0.Y, PV.W, literal.y,280; CM-NEXT: SETGT_INT T0.Z, PV.Z, literal.y,281; CM-NEXT: AND_INT * T0.W, KC0[5].W, literal.x,282; CM-NEXT: 2147483647(nan), 2139095039(3.402823e+38)283; CM-NEXT: AND_INT T1.X, KC0[5].Z, literal.x,284; CM-NEXT: SETGT_INT T1.Y, PV.W, literal.y,285; CM-NEXT: AND_INT T1.Z, KC0[5].X, literal.x,286; CM-NEXT: CNDE_INT * T1.W, PV.Z, 1, 0.0,287; CM-NEXT: 2147483647(nan), 2139095039(3.402823e+38)288; CM-NEXT: SETGT_INT T2.X, PV.Z, literal.x,289; CM-NEXT: AND_INT T2.Y, KC0[5].Y, literal.y,290; CM-NEXT: CNDE_INT T1.Z, PV.Y, 1, 0.0,291; CM-NEXT: SETGT_INT * T0.W, PV.X, literal.x,292; CM-NEXT: 2139095039(3.402823e+38), 2147483647(nan)293; CM-NEXT: AND_INT T3.X, KC0[4].Z, literal.x,294; CM-NEXT: CNDE_INT T1.Y, PV.W, 1, 0.0,295; CM-NEXT: SETGT_INT T0.Z, PV.Y, literal.y,296; CM-NEXT: CNDE_INT * T0.W, PV.X, 1, 0.0,297; CM-NEXT: 2147483647(nan), 2139095039(3.402823e+38)298; CM-NEXT: CNDE_INT T1.X, PV.Z, 1, 0.0,299; CM-NEXT: SETGT_INT T2.Y, PV.X, literal.x,300; CM-NEXT: CNDE_INT T0.Z, T0.Y, 1, 0.0,301; CM-NEXT: ADD_INT * T2.W, KC0[2].Y, literal.y,302; CM-NEXT: 2139095039(3.402823e+38), 16(2.242078e-44)303; CM-NEXT: LSHR T2.X, PV.W, literal.x,304; CM-NEXT: CNDE_INT T0.Y, PV.Y, 1, 0.0,305; CM-NEXT: SETGT_INT * T2.W, T0.X, literal.y,306; CM-NEXT: 2(2.802597e-45), 2139095039(3.402823e+38)307; CM-NEXT: CNDE_INT * T0.X, PV.W, 1, 0.0,308; CM-NEXT: LSHR * T3.X, KC0[2].Y, literal.x,309; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)310 %result = call <8 x i1> @llvm.is.fpclass.v3f32(<8 x float> %x, i32 504)311 %zext = zext <8 x i1> %result to <8 x i32>312 store <8 x i32> %zext, ptr addrspace(1) %out, align 32313 ret void314}315 316define amdgpu_kernel void @issue135083_v16f32(ptr addrspace(1) %out, <16 x float> %x) {317; CM-LABEL: issue135083_v16f32:318; CM: ; %bb.0:319; CM-NEXT: ALU 69, @6, KC0[CB0:0-32], KC1[]320; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1, T7.X321; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T2, T0.X322; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T3, T6.X323; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T4, T5.X324; CM-NEXT: CF_END325; CM-NEXT: ALU clause starting at 6:326; CM-NEXT: AND_INT T0.Z, KC0[6].Y, literal.x,327; CM-NEXT: AND_INT * T0.W, KC0[6].W, literal.x,328; CM-NEXT: 2147483647(nan), 0(0.000000e+00)329; CM-NEXT: SETGT_INT T0.X, PV.W, literal.x,330; CM-NEXT: AND_INT T0.Y, KC0[6].Z, literal.y,331; CM-NEXT: AND_INT T1.Z, KC0[7].Y, literal.y,332; CM-NEXT: AND_INT * T0.W, KC0[7].X, literal.y,333; CM-NEXT: 2139095039(3.402823e+38), 2147483647(nan)334; CM-NEXT: SETGT_INT T1.X, PV.W, literal.x,335; CM-NEXT: AND_INT T1.Y, KC0[7].Z, literal.y,336; CM-NEXT: AND_INT T2.Z, KC0[8].X, literal.y,337; CM-NEXT: AND_INT * T0.W, KC0[7].W, literal.y,338; CM-NEXT: 2139095039(3.402823e+38), 2147483647(nan)339; CM-NEXT: SETGT_INT T2.X, PV.W, literal.x,340; CM-NEXT: SETGT_INT T2.Y, PV.Z, literal.x,341; CM-NEXT: AND_INT T2.Z, KC0[10].X, literal.y,342; CM-NEXT: AND_INT * T0.W, KC0[8].W, literal.y,343; CM-NEXT: 2139095039(3.402823e+38), 2147483647(nan)344; CM-NEXT: AND_INT T3.X, KC0[8].Y, literal.x,345; CM-NEXT: SETGT_INT T3.Y, PV.W, literal.y,346; CM-NEXT: SETGT_INT T2.Z, PV.Z, literal.y,347; CM-NEXT: AND_INT * T0.W, KC0[9].W, literal.x,348; CM-NEXT: 2147483647(nan), 2139095039(3.402823e+38)349; CM-NEXT: AND_INT T4.X, KC0[9].Z, literal.x,350; CM-NEXT: SETGT_INT T4.Y, PV.W, literal.y,351; CM-NEXT: AND_INT T3.Z, KC0[9].X, literal.x,352; CM-NEXT: CNDE_INT * T4.W, PV.Z, 1, 0.0,353; CM-NEXT: 2147483647(nan), 2139095039(3.402823e+38)354; CM-NEXT: SETGT_INT T5.X, PV.Z, literal.x,355; CM-NEXT: AND_INT T5.Y, KC0[9].Y, literal.y,356; CM-NEXT: CNDE_INT T4.Z, PV.Y, 1, 0.0,357; CM-NEXT: SETGT_INT * T0.W, PV.X, literal.x,358; CM-NEXT: 2139095039(3.402823e+38), 2147483647(nan)359; CM-NEXT: AND_INT T6.X, KC0[8].Z, literal.x,360; CM-NEXT: CNDE_INT T4.Y, PV.W, 1, 0.0,361; CM-NEXT: SETGT_INT T2.Z, PV.Y, literal.y,362; CM-NEXT: CNDE_INT * T3.W, PV.X, 1, 0.0,363; CM-NEXT: 2147483647(nan), 2139095039(3.402823e+38)364; CM-NEXT: CNDE_INT T4.X, PV.Z, 1, 0.0,365; CM-NEXT: SETGT_INT T5.Y, PV.X, literal.x,366; CM-NEXT: CNDE_INT T3.Z, T3.Y, 1, 0.0,367; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,368; CM-NEXT: 2139095039(3.402823e+38), 48(6.726233e-44)369; CM-NEXT: LSHR T5.X, PV.W, literal.x,370; CM-NEXT: CNDE_INT T3.Y, PV.Y, 1, 0.0,371; CM-NEXT: SETGT_INT T2.Z, T3.X, literal.y,372; CM-NEXT: CNDE_INT * T2.W, T2.Y, 1, 0.0,373; CM-NEXT: 2(2.802597e-45), 2139095039(3.402823e+38)374; CM-NEXT: CNDE_INT T3.X, PV.Z, 1, 0.0,375; CM-NEXT: SETGT_INT T1.Y, T1.Y, literal.x,376; CM-NEXT: CNDE_INT T2.Z, T2.X, 1, 0.0,377; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,378; CM-NEXT: 2139095039(3.402823e+38), 32(4.484155e-44)379; CM-NEXT: LSHR T6.X, PV.W, literal.x,380; CM-NEXT: CNDE_INT T2.Y, PV.Y, 1, 0.0,381; CM-NEXT: SETGT_INT T1.Z, T1.Z, literal.y,382; CM-NEXT: CNDE_INT * T1.W, T1.X, 1, 0.0,383; CM-NEXT: 2(2.802597e-45), 2139095039(3.402823e+38)384; CM-NEXT: CNDE_INT T2.X, PV.Z, 1, 0.0,385; CM-NEXT: SETGT_INT T0.Y, T0.Y, literal.x,386; CM-NEXT: CNDE_INT T1.Z, T0.X, 1, 0.0,387; CM-NEXT: ADD_INT * T0.W, KC0[2].Y, literal.y,388; CM-NEXT: 2139095039(3.402823e+38), 16(2.242078e-44)389; CM-NEXT: LSHR T0.X, PV.W, literal.x,390; CM-NEXT: CNDE_INT T1.Y, PV.Y, 1, 0.0,391; CM-NEXT: SETGT_INT * T0.W, T0.Z, literal.y,392; CM-NEXT: 2(2.802597e-45), 2139095039(3.402823e+38)393; CM-NEXT: CNDE_INT * T1.X, PV.W, 1, 0.0,394; CM-NEXT: LSHR * T7.X, KC0[2].Y, literal.x,395; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)396 %result = call <16 x i1> @llvm.is.fpclass.v3f32(<16 x float> %x, i32 504)397 %zext = zext <16 x i1> %result to <16 x i32>398 store <16 x i32> %zext, ptr addrspace(1) %out, align 64399 ret void400}401