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1; RUN: llc -amdgpu-scalarize-global-loads=false -mtriple=r600 -mcpu=redwood < %s | FileCheck -enable-var-scope -check-prefixes=EG,FUNC %s2 3declare i32 @llvm.r600.read.tidig.x() readnone4 5; FUNC-LABEL: {{^}}s_sub_i32:6define amdgpu_kernel void @s_sub_i32(ptr addrspace(1) %out, i32 %a, i32 %b) {7  %result = sub i32 %a, %b8  store i32 %result, ptr addrspace(1) %out9  ret void10}11 12; FUNC-LABEL: {{^}}s_sub_imm_i32:13define amdgpu_kernel void @s_sub_imm_i32(ptr addrspace(1) %out, i32 %a) {14  %result = sub i32 1234, %a15  store i32 %result, ptr addrspace(1) %out16  ret void17}18 19; FUNC-LABEL: {{^}}test_sub_i32:20; EG: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}21define amdgpu_kernel void @test_sub_i32(ptr addrspace(1) %out, ptr addrspace(1) %in) {22  %b_ptr = getelementptr i32, ptr addrspace(1) %in, i32 123  %a = load i32, ptr addrspace(1) %in24  %b = load i32, ptr addrspace(1) %b_ptr25  %result = sub i32 %a, %b26  store i32 %result, ptr addrspace(1) %out27  ret void28}29 30; FUNC-LABEL: {{^}}test_sub_imm_i32:31; EG: SUB_INT32define amdgpu_kernel void @test_sub_imm_i32(ptr addrspace(1) %out, ptr addrspace(1) %in) {33  %a = load i32, ptr addrspace(1) %in34  %result = sub i32 123, %a35  store i32 %result, ptr addrspace(1) %out36  ret void37}38 39; FUNC-LABEL: {{^}}test_sub_v2i32:40; EG: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}41; EG: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}42define amdgpu_kernel void @test_sub_v2i32(ptr addrspace(1) %out, ptr addrspace(1) %in) {43  %b_ptr = getelementptr <2 x i32>, ptr addrspace(1) %in, i32 144  %a = load <2 x i32>, ptr addrspace(1) %in45  %b = load <2 x i32>, ptr addrspace(1) %b_ptr46  %result = sub <2 x i32> %a, %b47  store <2 x i32> %result, ptr addrspace(1) %out48  ret void49}50 51; FUNC-LABEL: {{^}}test_sub_v4i32:52; EG: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}53; EG: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}54; EG: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}55; EG: SUB_INT {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}56define amdgpu_kernel void @test_sub_v4i32(ptr addrspace(1) %out, ptr addrspace(1) %in) {57  %b_ptr = getelementptr <4 x i32>, ptr addrspace(1) %in, i32 158  %a = load <4 x i32>, ptr addrspace(1) %in59  %b = load <4 x i32>, ptr addrspace(1) %b_ptr60  %result = sub <4 x i32> %a, %b61  store <4 x i32> %result, ptr addrspace(1) %out62  ret void63}64 65; FUNC-LABEL: {{^}}test_sub_i16:66define amdgpu_kernel void @test_sub_i16(ptr addrspace(1) %out, ptr addrspace(1) %in) {67  %tid = call i32 @llvm.r600.read.tidig.x()68  %gep = getelementptr i16, ptr addrspace(1) %in, i32 %tid69  %b_ptr = getelementptr i16, ptr addrspace(1) %gep, i32 170  %a = load volatile i16, ptr addrspace(1) %gep71  %b = load volatile i16, ptr addrspace(1) %b_ptr72  %result = sub i16 %a, %b73  store i16 %result, ptr addrspace(1) %out74  ret void75}76 77; FUNC-LABEL: {{^}}test_sub_v2i16:78define amdgpu_kernel void @test_sub_v2i16(ptr addrspace(1) %out, ptr addrspace(1) %in) {79  %tid = call i32 @llvm.r600.read.tidig.x()80  %gep = getelementptr <2 x i16>, ptr addrspace(1) %in, i32 %tid81  %b_ptr = getelementptr <2 x i16>, ptr addrspace(1) %gep, i16 182  %a = load <2 x i16>, ptr addrspace(1) %gep83  %b = load <2 x i16>, ptr addrspace(1) %b_ptr84  %result = sub <2 x i16> %a, %b85  store <2 x i16> %result, ptr addrspace(1) %out86  ret void87}88 89; FUNC-LABEL: {{^}}test_sub_v4i16:90define amdgpu_kernel void @test_sub_v4i16(ptr addrspace(1) %out, ptr addrspace(1) %in) {91  %tid = call i32 @llvm.r600.read.tidig.x()92  %gep = getelementptr <4 x i16>, ptr addrspace(1) %in, i32 %tid93  %b_ptr = getelementptr <4 x i16>, ptr addrspace(1) %gep, i16 194  %a = load <4 x i16>, ptr addrspace(1) %gep95  %b = load <4 x i16>, ptr addrspace(1) %b_ptr96  %result = sub <4 x i16> %a, %b97  store <4 x i16> %result, ptr addrspace(1) %out98  ret void99}100 101; FUNC-LABEL: {{^}}s_sub_i64:102; EG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XY103; EG-DAG: SUB_INT {{[* ]*}}104; EG-DAG: SUBB_UINT105; EG-DAG: SUB_INT106; EG-DAG: SUB_INT {{[* ]*}}107define amdgpu_kernel void @s_sub_i64(ptr addrspace(1) noalias %out, i64 %a, i64 %b) nounwind {108  %result = sub i64 %a, %b109  store i64 %result, ptr addrspace(1) %out, align 8110  ret void111}112 113; FUNC-LABEL: {{^}}v_sub_i64:114; EG: MEM_RAT_CACHELESS STORE_RAW T{{[0-9]+}}.XY115; EG-DAG: SUB_INT {{[* ]*}}116; EG-DAG: SUBB_UINT117; EG-DAG: SUB_INT118; EG-DAG: SUB_INT {{[* ]*}}119define amdgpu_kernel void @v_sub_i64(ptr addrspace(1) noalias %out, ptr addrspace(1) noalias %inA, ptr addrspace(1) noalias %inB) nounwind {120  %tid = call i32 @llvm.r600.read.tidig.x() readnone121  %a_ptr = getelementptr i64, ptr addrspace(1) %inA, i32 %tid122  %b_ptr = getelementptr i64, ptr addrspace(1) %inB, i32 %tid123  %a = load i64, ptr addrspace(1) %a_ptr124  %b = load i64, ptr addrspace(1) %b_ptr125  %result = sub i64 %a, %b126  store i64 %result, ptr addrspace(1) %out, align 8127  ret void128}129 130; FUNC-LABEL: {{^}}v_test_sub_v2i64:131define amdgpu_kernel void @v_test_sub_v2i64(ptr addrspace(1) %out, ptr addrspace(1) noalias %inA, ptr addrspace(1) noalias %inB) {132  %tid = call i32 @llvm.r600.read.tidig.x() readnone133  %a_ptr = getelementptr <2 x i64>, ptr addrspace(1) %inA, i32 %tid134  %b_ptr = getelementptr <2 x i64>, ptr addrspace(1) %inB, i32 %tid135  %a = load <2 x i64>, ptr addrspace(1) %a_ptr136  %b = load <2 x i64>, ptr addrspace(1) %b_ptr137  %result = sub <2 x i64> %a, %b138  store <2 x i64> %result, ptr addrspace(1) %out139  ret void140}141 142; FUNC-LABEL: {{^}}v_test_sub_v4i64:143define amdgpu_kernel void @v_test_sub_v4i64(ptr addrspace(1) %out, ptr addrspace(1) noalias %inA, ptr addrspace(1) noalias %inB) {144  %tid = call i32 @llvm.r600.read.tidig.x() readnone145  %a_ptr = getelementptr <4 x i64>, ptr addrspace(1) %inA, i32 %tid146  %b_ptr = getelementptr <4 x i64>, ptr addrspace(1) %inB, i32 %tid147  %a = load <4 x i64>, ptr addrspace(1) %a_ptr148  %b = load <4 x i64>, ptr addrspace(1) %b_ptr149  %result = sub <4 x i64> %a, %b150  store <4 x i64> %result, ptr addrspace(1) %out151  ret void152}153