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1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 22; RUN: llc -mtriple=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,SI %s3; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GCN,VI %s4; RUN: llc -mtriple=r600 -mcpu=cypress < %s | FileCheck -check-prefixes=R600,EG %s5; RUN: llc -mtriple=r600 -mcpu=cayman < %s | FileCheck -check-prefixes=R600,CM %s6 7define float @v_rcp_f32_ieee(float %x) #3 {8; SI-LABEL: v_rcp_f32_ieee:9; SI: ; %bb.0:10; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)11; SI-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.012; SI-NEXT: v_rcp_f32_e32 v2, v113; SI-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.014; SI-NEXT: v_fma_f32 v4, -v1, v2, 1.015; SI-NEXT: v_fma_f32 v2, v4, v2, v216; SI-NEXT: v_mul_f32_e32 v4, v3, v217; SI-NEXT: v_fma_f32 v5, -v1, v4, v318; SI-NEXT: v_fma_f32 v4, v5, v2, v419; SI-NEXT: v_fma_f32 v1, -v1, v4, v320; SI-NEXT: v_div_fmas_f32 v1, v1, v2, v421; SI-NEXT: v_div_fixup_f32 v0, v1, v0, 1.022; SI-NEXT: s_setpc_b64 s[30:31]23;24; VI-LABEL: v_rcp_f32_ieee:25; VI: ; %bb.0:26; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)27; VI-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.028; VI-NEXT: v_div_scale_f32 v2, vcc, 1.0, v0, 1.029; VI-NEXT: v_rcp_f32_e32 v3, v130; VI-NEXT: v_fma_f32 v4, -v1, v3, 1.031; VI-NEXT: v_fma_f32 v3, v4, v3, v332; VI-NEXT: v_mul_f32_e32 v4, v2, v333; VI-NEXT: v_fma_f32 v5, -v1, v4, v234; VI-NEXT: v_fma_f32 v4, v5, v3, v435; VI-NEXT: v_fma_f32 v1, -v1, v4, v236; VI-NEXT: v_div_fmas_f32 v1, v1, v3, v437; VI-NEXT: v_div_fixup_f32 v0, v1, v0, 1.038; VI-NEXT: s_setpc_b64 s[30:31]39;40; R600-LABEL: v_rcp_f32_ieee:41; R600: ; %bb.0:42; R600-NEXT: CF_END43; R600-NEXT: PAD44 %rcp = fdiv float 1.0, %x45 ret float %rcp46}47 48define float @v_rcp_f32_ieee_unsafe(float %x) #4 {49; GCN-LABEL: v_rcp_f32_ieee_unsafe:50; GCN: ; %bb.0:51; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)52; GCN-NEXT: v_rcp_f32_e32 v0, v053; GCN-NEXT: s_setpc_b64 s[30:31]54;55; R600-LABEL: v_rcp_f32_ieee_unsafe:56; R600: ; %bb.0:57; R600-NEXT: CF_END58; R600-NEXT: PAD59 %rcp = fdiv afn float 1.0, %x60 ret float %rcp61}62 63define float @v_rcp_f32_ieee_known_not_denormal(float nofpclass(sub) %x) #3 {64; SI-LABEL: v_rcp_f32_ieee_known_not_denormal:65; SI: ; %bb.0:66; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)67; SI-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.068; SI-NEXT: v_rcp_f32_e32 v2, v169; SI-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.070; SI-NEXT: v_fma_f32 v4, -v1, v2, 1.071; SI-NEXT: v_fma_f32 v2, v4, v2, v272; SI-NEXT: v_mul_f32_e32 v4, v3, v273; SI-NEXT: v_fma_f32 v5, -v1, v4, v374; SI-NEXT: v_fma_f32 v4, v5, v2, v475; SI-NEXT: v_fma_f32 v1, -v1, v4, v376; SI-NEXT: v_div_fmas_f32 v1, v1, v2, v477; SI-NEXT: v_div_fixup_f32 v0, v1, v0, 1.078; SI-NEXT: s_setpc_b64 s[30:31]79;80; VI-LABEL: v_rcp_f32_ieee_known_not_denormal:81; VI: ; %bb.0:82; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)83; VI-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.084; VI-NEXT: v_div_scale_f32 v2, vcc, 1.0, v0, 1.085; VI-NEXT: v_rcp_f32_e32 v3, v186; VI-NEXT: v_fma_f32 v4, -v1, v3, 1.087; VI-NEXT: v_fma_f32 v3, v4, v3, v388; VI-NEXT: v_mul_f32_e32 v4, v2, v389; VI-NEXT: v_fma_f32 v5, -v1, v4, v290; VI-NEXT: v_fma_f32 v4, v5, v3, v491; VI-NEXT: v_fma_f32 v1, -v1, v4, v292; VI-NEXT: v_div_fmas_f32 v1, v1, v3, v493; VI-NEXT: v_div_fixup_f32 v0, v1, v0, 1.094; VI-NEXT: s_setpc_b64 s[30:31]95;96; R600-LABEL: v_rcp_f32_ieee_known_not_denormal:97; R600: ; %bb.0:98; R600-NEXT: CF_END99; R600-NEXT: PAD100 %rcp = fdiv float 1.0, %x101 ret float %rcp102}103 104define float @v_rcp_f32_ieee_nnan_ninf(float %x) #3 {105; SI-LABEL: v_rcp_f32_ieee_nnan_ninf:106; SI: ; %bb.0:107; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)108; SI-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0109; SI-NEXT: v_rcp_f32_e32 v2, v1110; SI-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0111; SI-NEXT: v_fma_f32 v4, -v1, v2, 1.0112; SI-NEXT: v_fma_f32 v2, v4, v2, v2113; SI-NEXT: v_mul_f32_e32 v4, v3, v2114; SI-NEXT: v_fma_f32 v5, -v1, v4, v3115; SI-NEXT: v_fma_f32 v4, v5, v2, v4116; SI-NEXT: v_fma_f32 v1, -v1, v4, v3117; SI-NEXT: v_div_fmas_f32 v1, v1, v2, v4118; SI-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0119; SI-NEXT: s_setpc_b64 s[30:31]120;121; VI-LABEL: v_rcp_f32_ieee_nnan_ninf:122; VI: ; %bb.0:123; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)124; VI-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0125; VI-NEXT: v_div_scale_f32 v2, vcc, 1.0, v0, 1.0126; VI-NEXT: v_rcp_f32_e32 v3, v1127; VI-NEXT: v_fma_f32 v4, -v1, v3, 1.0128; VI-NEXT: v_fma_f32 v3, v4, v3, v3129; VI-NEXT: v_mul_f32_e32 v4, v2, v3130; VI-NEXT: v_fma_f32 v5, -v1, v4, v2131; VI-NEXT: v_fma_f32 v4, v5, v3, v4132; VI-NEXT: v_fma_f32 v1, -v1, v4, v2133; VI-NEXT: v_div_fmas_f32 v1, v1, v3, v4134; VI-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0135; VI-NEXT: s_setpc_b64 s[30:31]136;137; R600-LABEL: v_rcp_f32_ieee_nnan_ninf:138; R600: ; %bb.0:139; R600-NEXT: CF_END140; R600-NEXT: PAD141 %rcp = fdiv nnan ninf float 1.0, %x142 ret float %rcp143}144 145define float @v_neg_rcp_f32_ieee(float %x) #3 {146; SI-LABEL: v_neg_rcp_f32_ieee:147; SI: ; %bb.0:148; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)149; SI-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, -1.0150; SI-NEXT: v_rcp_f32_e32 v2, v1151; SI-NEXT: v_div_scale_f32 v3, vcc, -1.0, v0, -1.0152; SI-NEXT: v_fma_f32 v4, -v1, v2, 1.0153; SI-NEXT: v_fma_f32 v2, v4, v2, v2154; SI-NEXT: v_mul_f32_e32 v4, v3, v2155; SI-NEXT: v_fma_f32 v5, -v1, v4, v3156; SI-NEXT: v_fma_f32 v4, v5, v2, v4157; SI-NEXT: v_fma_f32 v1, -v1, v4, v3158; SI-NEXT: v_div_fmas_f32 v1, v1, v2, v4159; SI-NEXT: v_div_fixup_f32 v0, v1, v0, -1.0160; SI-NEXT: s_setpc_b64 s[30:31]161;162; VI-LABEL: v_neg_rcp_f32_ieee:163; VI: ; %bb.0:164; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)165; VI-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, -1.0166; VI-NEXT: v_div_scale_f32 v2, vcc, -1.0, v0, -1.0167; VI-NEXT: v_rcp_f32_e32 v3, v1168; VI-NEXT: v_fma_f32 v4, -v1, v3, 1.0169; VI-NEXT: v_fma_f32 v3, v4, v3, v3170; VI-NEXT: v_mul_f32_e32 v4, v2, v3171; VI-NEXT: v_fma_f32 v5, -v1, v4, v2172; VI-NEXT: v_fma_f32 v4, v5, v3, v4173; VI-NEXT: v_fma_f32 v1, -v1, v4, v2174; VI-NEXT: v_div_fmas_f32 v1, v1, v3, v4175; VI-NEXT: v_div_fixup_f32 v0, v1, v0, -1.0176; VI-NEXT: s_setpc_b64 s[30:31]177;178; R600-LABEL: v_neg_rcp_f32_ieee:179; R600: ; %bb.0:180; R600-NEXT: CF_END181; R600-NEXT: PAD182 %rcp = fdiv float -1.0, %x183 ret float %rcp184}185 186define float @v_rcp_f32_daz(float %x) #0 {187; SI-LABEL: v_rcp_f32_daz:188; SI: ; %bb.0:189; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)190; SI-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0191; SI-NEXT: v_rcp_f32_e32 v2, v1192; SI-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0193; SI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3194; SI-NEXT: v_fma_f32 v4, -v1, v2, 1.0195; SI-NEXT: v_fma_f32 v2, v4, v2, v2196; SI-NEXT: v_mul_f32_e32 v4, v3, v2197; SI-NEXT: v_fma_f32 v5, -v1, v4, v3198; SI-NEXT: v_fma_f32 v4, v5, v2, v4199; SI-NEXT: v_fma_f32 v1, -v1, v4, v3200; SI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0201; SI-NEXT: v_div_fmas_f32 v1, v1, v2, v4202; SI-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0203; SI-NEXT: s_setpc_b64 s[30:31]204;205; VI-LABEL: v_rcp_f32_daz:206; VI: ; %bb.0:207; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)208; VI-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0209; VI-NEXT: v_div_scale_f32 v2, vcc, 1.0, v0, 1.0210; VI-NEXT: v_rcp_f32_e32 v3, v1211; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3212; VI-NEXT: v_fma_f32 v4, -v1, v3, 1.0213; VI-NEXT: v_fma_f32 v3, v4, v3, v3214; VI-NEXT: v_mul_f32_e32 v4, v2, v3215; VI-NEXT: v_fma_f32 v5, -v1, v4, v2216; VI-NEXT: v_fma_f32 v4, v5, v3, v4217; VI-NEXT: v_fma_f32 v1, -v1, v4, v2218; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0219; VI-NEXT: v_div_fmas_f32 v1, v1, v3, v4220; VI-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0221; VI-NEXT: s_setpc_b64 s[30:31]222;223; R600-LABEL: v_rcp_f32_daz:224; R600: ; %bb.0:225; R600-NEXT: CF_END226; R600-NEXT: PAD227 %rcp = fdiv float 1.0, %x228 ret float %rcp229}230 231define float @v_neg_rcp_f32_daz(float %x) #0 {232; SI-LABEL: v_neg_rcp_f32_daz:233; SI: ; %bb.0:234; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)235; SI-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, -1.0236; SI-NEXT: v_rcp_f32_e32 v2, v1237; SI-NEXT: v_div_scale_f32 v3, vcc, -1.0, v0, -1.0238; SI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3239; SI-NEXT: v_fma_f32 v4, -v1, v2, 1.0240; SI-NEXT: v_fma_f32 v2, v4, v2, v2241; SI-NEXT: v_mul_f32_e32 v4, v3, v2242; SI-NEXT: v_fma_f32 v5, -v1, v4, v3243; SI-NEXT: v_fma_f32 v4, v5, v2, v4244; SI-NEXT: v_fma_f32 v1, -v1, v4, v3245; SI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0246; SI-NEXT: v_div_fmas_f32 v1, v1, v2, v4247; SI-NEXT: v_div_fixup_f32 v0, v1, v0, -1.0248; SI-NEXT: s_setpc_b64 s[30:31]249;250; VI-LABEL: v_neg_rcp_f32_daz:251; VI: ; %bb.0:252; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)253; VI-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, -1.0254; VI-NEXT: v_div_scale_f32 v2, vcc, -1.0, v0, -1.0255; VI-NEXT: v_rcp_f32_e32 v3, v1256; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3257; VI-NEXT: v_fma_f32 v4, -v1, v3, 1.0258; VI-NEXT: v_fma_f32 v3, v4, v3, v3259; VI-NEXT: v_mul_f32_e32 v4, v2, v3260; VI-NEXT: v_fma_f32 v5, -v1, v4, v2261; VI-NEXT: v_fma_f32 v4, v5, v3, v4262; VI-NEXT: v_fma_f32 v1, -v1, v4, v2263; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0264; VI-NEXT: v_div_fmas_f32 v1, v1, v3, v4265; VI-NEXT: v_div_fixup_f32 v0, v1, v0, -1.0266; VI-NEXT: s_setpc_b64 s[30:31]267;268; R600-LABEL: v_neg_rcp_f32_daz:269; R600: ; %bb.0:270; R600-NEXT: CF_END271; R600-NEXT: PAD272 %rcp = fdiv float -1.0, %x273 ret float %rcp274}275 276define float @v_rcp_f32_ieee_ulp25(float %x) #3 {277; SI-LABEL: v_rcp_f32_ieee_ulp25:278; SI: ; %bb.0:279; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)280; SI-NEXT: s_mov_b32 s4, 0x7f800000281; SI-NEXT: v_frexp_mant_f32_e32 v1, v0282; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4283; SI-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc284; SI-NEXT: v_rcp_f32_e32 v1, v1285; SI-NEXT: v_frexp_exp_i32_f32_e32 v0, v0286; SI-NEXT: v_sub_i32_e32 v0, vcc, 0, v0287; SI-NEXT: v_ldexp_f32_e32 v0, v1, v0288; SI-NEXT: s_setpc_b64 s[30:31]289;290; VI-LABEL: v_rcp_f32_ieee_ulp25:291; VI: ; %bb.0:292; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)293; VI-NEXT: v_frexp_mant_f32_e32 v1, v0294; VI-NEXT: v_rcp_f32_e32 v1, v1295; VI-NEXT: v_frexp_exp_i32_f32_e32 v0, v0296; VI-NEXT: v_sub_u32_e32 v0, vcc, 0, v0297; VI-NEXT: v_ldexp_f32 v0, v1, v0298; VI-NEXT: s_setpc_b64 s[30:31]299;300; R600-LABEL: v_rcp_f32_ieee_ulp25:301; R600: ; %bb.0:302; R600-NEXT: CF_END303; R600-NEXT: PAD304 %rcp = fdiv float 1.0, %x, !fpmath !0305 ret float %rcp306}307 308define float @v_rcp_f32_ieee_ulp25_known_not_denormal(float nofpclass(sub) %x) #3 {309; SI-LABEL: v_rcp_f32_ieee_ulp25_known_not_denormal:310; SI: ; %bb.0:311; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)312; SI-NEXT: s_mov_b32 s4, 0x7f800000313; SI-NEXT: v_frexp_mant_f32_e32 v1, v0314; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4315; SI-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc316; SI-NEXT: v_rcp_f32_e32 v1, v1317; SI-NEXT: v_frexp_exp_i32_f32_e32 v0, v0318; SI-NEXT: v_sub_i32_e32 v0, vcc, 0, v0319; SI-NEXT: v_ldexp_f32_e32 v0, v1, v0320; SI-NEXT: s_setpc_b64 s[30:31]321;322; VI-LABEL: v_rcp_f32_ieee_ulp25_known_not_denormal:323; VI: ; %bb.0:324; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)325; VI-NEXT: v_frexp_mant_f32_e32 v1, v0326; VI-NEXT: v_rcp_f32_e32 v1, v1327; VI-NEXT: v_frexp_exp_i32_f32_e32 v0, v0328; VI-NEXT: v_sub_u32_e32 v0, vcc, 0, v0329; VI-NEXT: v_ldexp_f32 v0, v1, v0330; VI-NEXT: s_setpc_b64 s[30:31]331;332; R600-LABEL: v_rcp_f32_ieee_ulp25_known_not_denormal:333; R600: ; %bb.0:334; R600-NEXT: CF_END335; R600-NEXT: PAD336 %rcp = fdiv float 1.0, %x, !fpmath !0337 ret float %rcp338}339 340define float @v_neg_rcp_f32_ieee_ulp25_known_not_denormal(float nofpclass(sub) %x) #3 {341; SI-LABEL: v_neg_rcp_f32_ieee_ulp25_known_not_denormal:342; SI: ; %bb.0:343; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)344; SI-NEXT: s_mov_b32 s4, 0x7f800000345; SI-NEXT: v_frexp_mant_f32_e64 v1, -v0346; SI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4347; SI-NEXT: v_cndmask_b32_e64 v1, -v0, v1, s[4:5]348; SI-NEXT: v_rcp_f32_e32 v1, v1349; SI-NEXT: v_frexp_exp_i32_f32_e32 v0, v0350; SI-NEXT: v_sub_i32_e32 v0, vcc, 0, v0351; SI-NEXT: v_ldexp_f32_e32 v0, v1, v0352; SI-NEXT: s_setpc_b64 s[30:31]353;354; VI-LABEL: v_neg_rcp_f32_ieee_ulp25_known_not_denormal:355; VI: ; %bb.0:356; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)357; VI-NEXT: v_frexp_mant_f32_e64 v1, -v0358; VI-NEXT: v_rcp_f32_e32 v1, v1359; VI-NEXT: v_frexp_exp_i32_f32_e32 v0, v0360; VI-NEXT: v_sub_u32_e32 v0, vcc, 0, v0361; VI-NEXT: v_ldexp_f32 v0, v1, v0362; VI-NEXT: s_setpc_b64 s[30:31]363;364; R600-LABEL: v_neg_rcp_f32_ieee_ulp25_known_not_denormal:365; R600: ; %bb.0:366; R600-NEXT: CF_END367; R600-NEXT: PAD368 %rcp = fdiv float -1.0, %x, !fpmath !0369 ret float %rcp370}371 372define float @v_rcp_f32_ieee_ulp25_ninf_nnan(float %x) #3 {373; SI-LABEL: v_rcp_f32_ieee_ulp25_ninf_nnan:374; SI: ; %bb.0:375; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)376; SI-NEXT: s_mov_b32 s4, 0x7f800000377; SI-NEXT: v_frexp_mant_f32_e32 v1, v0378; SI-NEXT: v_cmp_lt_f32_e64 vcc, |v0|, s4379; SI-NEXT: v_cndmask_b32_e32 v1, v0, v1, vcc380; SI-NEXT: v_rcp_f32_e32 v1, v1381; SI-NEXT: v_frexp_exp_i32_f32_e32 v0, v0382; SI-NEXT: v_sub_i32_e32 v0, vcc, 0, v0383; SI-NEXT: v_ldexp_f32_e32 v0, v1, v0384; SI-NEXT: s_setpc_b64 s[30:31]385;386; VI-LABEL: v_rcp_f32_ieee_ulp25_ninf_nnan:387; VI: ; %bb.0:388; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)389; VI-NEXT: v_frexp_mant_f32_e32 v1, v0390; VI-NEXT: v_rcp_f32_e32 v1, v1391; VI-NEXT: v_frexp_exp_i32_f32_e32 v0, v0392; VI-NEXT: v_sub_u32_e32 v0, vcc, 0, v0393; VI-NEXT: v_ldexp_f32 v0, v1, v0394; VI-NEXT: s_setpc_b64 s[30:31]395;396; R600-LABEL: v_rcp_f32_ieee_ulp25_ninf_nnan:397; R600: ; %bb.0:398; R600-NEXT: CF_END399; R600-NEXT: PAD400 %rcp = fdiv ninf nnan float 1.0, %x, !fpmath !0401 ret float %rcp402}403 404define float @v_rcp_f32_daz_ulp25(float %x) #0 {405; GCN-LABEL: v_rcp_f32_daz_ulp25:406; GCN: ; %bb.0:407; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)408; GCN-NEXT: v_rcp_f32_e32 v0, v0409; GCN-NEXT: s_setpc_b64 s[30:31]410;411; R600-LABEL: v_rcp_f32_daz_ulp25:412; R600: ; %bb.0:413; R600-NEXT: CF_END414; R600-NEXT: PAD415 %rcp = fdiv float 1.0, %x, !fpmath !0416 ret float %rcp417}418 419define float @v_neg_rcp_f32_ieee_ulp25(float %x) #3 {420; SI-LABEL: v_neg_rcp_f32_ieee_ulp25:421; SI: ; %bb.0:422; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)423; SI-NEXT: s_mov_b32 s4, 0x7f800000424; SI-NEXT: v_frexp_mant_f32_e64 v1, -v0425; SI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4426; SI-NEXT: v_cndmask_b32_e64 v1, -v0, v1, s[4:5]427; SI-NEXT: v_rcp_f32_e32 v1, v1428; SI-NEXT: v_frexp_exp_i32_f32_e32 v0, v0429; SI-NEXT: v_sub_i32_e32 v0, vcc, 0, v0430; SI-NEXT: v_ldexp_f32_e32 v0, v1, v0431; SI-NEXT: s_setpc_b64 s[30:31]432;433; VI-LABEL: v_neg_rcp_f32_ieee_ulp25:434; VI: ; %bb.0:435; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)436; VI-NEXT: v_frexp_mant_f32_e64 v1, -v0437; VI-NEXT: v_rcp_f32_e32 v1, v1438; VI-NEXT: v_frexp_exp_i32_f32_e32 v0, v0439; VI-NEXT: v_sub_u32_e32 v0, vcc, 0, v0440; VI-NEXT: v_ldexp_f32 v0, v1, v0441; VI-NEXT: s_setpc_b64 s[30:31]442;443; R600-LABEL: v_neg_rcp_f32_ieee_ulp25:444; R600: ; %bb.0:445; R600-NEXT: CF_END446; R600-NEXT: PAD447 %rcp = fdiv float -1.0, %x, !fpmath !0448 ret float %rcp449}450 451define float @v_neg_rcp_f32_daz_ulp25(float %x) #0 {452; GCN-LABEL: v_neg_rcp_f32_daz_ulp25:453; GCN: ; %bb.0:454; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)455; GCN-NEXT: v_rcp_f32_e64 v0, -v0456; GCN-NEXT: s_setpc_b64 s[30:31]457;458; R600-LABEL: v_neg_rcp_f32_daz_ulp25:459; R600: ; %bb.0:460; R600-NEXT: CF_END461; R600-NEXT: PAD462 %rcp = fdiv float -1.0, %x, !fpmath !0463 ret float %rcp464}465 466define float @v_rcp_fabs_f32_ieee(float %x) #3 {467; SI-LABEL: v_rcp_fabs_f32_ieee:468; SI: ; %bb.0:469; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)470; SI-NEXT: v_and_b32_e32 v1, 0x7fffffff, v0471; SI-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, 1.0472; SI-NEXT: v_rcp_f32_e32 v3, v2473; SI-NEXT: v_div_scale_f32 v1, vcc, 1.0, v1, 1.0474; SI-NEXT: v_fma_f32 v4, -v2, v3, 1.0475; SI-NEXT: v_fma_f32 v3, v4, v3, v3476; SI-NEXT: v_mul_f32_e32 v4, v1, v3477; SI-NEXT: v_fma_f32 v5, -v2, v4, v1478; SI-NEXT: v_fma_f32 v4, v5, v3, v4479; SI-NEXT: v_fma_f32 v1, -v2, v4, v1480; SI-NEXT: v_div_fmas_f32 v1, v1, v3, v4481; SI-NEXT: v_div_fixup_f32 v0, v1, |v0|, 1.0482; SI-NEXT: s_setpc_b64 s[30:31]483;484; VI-LABEL: v_rcp_fabs_f32_ieee:485; VI: ; %bb.0:486; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)487; VI-NEXT: v_and_b32_e32 v1, 0x7fffffff, v0488; VI-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, 1.0489; VI-NEXT: v_div_scale_f32 v1, vcc, 1.0, v1, 1.0490; VI-NEXT: v_rcp_f32_e32 v3, v2491; VI-NEXT: v_fma_f32 v4, -v2, v3, 1.0492; VI-NEXT: v_fma_f32 v3, v4, v3, v3493; VI-NEXT: v_mul_f32_e32 v4, v1, v3494; VI-NEXT: v_fma_f32 v5, -v2, v4, v1495; VI-NEXT: v_fma_f32 v4, v5, v3, v4496; VI-NEXT: v_fma_f32 v1, -v2, v4, v1497; VI-NEXT: v_div_fmas_f32 v1, v1, v3, v4498; VI-NEXT: v_div_fixup_f32 v0, v1, |v0|, 1.0499; VI-NEXT: s_setpc_b64 s[30:31]500;501; R600-LABEL: v_rcp_fabs_f32_ieee:502; R600: ; %bb.0:503; R600-NEXT: CF_END504; R600-NEXT: PAD505 %fabs.x = call float @llvm.fabs.f32(float %x)506 %rcp = fdiv float 1.0, %fabs.x507 ret float %rcp508}509 510define float @v_rcp_fabs_f32_daz(float %x) #0 {511; SI-LABEL: v_rcp_fabs_f32_daz:512; SI: ; %bb.0:513; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)514; SI-NEXT: v_and_b32_e32 v1, 0x7fffffff, v0515; SI-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, 1.0516; SI-NEXT: v_rcp_f32_e32 v3, v2517; SI-NEXT: v_div_scale_f32 v1, vcc, 1.0, v1, 1.0518; SI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3519; SI-NEXT: v_fma_f32 v4, -v2, v3, 1.0520; SI-NEXT: v_fma_f32 v3, v4, v3, v3521; SI-NEXT: v_mul_f32_e32 v4, v1, v3522; SI-NEXT: v_fma_f32 v5, -v2, v4, v1523; SI-NEXT: v_fma_f32 v4, v5, v3, v4524; SI-NEXT: v_fma_f32 v1, -v2, v4, v1525; SI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0526; SI-NEXT: v_div_fmas_f32 v1, v1, v3, v4527; SI-NEXT: v_div_fixup_f32 v0, v1, |v0|, 1.0528; SI-NEXT: s_setpc_b64 s[30:31]529;530; VI-LABEL: v_rcp_fabs_f32_daz:531; VI: ; %bb.0:532; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)533; VI-NEXT: v_and_b32_e32 v1, 0x7fffffff, v0534; VI-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, 1.0535; VI-NEXT: v_div_scale_f32 v1, vcc, 1.0, v1, 1.0536; VI-NEXT: v_rcp_f32_e32 v3, v2537; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3538; VI-NEXT: v_fma_f32 v4, -v2, v3, 1.0539; VI-NEXT: v_fma_f32 v3, v4, v3, v3540; VI-NEXT: v_mul_f32_e32 v4, v1, v3541; VI-NEXT: v_fma_f32 v5, -v2, v4, v1542; VI-NEXT: v_fma_f32 v4, v5, v3, v4543; VI-NEXT: v_fma_f32 v1, -v2, v4, v1544; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0545; VI-NEXT: v_div_fmas_f32 v1, v1, v3, v4546; VI-NEXT: v_div_fixup_f32 v0, v1, |v0|, 1.0547; VI-NEXT: s_setpc_b64 s[30:31]548;549; R600-LABEL: v_rcp_fabs_f32_daz:550; R600: ; %bb.0:551; R600-NEXT: CF_END552; R600-NEXT: PAD553 %fabs.x = call float @llvm.fabs.f32(float %x)554 %rcp = fdiv float 1.0, %fabs.x555 ret float %rcp556}557 558define float @v_rcp_fabs_f32_ieee_ulp25(float %x) #3 {559; SI-LABEL: v_rcp_fabs_f32_ieee_ulp25:560; SI: ; %bb.0:561; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)562; SI-NEXT: s_mov_b32 s4, 0x7f800000563; SI-NEXT: v_frexp_mant_f32_e64 v1, |v0|564; SI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4565; SI-NEXT: v_cndmask_b32_e64 v1, |v0|, v1, s[4:5]566; SI-NEXT: v_rcp_f32_e32 v1, v1567; SI-NEXT: v_frexp_exp_i32_f32_e32 v0, v0568; SI-NEXT: v_sub_i32_e32 v0, vcc, 0, v0569; SI-NEXT: v_ldexp_f32_e32 v0, v1, v0570; SI-NEXT: s_setpc_b64 s[30:31]571;572; VI-LABEL: v_rcp_fabs_f32_ieee_ulp25:573; VI: ; %bb.0:574; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)575; VI-NEXT: v_frexp_mant_f32_e64 v1, |v0|576; VI-NEXT: v_rcp_f32_e32 v1, v1577; VI-NEXT: v_frexp_exp_i32_f32_e32 v0, v0578; VI-NEXT: v_sub_u32_e32 v0, vcc, 0, v0579; VI-NEXT: v_ldexp_f32 v0, v1, v0580; VI-NEXT: s_setpc_b64 s[30:31]581;582; R600-LABEL: v_rcp_fabs_f32_ieee_ulp25:583; R600: ; %bb.0:584; R600-NEXT: CF_END585; R600-NEXT: PAD586 %fabs.x = call float @llvm.fabs.f32(float %x)587 %rcp = fdiv float 1.0, %fabs.x, !fpmath !0588 ret float %rcp589}590 591define float @v_rcp_fabs_f32_daz_ulp25(float %x) #0 {592; GCN-LABEL: v_rcp_fabs_f32_daz_ulp25:593; GCN: ; %bb.0:594; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)595; GCN-NEXT: v_rcp_f32_e64 v0, |v0|596; GCN-NEXT: s_setpc_b64 s[30:31]597;598; R600-LABEL: v_rcp_fabs_f32_daz_ulp25:599; R600: ; %bb.0:600; R600-NEXT: CF_END601; R600-NEXT: PAD602 %fabs.x = call float @llvm.fabs.f32(float %x)603 %rcp = fdiv float 1.0, %fabs.x, !fpmath !0604 ret float %rcp605}606 607define float @v_rcp_neg_fabs_f32_ieee(float %x) #3 {608; SI-LABEL: v_rcp_neg_fabs_f32_ieee:609; SI: ; %bb.0:610; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)611; SI-NEXT: v_and_b32_e32 v1, 0x7fffffff, v0612; SI-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, -1.0613; SI-NEXT: v_rcp_f32_e32 v3, v2614; SI-NEXT: v_div_scale_f32 v1, vcc, -1.0, v1, -1.0615; SI-NEXT: v_fma_f32 v4, -v2, v3, 1.0616; SI-NEXT: v_fma_f32 v3, v4, v3, v3617; SI-NEXT: v_mul_f32_e32 v4, v1, v3618; SI-NEXT: v_fma_f32 v5, -v2, v4, v1619; SI-NEXT: v_fma_f32 v4, v5, v3, v4620; SI-NEXT: v_fma_f32 v1, -v2, v4, v1621; SI-NEXT: v_div_fmas_f32 v1, v1, v3, v4622; SI-NEXT: v_div_fixup_f32 v0, v1, |v0|, -1.0623; SI-NEXT: s_setpc_b64 s[30:31]624;625; VI-LABEL: v_rcp_neg_fabs_f32_ieee:626; VI: ; %bb.0:627; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)628; VI-NEXT: v_and_b32_e32 v1, 0x7fffffff, v0629; VI-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, -1.0630; VI-NEXT: v_div_scale_f32 v1, vcc, -1.0, v1, -1.0631; VI-NEXT: v_rcp_f32_e32 v3, v2632; VI-NEXT: v_fma_f32 v4, -v2, v3, 1.0633; VI-NEXT: v_fma_f32 v3, v4, v3, v3634; VI-NEXT: v_mul_f32_e32 v4, v1, v3635; VI-NEXT: v_fma_f32 v5, -v2, v4, v1636; VI-NEXT: v_fma_f32 v4, v5, v3, v4637; VI-NEXT: v_fma_f32 v1, -v2, v4, v1638; VI-NEXT: v_div_fmas_f32 v1, v1, v3, v4639; VI-NEXT: v_div_fixup_f32 v0, v1, |v0|, -1.0640; VI-NEXT: s_setpc_b64 s[30:31]641;642; R600-LABEL: v_rcp_neg_fabs_f32_ieee:643; R600: ; %bb.0:644; R600-NEXT: CF_END645; R600-NEXT: PAD646 %fabs.x = call float @llvm.fabs.f32(float %x)647 %rcp = fdiv float -1.0, %fabs.x648 ret float %rcp649}650 651define float @v_rcp_neg_fabs_f32_daz(float %x) #0 {652; SI-LABEL: v_rcp_neg_fabs_f32_daz:653; SI: ; %bb.0:654; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)655; SI-NEXT: v_and_b32_e32 v1, 0x7fffffff, v0656; SI-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, -1.0657; SI-NEXT: v_rcp_f32_e32 v3, v2658; SI-NEXT: v_div_scale_f32 v1, vcc, -1.0, v1, -1.0659; SI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3660; SI-NEXT: v_fma_f32 v4, -v2, v3, 1.0661; SI-NEXT: v_fma_f32 v3, v4, v3, v3662; SI-NEXT: v_mul_f32_e32 v4, v1, v3663; SI-NEXT: v_fma_f32 v5, -v2, v4, v1664; SI-NEXT: v_fma_f32 v4, v5, v3, v4665; SI-NEXT: v_fma_f32 v1, -v2, v4, v1666; SI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0667; SI-NEXT: v_div_fmas_f32 v1, v1, v3, v4668; SI-NEXT: v_div_fixup_f32 v0, v1, |v0|, -1.0669; SI-NEXT: s_setpc_b64 s[30:31]670;671; VI-LABEL: v_rcp_neg_fabs_f32_daz:672; VI: ; %bb.0:673; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)674; VI-NEXT: v_and_b32_e32 v1, 0x7fffffff, v0675; VI-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, -1.0676; VI-NEXT: v_div_scale_f32 v1, vcc, -1.0, v1, -1.0677; VI-NEXT: v_rcp_f32_e32 v3, v2678; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3679; VI-NEXT: v_fma_f32 v4, -v2, v3, 1.0680; VI-NEXT: v_fma_f32 v3, v4, v3, v3681; VI-NEXT: v_mul_f32_e32 v4, v1, v3682; VI-NEXT: v_fma_f32 v5, -v2, v4, v1683; VI-NEXT: v_fma_f32 v4, v5, v3, v4684; VI-NEXT: v_fma_f32 v1, -v2, v4, v1685; VI-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0686; VI-NEXT: v_div_fmas_f32 v1, v1, v3, v4687; VI-NEXT: v_div_fixup_f32 v0, v1, |v0|, -1.0688; VI-NEXT: s_setpc_b64 s[30:31]689;690; R600-LABEL: v_rcp_neg_fabs_f32_daz:691; R600: ; %bb.0:692; R600-NEXT: CF_END693; R600-NEXT: PAD694 %fabs.x = call float @llvm.fabs.f32(float %x)695 %rcp = fdiv float -1.0, %fabs.x696 ret float %rcp697}698 699define float @v_rcp_neg_fabs_f32_ieee_ulp25(float %x) #3 {700; SI-LABEL: v_rcp_neg_fabs_f32_ieee_ulp25:701; SI: ; %bb.0:702; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)703; SI-NEXT: s_mov_b32 s4, 0x7f800000704; SI-NEXT: v_frexp_mant_f32_e64 v1, -|v0|705; SI-NEXT: v_cmp_lt_f32_e64 s[4:5], |v0|, s4706; SI-NEXT: v_cndmask_b32_e64 v1, -|v0|, v1, s[4:5]707; SI-NEXT: v_rcp_f32_e32 v1, v1708; SI-NEXT: v_frexp_exp_i32_f32_e32 v0, v0709; SI-NEXT: v_sub_i32_e32 v0, vcc, 0, v0710; SI-NEXT: v_ldexp_f32_e32 v0, v1, v0711; SI-NEXT: s_setpc_b64 s[30:31]712;713; VI-LABEL: v_rcp_neg_fabs_f32_ieee_ulp25:714; VI: ; %bb.0:715; VI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)716; VI-NEXT: v_frexp_mant_f32_e64 v1, -|v0|717; VI-NEXT: v_rcp_f32_e32 v1, v1718; VI-NEXT: v_frexp_exp_i32_f32_e32 v0, v0719; VI-NEXT: v_sub_u32_e32 v0, vcc, 0, v0720; VI-NEXT: v_ldexp_f32 v0, v1, v0721; VI-NEXT: s_setpc_b64 s[30:31]722;723; R600-LABEL: v_rcp_neg_fabs_f32_ieee_ulp25:724; R600: ; %bb.0:725; R600-NEXT: CF_END726; R600-NEXT: PAD727 %fabs.x = call float @llvm.fabs.f32(float %x)728 %rcp = fdiv float -1.0, %fabs.x, !fpmath !0729 ret float %rcp730}731 732define float @v_rcp_neg_fabs_f32_daz_ulp25(float %x) #0 {733; GCN-LABEL: v_rcp_neg_fabs_f32_daz_ulp25:734; GCN: ; %bb.0:735; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)736; GCN-NEXT: v_rcp_f32_e64 v0, -|v0|737; GCN-NEXT: s_setpc_b64 s[30:31]738;739; R600-LABEL: v_rcp_neg_fabs_f32_daz_ulp25:740; R600: ; %bb.0:741; R600-NEXT: CF_END742; R600-NEXT: PAD743 %fabs.x = call float @llvm.fabs.f32(float %x)744 %rcp = fdiv float -1.0, %fabs.x, !fpmath !0745 ret float %rcp746}747 748define amdgpu_kernel void @s_rcp_pat_f32_daz(ptr addrspace(1) %out, float %src) #0 {749; SI-LABEL: s_rcp_pat_f32_daz:750; SI: ; %bb.0:751; SI-NEXT: s_load_dword s2, s[4:5], 0xb752; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9753; SI-NEXT: s_mov_b32 s3, 0xf000754; SI-NEXT: s_waitcnt lgkmcnt(0)755; SI-NEXT: v_rcp_f32_e32 v0, s2756; SI-NEXT: s_mov_b32 s2, -1757; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0758; SI-NEXT: s_endpgm759;760; VI-LABEL: s_rcp_pat_f32_daz:761; VI: ; %bb.0:762; VI-NEXT: s_load_dword s2, s[4:5], 0x2c763; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24764; VI-NEXT: s_waitcnt lgkmcnt(0)765; VI-NEXT: v_rcp_f32_e32 v2, s2766; VI-NEXT: v_mov_b32_e32 v0, s0767; VI-NEXT: v_mov_b32_e32 v1, s1768; VI-NEXT: flat_store_dword v[0:1], v2769; VI-NEXT: s_endpgm770;771; EG-LABEL: s_rcp_pat_f32_daz:772; EG: ; %bb.0:773; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]774; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1775; EG-NEXT: CF_END776; EG-NEXT: PAD777; EG-NEXT: ALU clause starting at 4:778; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x,779; EG-NEXT: RECIP_IEEE * T1.X, KC0[2].Z,780; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)781;782; CM-LABEL: s_rcp_pat_f32_daz:783; CM: ; %bb.0:784; CM-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[]785; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X786; CM-NEXT: CF_END787; CM-NEXT: PAD788; CM-NEXT: ALU clause starting at 4:789; CM-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,790; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)791; CM-NEXT: RECIP_IEEE T1.X, KC0[2].Z,792; CM-NEXT: RECIP_IEEE T1.Y (MASKED), KC0[2].Z,793; CM-NEXT: RECIP_IEEE T1.Z (MASKED), KC0[2].Z,794; CM-NEXT: RECIP_IEEE * T1.W (MASKED), KC0[2].Z,795 %rcp = fdiv float 1.0, %src, !fpmath !0796 store float %rcp, ptr addrspace(1) %out, align 4797 ret void798}799 800define amdgpu_kernel void @s_rcp_ulp25_pat_f32_daz(ptr addrspace(1) %out, float %src) #0 {801; SI-LABEL: s_rcp_ulp25_pat_f32_daz:802; SI: ; %bb.0:803; SI-NEXT: s_load_dword s2, s[4:5], 0xb804; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9805; SI-NEXT: s_mov_b32 s3, 0xf000806; SI-NEXT: s_waitcnt lgkmcnt(0)807; SI-NEXT: v_rcp_f32_e32 v0, s2808; SI-NEXT: s_mov_b32 s2, -1809; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0810; SI-NEXT: s_endpgm811;812; VI-LABEL: s_rcp_ulp25_pat_f32_daz:813; VI: ; %bb.0:814; VI-NEXT: s_load_dword s2, s[4:5], 0x2c815; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24816; VI-NEXT: s_waitcnt lgkmcnt(0)817; VI-NEXT: v_rcp_f32_e32 v2, s2818; VI-NEXT: v_mov_b32_e32 v0, s0819; VI-NEXT: v_mov_b32_e32 v1, s1820; VI-NEXT: flat_store_dword v[0:1], v2821; VI-NEXT: s_endpgm822;823; EG-LABEL: s_rcp_ulp25_pat_f32_daz:824; EG: ; %bb.0:825; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]826; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1827; EG-NEXT: CF_END828; EG-NEXT: PAD829; EG-NEXT: ALU clause starting at 4:830; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x,831; EG-NEXT: RECIP_IEEE * T1.X, KC0[2].Z,832; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)833;834; CM-LABEL: s_rcp_ulp25_pat_f32_daz:835; CM: ; %bb.0:836; CM-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[]837; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X838; CM-NEXT: CF_END839; CM-NEXT: PAD840; CM-NEXT: ALU clause starting at 4:841; CM-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,842; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)843; CM-NEXT: RECIP_IEEE T1.X, KC0[2].Z,844; CM-NEXT: RECIP_IEEE T1.Y (MASKED), KC0[2].Z,845; CM-NEXT: RECIP_IEEE T1.Z (MASKED), KC0[2].Z,846; CM-NEXT: RECIP_IEEE * T1.W (MASKED), KC0[2].Z,847 %rcp = fdiv float 1.0, %src, !fpmath !0848 store float %rcp, ptr addrspace(1) %out, align 4849 ret void850}851 852define amdgpu_kernel void @s_rcp_fast_ulp25_pat_f32_daz(ptr addrspace(1) %out, float %src) #0 {853; SI-LABEL: s_rcp_fast_ulp25_pat_f32_daz:854; SI: ; %bb.0:855; SI-NEXT: s_load_dword s2, s[4:5], 0xb856; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9857; SI-NEXT: s_mov_b32 s3, 0xf000858; SI-NEXT: s_waitcnt lgkmcnt(0)859; SI-NEXT: v_rcp_f32_e32 v0, s2860; SI-NEXT: s_mov_b32 s2, -1861; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0862; SI-NEXT: s_endpgm863;864; VI-LABEL: s_rcp_fast_ulp25_pat_f32_daz:865; VI: ; %bb.0:866; VI-NEXT: s_load_dword s2, s[4:5], 0x2c867; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24868; VI-NEXT: s_waitcnt lgkmcnt(0)869; VI-NEXT: v_rcp_f32_e32 v2, s2870; VI-NEXT: v_mov_b32_e32 v0, s0871; VI-NEXT: v_mov_b32_e32 v1, s1872; VI-NEXT: flat_store_dword v[0:1], v2873; VI-NEXT: s_endpgm874;875; EG-LABEL: s_rcp_fast_ulp25_pat_f32_daz:876; EG: ; %bb.0:877; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]878; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1879; EG-NEXT: CF_END880; EG-NEXT: PAD881; EG-NEXT: ALU clause starting at 4:882; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x,883; EG-NEXT: RECIP_IEEE * T1.X, KC0[2].Z,884; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)885;886; CM-LABEL: s_rcp_fast_ulp25_pat_f32_daz:887; CM: ; %bb.0:888; CM-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[]889; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X890; CM-NEXT: CF_END891; CM-NEXT: PAD892; CM-NEXT: ALU clause starting at 4:893; CM-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,894; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)895; CM-NEXT: RECIP_IEEE T1.X, KC0[2].Z,896; CM-NEXT: RECIP_IEEE T1.Y (MASKED), KC0[2].Z,897; CM-NEXT: RECIP_IEEE T1.Z (MASKED), KC0[2].Z,898; CM-NEXT: RECIP_IEEE * T1.W (MASKED), KC0[2].Z,899 %rcp = fdiv fast float 1.0, %src, !fpmath !0900 store float %rcp, ptr addrspace(1) %out, align 4901 ret void902}903 904define amdgpu_kernel void @s_rcp_arcp_ulp25_pat_f32_daz(ptr addrspace(1) %out, float %src) #0 {905; SI-LABEL: s_rcp_arcp_ulp25_pat_f32_daz:906; SI: ; %bb.0:907; SI-NEXT: s_load_dword s2, s[4:5], 0xb908; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9909; SI-NEXT: s_mov_b32 s3, 0xf000910; SI-NEXT: s_waitcnt lgkmcnt(0)911; SI-NEXT: v_rcp_f32_e32 v0, s2912; SI-NEXT: s_mov_b32 s2, -1913; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0914; SI-NEXT: s_endpgm915;916; VI-LABEL: s_rcp_arcp_ulp25_pat_f32_daz:917; VI: ; %bb.0:918; VI-NEXT: s_load_dword s2, s[4:5], 0x2c919; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24920; VI-NEXT: s_waitcnt lgkmcnt(0)921; VI-NEXT: v_rcp_f32_e32 v2, s2922; VI-NEXT: v_mov_b32_e32 v0, s0923; VI-NEXT: v_mov_b32_e32 v1, s1924; VI-NEXT: flat_store_dword v[0:1], v2925; VI-NEXT: s_endpgm926;927; EG-LABEL: s_rcp_arcp_ulp25_pat_f32_daz:928; EG: ; %bb.0:929; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]930; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1931; EG-NEXT: CF_END932; EG-NEXT: PAD933; EG-NEXT: ALU clause starting at 4:934; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x,935; EG-NEXT: RECIP_IEEE * T1.X, KC0[2].Z,936; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)937;938; CM-LABEL: s_rcp_arcp_ulp25_pat_f32_daz:939; CM: ; %bb.0:940; CM-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[]941; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X942; CM-NEXT: CF_END943; CM-NEXT: PAD944; CM-NEXT: ALU clause starting at 4:945; CM-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,946; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)947; CM-NEXT: RECIP_IEEE T1.X, KC0[2].Z,948; CM-NEXT: RECIP_IEEE T1.Y (MASKED), KC0[2].Z,949; CM-NEXT: RECIP_IEEE T1.Z (MASKED), KC0[2].Z,950; CM-NEXT: RECIP_IEEE * T1.W (MASKED), KC0[2].Z,951 %rcp = fdiv arcp float 1.0, %src, !fpmath !0952 store float %rcp, ptr addrspace(1) %out, align 4953 ret void954}955 956define amdgpu_kernel void @s_rcp_global_fast_ulp25_pat_f32_daz(ptr addrspace(1) %out, float %src) #2 {957; SI-LABEL: s_rcp_global_fast_ulp25_pat_f32_daz:958; SI: ; %bb.0:959; SI-NEXT: s_load_dword s2, s[4:5], 0xb960; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9961; SI-NEXT: s_mov_b32 s3, 0xf000962; SI-NEXT: s_waitcnt lgkmcnt(0)963; SI-NEXT: v_rcp_f32_e32 v0, s2964; SI-NEXT: s_mov_b32 s2, -1965; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0966; SI-NEXT: s_endpgm967;968; VI-LABEL: s_rcp_global_fast_ulp25_pat_f32_daz:969; VI: ; %bb.0:970; VI-NEXT: s_load_dword s2, s[4:5], 0x2c971; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24972; VI-NEXT: s_waitcnt lgkmcnt(0)973; VI-NEXT: v_rcp_f32_e32 v2, s2974; VI-NEXT: v_mov_b32_e32 v0, s0975; VI-NEXT: v_mov_b32_e32 v1, s1976; VI-NEXT: flat_store_dword v[0:1], v2977; VI-NEXT: s_endpgm978;979; EG-LABEL: s_rcp_global_fast_ulp25_pat_f32_daz:980; EG: ; %bb.0:981; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]982; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1983; EG-NEXT: CF_END984; EG-NEXT: PAD985; EG-NEXT: ALU clause starting at 4:986; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x,987; EG-NEXT: RECIP_IEEE * T1.X, KC0[2].Z,988; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)989;990; CM-LABEL: s_rcp_global_fast_ulp25_pat_f32_daz:991; CM: ; %bb.0:992; CM-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[]993; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X994; CM-NEXT: CF_END995; CM-NEXT: PAD996; CM-NEXT: ALU clause starting at 4:997; CM-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,998; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)999; CM-NEXT: RECIP_IEEE T1.X, KC0[2].Z,1000; CM-NEXT: RECIP_IEEE T1.Y (MASKED), KC0[2].Z,1001; CM-NEXT: RECIP_IEEE T1.Z (MASKED), KC0[2].Z,1002; CM-NEXT: RECIP_IEEE * T1.W (MASKED), KC0[2].Z,1003 %rcp = fdiv float 1.0, %src, !fpmath !01004 store float %rcp, ptr addrspace(1) %out, align 41005 ret void1006}1007 1008define amdgpu_kernel void @s_rcp_fabs_pat_f32_daz(ptr addrspace(1) %out, float %src) #0 {1009; SI-LABEL: s_rcp_fabs_pat_f32_daz:1010; SI: ; %bb.0:1011; SI-NEXT: s_load_dword s2, s[4:5], 0xb1012; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91013; SI-NEXT: s_mov_b32 s3, 0xf0001014; SI-NEXT: s_waitcnt lgkmcnt(0)1015; SI-NEXT: v_rcp_f32_e64 v0, |s2|1016; SI-NEXT: s_mov_b32 s2, -11017; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01018; SI-NEXT: s_endpgm1019;1020; VI-LABEL: s_rcp_fabs_pat_f32_daz:1021; VI: ; %bb.0:1022; VI-NEXT: s_load_dword s2, s[4:5], 0x2c1023; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241024; VI-NEXT: s_waitcnt lgkmcnt(0)1025; VI-NEXT: v_rcp_f32_e64 v2, |s2|1026; VI-NEXT: v_mov_b32_e32 v0, s01027; VI-NEXT: v_mov_b32_e32 v1, s11028; VI-NEXT: flat_store_dword v[0:1], v21029; VI-NEXT: s_endpgm1030;1031; EG-LABEL: s_rcp_fabs_pat_f32_daz:1032; EG: ; %bb.0:1033; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]1034; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 11035; EG-NEXT: CF_END1036; EG-NEXT: PAD1037; EG-NEXT: ALU clause starting at 4:1038; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x,1039; EG-NEXT: RECIP_IEEE * T1.X, |KC0[2].Z|,1040; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1041;1042; CM-LABEL: s_rcp_fabs_pat_f32_daz:1043; CM: ; %bb.0:1044; CM-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[]1045; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T0.X1046; CM-NEXT: CF_END1047; CM-NEXT: PAD1048; CM-NEXT: ALU clause starting at 4:1049; CM-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,1050; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)1051; CM-NEXT: RECIP_IEEE T1.X, |KC0[2].Z|,1052; CM-NEXT: RECIP_IEEE T1.Y (MASKED), |KC0[2].Z|,1053; CM-NEXT: RECIP_IEEE T1.Z (MASKED), |KC0[2].Z|,1054; CM-NEXT: RECIP_IEEE * T1.W (MASKED), |KC0[2].Z|,1055 %src.fabs = call float @llvm.fabs.f32(float %src)1056 %rcp = fdiv float 1.0, %src.fabs, !fpmath !01057 store float %rcp, ptr addrspace(1) %out, align 41058 ret void1059}1060 1061define amdgpu_kernel void @s_neg_rcp_pat_f32_daz(ptr addrspace(1) %out, float %src) #0 {1062; SI-LABEL: s_neg_rcp_pat_f32_daz:1063; SI: ; %bb.0:1064; SI-NEXT: s_load_dword s2, s[4:5], 0xb1065; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91066; SI-NEXT: s_mov_b32 s3, 0xf0001067; SI-NEXT: s_waitcnt lgkmcnt(0)1068; SI-NEXT: v_rcp_f32_e64 v0, -s21069; SI-NEXT: s_mov_b32 s2, -11070; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01071; SI-NEXT: s_endpgm1072;1073; VI-LABEL: s_neg_rcp_pat_f32_daz:1074; VI: ; %bb.0:1075; VI-NEXT: s_load_dword s2, s[4:5], 0x2c1076; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241077; VI-NEXT: s_waitcnt lgkmcnt(0)1078; VI-NEXT: v_rcp_f32_e64 v2, -s21079; VI-NEXT: v_mov_b32_e32 v0, s01080; VI-NEXT: v_mov_b32_e32 v1, s11081; VI-NEXT: flat_store_dword v[0:1], v21082; VI-NEXT: s_endpgm1083;1084; EG-LABEL: s_neg_rcp_pat_f32_daz:1085; EG: ; %bb.0:1086; EG-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]1087; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 11088; EG-NEXT: CF_END1089; EG-NEXT: PAD1090; EG-NEXT: ALU clause starting at 4:1091; EG-NEXT: RECIP_IEEE * T0.X, KC0[2].Z,1092; EG-NEXT: MUL_IEEE T0.X, literal.x, PS,1093; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,1094; EG-NEXT: -1082130432(-1.000000e+00), 2(2.802597e-45)1095;1096; CM-LABEL: s_neg_rcp_pat_f32_daz:1097; CM: ; %bb.0:1098; CM-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[]1099; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X1100; CM-NEXT: CF_END1101; CM-NEXT: PAD1102; CM-NEXT: ALU clause starting at 4:1103; CM-NEXT: RECIP_IEEE T0.X, KC0[2].Z,1104; CM-NEXT: RECIP_IEEE T0.Y (MASKED), KC0[2].Z,1105; CM-NEXT: RECIP_IEEE T0.Z (MASKED), KC0[2].Z,1106; CM-NEXT: RECIP_IEEE * T0.W (MASKED), KC0[2].Z,1107; CM-NEXT: MUL_IEEE * T0.X, literal.x, PV.X,1108; CM-NEXT: -1082130432(-1.000000e+00), 0(0.000000e+00)1109; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1110; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)1111 %rcp = fdiv float -1.0, %src, !fpmath !01112 store float %rcp, ptr addrspace(1) %out, align 41113 ret void1114}1115 1116define amdgpu_kernel void @s_rcp_fabs_fneg_pat_f32_daz(ptr addrspace(1) %out, float %src) #0 {1117; SI-LABEL: s_rcp_fabs_fneg_pat_f32_daz:1118; SI: ; %bb.0:1119; SI-NEXT: s_load_dword s2, s[4:5], 0xb1120; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91121; SI-NEXT: s_mov_b32 s3, 0xf0001122; SI-NEXT: s_waitcnt lgkmcnt(0)1123; SI-NEXT: v_rcp_f32_e64 v0, -|s2|1124; SI-NEXT: s_mov_b32 s2, -11125; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01126; SI-NEXT: s_endpgm1127;1128; VI-LABEL: s_rcp_fabs_fneg_pat_f32_daz:1129; VI: ; %bb.0:1130; VI-NEXT: s_load_dword s2, s[4:5], 0x2c1131; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241132; VI-NEXT: s_waitcnt lgkmcnt(0)1133; VI-NEXT: v_rcp_f32_e64 v2, -|s2|1134; VI-NEXT: v_mov_b32_e32 v0, s01135; VI-NEXT: v_mov_b32_e32 v1, s11136; VI-NEXT: flat_store_dword v[0:1], v21137; VI-NEXT: s_endpgm1138;1139; EG-LABEL: s_rcp_fabs_fneg_pat_f32_daz:1140; EG: ; %bb.0:1141; EG-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]1142; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 11143; EG-NEXT: CF_END1144; EG-NEXT: PAD1145; EG-NEXT: ALU clause starting at 4:1146; EG-NEXT: RECIP_IEEE * T0.X, |KC0[2].Z|,1147; EG-NEXT: MUL_IEEE T0.X, literal.x, PS,1148; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,1149; EG-NEXT: -1082130432(-1.000000e+00), 2(2.802597e-45)1150;1151; CM-LABEL: s_rcp_fabs_fneg_pat_f32_daz:1152; CM: ; %bb.0:1153; CM-NEXT: ALU 7, @4, KC0[CB0:0-32], KC1[]1154; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X1155; CM-NEXT: CF_END1156; CM-NEXT: PAD1157; CM-NEXT: ALU clause starting at 4:1158; CM-NEXT: RECIP_IEEE T0.X, |KC0[2].Z|,1159; CM-NEXT: RECIP_IEEE T0.Y (MASKED), |KC0[2].Z|,1160; CM-NEXT: RECIP_IEEE T0.Z (MASKED), |KC0[2].Z|,1161; CM-NEXT: RECIP_IEEE * T0.W (MASKED), |KC0[2].Z|,1162; CM-NEXT: MUL_IEEE * T0.X, literal.x, PV.X,1163; CM-NEXT: -1082130432(-1.000000e+00), 0(0.000000e+00)1164; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1165; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)1166 %src.fabs = call float @llvm.fabs.f32(float %src)1167 %src.fabs.fneg = fneg float %src.fabs1168 %rcp = fdiv float 1.0, %src.fabs.fneg, !fpmath !01169 store float %rcp, ptr addrspace(1) %out, align 41170 ret void1171}1172 1173define amdgpu_kernel void @s_rcp_fabs_fneg_pat_multi_use_f32_daz(ptr addrspace(1) %out, float %src) #0 {1174; SI-LABEL: s_rcp_fabs_fneg_pat_multi_use_f32_daz:1175; SI: ; %bb.0:1176; SI-NEXT: s_load_dword s6, s[4:5], 0xb1177; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91178; SI-NEXT: s_mov_b32 s3, 0xf0001179; SI-NEXT: s_mov_b32 s2, -11180; SI-NEXT: s_waitcnt lgkmcnt(0)1181; SI-NEXT: v_rcp_f32_e64 v0, -|s6|1182; SI-NEXT: v_mul_f32_e64 v1, s6, -|s6|1183; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01184; SI-NEXT: s_waitcnt vmcnt(0)1185; SI-NEXT: buffer_store_dword v1, off, s[0:3], 01186; SI-NEXT: s_waitcnt vmcnt(0)1187; SI-NEXT: s_endpgm1188;1189; VI-LABEL: s_rcp_fabs_fneg_pat_multi_use_f32_daz:1190; VI: ; %bb.0:1191; VI-NEXT: s_load_dword s2, s[4:5], 0x2c1192; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241193; VI-NEXT: s_waitcnt lgkmcnt(0)1194; VI-NEXT: v_rcp_f32_e64 v2, -|s2|1195; VI-NEXT: v_mov_b32_e32 v0, s01196; VI-NEXT: v_mov_b32_e32 v1, s11197; VI-NEXT: v_mul_f32_e64 v3, s2, -|s2|1198; VI-NEXT: flat_store_dword v[0:1], v21199; VI-NEXT: s_waitcnt vmcnt(0)1200; VI-NEXT: flat_store_dword v[0:1], v31201; VI-NEXT: s_waitcnt vmcnt(0)1202; VI-NEXT: s_endpgm1203;1204; EG-LABEL: s_rcp_fabs_fneg_pat_multi_use_f32_daz:1205; EG: ; %bb.0:1206; EG-NEXT: ALU 4, @4, KC0[CB0:0-32], KC1[]1207; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T2.X, 01208; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T2.X, 11209; EG-NEXT: CF_END1210; EG-NEXT: ALU clause starting at 4:1211; EG-NEXT: MUL_IEEE T0.X, KC0[2].Z, -|KC0[2].Z|,1212; EG-NEXT: RECIP_IEEE * T0.Y, |KC0[2].Z|,1213; EG-NEXT: MUL_IEEE T1.X, literal.x, PS,1214; EG-NEXT: LSHR * T2.X, KC0[2].Y, literal.y,1215; EG-NEXT: -1082130432(-1.000000e+00), 2(2.802597e-45)1216;1217; CM-LABEL: s_rcp_fabs_fneg_pat_multi_use_f32_daz:1218; CM: ; %bb.0:1219; CM-NEXT: ALU 8, @4, KC0[CB0:0-32], KC1[]1220; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T1.X, T2.X1221; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T2.X1222; CM-NEXT: CF_END1223; CM-NEXT: ALU clause starting at 4:1224; CM-NEXT: MUL_IEEE * T0.X, KC0[2].Z, -|KC0[2].Z|,1225; CM-NEXT: RECIP_IEEE T0.X (MASKED), |KC0[2].Z|,1226; CM-NEXT: RECIP_IEEE T0.Y, |KC0[2].Z|,1227; CM-NEXT: RECIP_IEEE T0.Z (MASKED), |KC0[2].Z|,1228; CM-NEXT: RECIP_IEEE * T0.W (MASKED), |KC0[2].Z|,1229; CM-NEXT: MUL_IEEE * T1.X, literal.x, PV.Y,1230; CM-NEXT: -1082130432(-1.000000e+00), 0(0.000000e+00)1231; CM-NEXT: LSHR * T2.X, KC0[2].Y, literal.x,1232; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)1233 %src.fabs = call float @llvm.fabs.f32(float %src)1234 %src.fabs.fneg = fneg float %src.fabs1235 %rcp = fdiv float 1.0, %src.fabs.fneg, !fpmath !01236 store volatile float %rcp, ptr addrspace(1) %out, align 41237 1238 %other = fmul float %src, %src.fabs.fneg1239 store volatile float %other, ptr addrspace(1) %out, align 41240 ret void1241}1242 1243define amdgpu_kernel void @s_div_arcp_2_x_pat_f32_daz(ptr addrspace(1) %out) #0 {1244; SI-LABEL: s_div_arcp_2_x_pat_f32_daz:1245; SI: ; %bb.0:1246; SI-NEXT: s_load_dword s6, s[0:1], 0x01247; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91248; SI-NEXT: s_mov_b32 s3, 0xf0001249; SI-NEXT: s_mov_b32 s2, -11250; SI-NEXT: s_waitcnt lgkmcnt(0)1251; SI-NEXT: v_mul_f32_e64 v0, s6, 0.51252; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01253; SI-NEXT: s_endpgm1254;1255; VI-LABEL: s_div_arcp_2_x_pat_f32_daz:1256; VI: ; %bb.0:1257; VI-NEXT: s_load_dword s2, s[0:1], 0x01258; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241259; VI-NEXT: s_waitcnt lgkmcnt(0)1260; VI-NEXT: v_mul_f32_e64 v2, s2, 0.51261; VI-NEXT: v_mov_b32_e32 v0, s01262; VI-NEXT: v_mov_b32_e32 v1, s11263; VI-NEXT: flat_store_dword v[0:1], v21264; VI-NEXT: s_endpgm1265;1266; EG-LABEL: s_div_arcp_2_x_pat_f32_daz:1267; EG: ; %bb.0:1268; EG-NEXT: TEX 0 @41269; EG-NEXT: ALU 2, @6, KC0[CB0:0-32], KC1[]1270; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 11271; EG-NEXT: CF_END1272; EG-NEXT: Fetch clause starting at 4:1273; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #11274; EG-NEXT: ALU clause starting at 6:1275; EG-NEXT: MUL_IEEE T0.X, T0.X, 0.5,1276; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1277; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)1278;1279; CM-LABEL: s_div_arcp_2_x_pat_f32_daz:1280; CM: ; %bb.0:1281; CM-NEXT: TEX 0 @41282; CM-NEXT: ALU 2, @6, KC0[CB0:0-32], KC1[]1283; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X1284; CM-NEXT: CF_END1285; CM-NEXT: Fetch clause starting at 4:1286; CM-NEXT: VTX_READ_32 T0.X, T0.X, 0, #11287; CM-NEXT: ALU clause starting at 6:1288; CM-NEXT: MUL_IEEE * T0.X, T0.X, 0.5,1289; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1290; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)1291 %x = load float, ptr addrspace(1) poison1292 %rcp = fdiv arcp float %x, 2.01293 store float %rcp, ptr addrspace(1) %out, align 41294 ret void1295}1296 1297define amdgpu_kernel void @s_div_arcp_k_x_pat_f32_daz(ptr addrspace(1) %out) #0 {1298; SI-LABEL: s_div_arcp_k_x_pat_f32_daz:1299; SI: ; %bb.0:1300; SI-NEXT: s_load_dword s6, s[0:1], 0x01301; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91302; SI-NEXT: v_mov_b32_e32 v0, 0x3dcccccd1303; SI-NEXT: s_mov_b32 s3, 0xf0001304; SI-NEXT: s_mov_b32 s2, -11305; SI-NEXT: s_waitcnt lgkmcnt(0)1306; SI-NEXT: v_mul_f32_e32 v0, s6, v01307; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01308; SI-NEXT: s_endpgm1309;1310; VI-LABEL: s_div_arcp_k_x_pat_f32_daz:1311; VI: ; %bb.0:1312; VI-NEXT: s_load_dword s2, s[0:1], 0x01313; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241314; VI-NEXT: v_mov_b32_e32 v0, 0x3dcccccd1315; VI-NEXT: s_waitcnt lgkmcnt(0)1316; VI-NEXT: v_mul_f32_e32 v2, s2, v01317; VI-NEXT: v_mov_b32_e32 v0, s01318; VI-NEXT: v_mov_b32_e32 v1, s11319; VI-NEXT: flat_store_dword v[0:1], v21320; VI-NEXT: s_endpgm1321;1322; EG-LABEL: s_div_arcp_k_x_pat_f32_daz:1323; EG: ; %bb.0:1324; EG-NEXT: TEX 0 @41325; EG-NEXT: ALU 2, @6, KC0[CB0:0-32], KC1[]1326; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 11327; EG-NEXT: CF_END1328; EG-NEXT: Fetch clause starting at 4:1329; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #11330; EG-NEXT: ALU clause starting at 6:1331; EG-NEXT: MUL_IEEE T0.X, T0.X, literal.x,1332; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,1333; EG-NEXT: 1036831949(1.000000e-01), 2(2.802597e-45)1334;1335; CM-LABEL: s_div_arcp_k_x_pat_f32_daz:1336; CM: ; %bb.0:1337; CM-NEXT: TEX 0 @41338; CM-NEXT: ALU 3, @6, KC0[CB0:0-32], KC1[]1339; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X1340; CM-NEXT: CF_END1341; CM-NEXT: Fetch clause starting at 4:1342; CM-NEXT: VTX_READ_32 T0.X, T0.X, 0, #11343; CM-NEXT: ALU clause starting at 6:1344; CM-NEXT: MUL_IEEE * T0.X, T0.X, literal.x,1345; CM-NEXT: 1036831949(1.000000e-01), 0(0.000000e+00)1346; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1347; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)1348 %x = load float, ptr addrspace(1) poison1349 %rcp = fdiv arcp float %x, 10.01350 store float %rcp, ptr addrspace(1) %out, align 41351 ret void1352}1353 1354define amdgpu_kernel void @s_div_arcp_neg_k_x_pat_f32_daz(ptr addrspace(1) %out) #0 {1355; SI-LABEL: s_div_arcp_neg_k_x_pat_f32_daz:1356; SI: ; %bb.0:1357; SI-NEXT: s_load_dword s6, s[0:1], 0x01358; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x91359; SI-NEXT: v_mov_b32_e32 v0, 0xbdcccccd1360; SI-NEXT: s_mov_b32 s3, 0xf0001361; SI-NEXT: s_mov_b32 s2, -11362; SI-NEXT: s_waitcnt lgkmcnt(0)1363; SI-NEXT: v_mul_f32_e32 v0, s6, v01364; SI-NEXT: buffer_store_dword v0, off, s[0:3], 01365; SI-NEXT: s_endpgm1366;1367; VI-LABEL: s_div_arcp_neg_k_x_pat_f32_daz:1368; VI: ; %bb.0:1369; VI-NEXT: s_load_dword s2, s[0:1], 0x01370; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x241371; VI-NEXT: v_mov_b32_e32 v0, 0xbdcccccd1372; VI-NEXT: s_waitcnt lgkmcnt(0)1373; VI-NEXT: v_mul_f32_e32 v2, s2, v01374; VI-NEXT: v_mov_b32_e32 v0, s01375; VI-NEXT: v_mov_b32_e32 v1, s11376; VI-NEXT: flat_store_dword v[0:1], v21377; VI-NEXT: s_endpgm1378;1379; EG-LABEL: s_div_arcp_neg_k_x_pat_f32_daz:1380; EG: ; %bb.0:1381; EG-NEXT: TEX 0 @41382; EG-NEXT: ALU 2, @6, KC0[CB0:0-32], KC1[]1383; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 11384; EG-NEXT: CF_END1385; EG-NEXT: Fetch clause starting at 4:1386; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #11387; EG-NEXT: ALU clause starting at 6:1388; EG-NEXT: MUL_IEEE T0.X, T0.X, literal.x,1389; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,1390; EG-NEXT: -1110651699(-1.000000e-01), 2(2.802597e-45)1391;1392; CM-LABEL: s_div_arcp_neg_k_x_pat_f32_daz:1393; CM: ; %bb.0:1394; CM-NEXT: TEX 0 @41395; CM-NEXT: ALU 3, @6, KC0[CB0:0-32], KC1[]1396; CM-NEXT: MEM_RAT_CACHELESS STORE_DWORD T0.X, T1.X1397; CM-NEXT: CF_END1398; CM-NEXT: Fetch clause starting at 4:1399; CM-NEXT: VTX_READ_32 T0.X, T0.X, 0, #11400; CM-NEXT: ALU clause starting at 6:1401; CM-NEXT: MUL_IEEE * T0.X, T0.X, literal.x,1402; CM-NEXT: -1110651699(-1.000000e-01), 0(0.000000e+00)1403; CM-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,1404; CM-NEXT: 2(2.802597e-45), 0(0.000000e+00)1405 %x = load float, ptr addrspace(1) poison1406 %rcp = fdiv arcp float %x, -10.01407 store float %rcp, ptr addrspace(1) %out, align 41408 ret void1409}1410 1411declare float @llvm.fabs.f32(float) #11412declare float @llvm.sqrt.f32(float) #11413 1414attributes #0 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" }1415attributes #1 = { nounwind readnone }1416attributes #2 = { nounwind "denormal-fp-math-f32"="preserve-sign,preserve-sign" }1417attributes #3 = { nounwind "denormal-fp-math-f32"="ieee,ieee" }1418attributes #4 = { nounwind "denormal-fp-math-f32"="ieee,ieee" }1419 1420!0 = !{float 2.500000e+00}1421